ST PeakSHDSL User Manual

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PeakSHDSL 8 CHANNEL CENTRAL OFFICE CHIPSET

DESCRIPTION

The 8-channel SHDSL chipset from S TM icroelec­tronics provides a complete low-power, low cost
solution for Central Office (CO) SHDSL solutions.
The chipset integrates all SHDS L functions from
Utopia interface to the line in three devices:

■ STLC80815: 8 channel SHDSL data pump

(SHDSL Transceiver)

■ STLC60444: 4 channel SHDSL Analog front

end

■ TS615: Dual wide band operational amplifier

with high output current

The product is targeted for customers looking to
build cost effective central office sol utions, i nclud­ing Digital Subscriber Line Access Multiplexers
(DSLAM) and Digital Loop Carriers (DLC).

PeakSHDSL

PRODUCT BRIEF

PBGA-272 package
for
STLC80815 device

EFBGA216 package
for
STLC60444 device

TSSOP14 package
for
TS615 device

CHIPSET ARCHITECTURE OVERVIEW
Figure 1. Chipset Architecture Overview

Flash ROM Host CPU SDRAM

Utopia

ATM

Octal SHDSL

PCM Highway

8

transceiver

PCM

Serial boot & management interface

Quad SHDSL

AFE

Quad SHDSL

AFE

Line driver &

hybrid

Line driver &

hybrid

Line

I/F

Line

I/F

Loop

Loop

With less than 750 mWatt per chan nel, the Pe akSHDSL chi ps et is one of the mo st com petitive s olutions
for SHDSL central office applications.

May 2003

This is preliminary information on a new product now in development. Details are subject to change without notice.

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PeakSHDSL

STLC80815- 8 CHANNEL SHDSL DATA PUMP (SHDSL TRANSCEIVER)

Introduction

The STLC80815 includes eight indep endent transceive rs, which are optimized for central office applica­tion of Symmetrical Digital Subscriber Line (SHDSL) modems. The channels can operate simultaneously
in different modes and standards. It is an ideal integrated solution for central office equipment sensitive to
cost, power and space.

It includes full object code for a complete management/control and diagnostic API, and requires only pow­er up initialization from the host interface. This allows a single low-cost host processor to supports tens of
ports via a parallel or serial interface.

A "hostless" line card can be designed using the STLC80815. In this case a remote host can boot the chip
and manage it via a serial host interface or using the in-band ATM cells.

Each channel in this highly integrated device includes the following components : frame, a PAM receiver
and transmitter, a 512 state TCM decoder and a timing synthesizer. In addition the device includes a cen­tralized controller, which reduces to a minimum the requirements placed from the host, a Utopi a and a
PCM highway interface, which are common to all eight channels.

Figure 2. Block diagram of the STLC80815 SHDSL transceiver

Bitpump

(G.991.2

PCM x 8

PCM HW

NTR

PCM

TC

xDSL

Framer

(G.991.2

PMS-TC)

TPS-TC)

Modulator

Echo

Canceller

AFE Data

AFE

I/F

AFE Control

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Utopia

ATM

TC

TC

(G.991.2

TPS-TC)

Dedicated

Risc

Controller

DSP

Controller

512 states

TCM

Decoder

modulator

Host I/F

Host Serial I/F

De-

PLL

Host Parallel I/F

17.664MHz Clk

PeakSHDSL

Main features

■ Compatibility with: ITU G.991.2 (G.SHDSL), ITU G.994.1 (G.HS) and ETSI RE/TM-06011 (SDSL),

ANSI HDSL2 and HDSL4.

■ Supports four-wire operation

■ Extremely low power consumption per channel: <700mW for all ITU G.991.2 Annex B rates, masks and

loops.

■ Outstanding reach performance: Symmetrical rate of 1552kbps over 5.5 Km (18.0kft) for an ETSI

0.4mm cable.

■ Includes 512 states TCM decoder

■ Supports symmetrical rates from 192 kbps up to 2.3 Mbit/s in step of 8kbps

■ Includes an internal, flexible frequency synthesizer

■ Supports all G.991.2 clock modes, including synchronous and plesiochronous modes.

■ Support operation with NTR, External PLL or VCXO are not required

■ Includes a fully-featured flexible framer, which supports simultaneous ATM and PCM transmis sion

■ T1/E1 and in-band ISDN services are supported

■ Serial and parallel host interface

■

In-band ATM boot and management supporte d

■ Complete software control protocol stack/API

■ Boundary scan testing compliant to IEEE 1149.1 Join Test Action Group (JTAG)

■ 272-pin TPBGA272 package (27x27m m)

■ -40 to 85°C operation

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