ST NAND128-A, NAND256-A, NAND512-A, NAND01G-A User Manual
528 Byte/264 Word Page, 1.8 V/3V, NAND Flash Memories
FEATURES SUMMARY
NAND128-A, NAND256-A
NAND512-A, NAND01G-A
128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16)
■ HIGH DENSITY NAND FLASH MEMORIES
– Up to 1 Gbit memory array
– Up to 32 Mbit spare area
– Cost effective solutions for mass storage
applications
■ NAND INTE RFACE
– x8 or x16 bus width
– Multiplexed Address/ Data
– Pinout compatibility for all densities
■ SUPPLY VOLTAGE
– 1.8V device: V
– 3.0V device: V
■ PAGE SIZE
= 1.7 to 1.95V
DD
= 2.7 to 3.6V
DD
– x8 device: (512 + 16 spare) Bytes
– x16 device: (256 + 8 spare) Words
■ BLOCK SIZE
– x8 device: (16K + 512 spare) Bytes
– x16 device: (8K + 256 spare) Words
■ PAGE READ / PROGRAM
– Random access: 12µs (max)
– Sequential access: 50ns (min)
– Page program time: 200µs (typ)
■ COPY BACK PROGRAM MODE
– Fast page copy without external buffering
■ FAST BLOCK ERASE
– Block erase time: 2ms (Typ)
■ STATUS REGISTER
■ ELECTRONIC SIGNATURE
■ CHIP ENABLE ‘DON’T CARE’ OPTION
– Simple interface wit h microcontroller
■ SERIAL NUMBER OPTION
■ HARDWARE DATA PROTECTION
– Program/Erase locked during Power
transitions
Figure 1. Packages
TSOP48 12 x 20mm
USOP48 12 x 17 x 0.65mm
FBGA
VFBGA55 8 x 10 x 1mm
TFBGA55 8 x 10 x 1.2mm
VFBGA63 9 x 11 x 1mm
TFBGA63 9 x 11 x 1.2mm
■ DATA INTEGRITY
– 100,000 Program/Erase cycles
– 10 years Data Retention
■ RoHS COMPLIANCE
– Lead-Free Components are Compliant
with the RoHS Directive
■ DEVELOPMENT TOOLS
– Error Correction Code software and
hardware models
– Bad Blocks Management and Wear
Leveling algorithms
– File System OS Native refer ence sof tware
– Hardware simulation models
1/57February 2005
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Table 1. P r o du c t List
Reference Part Number
NAND128R3A
NAND128-A
NAND256-A
NAND512-A
NAND01G-A
NAND128W3A
NAND128R4A
NAND128W4A
NAND256R3A
NAND256W3A
NAND256R4A
NAND256W4A
NAND512R3A
NAND512W3A
NAND512R4A
NAND512W4A
NAND01GR3A
NAND01GW3A
NAND01GR4A
NAND01GW4A
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TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 1. Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Product Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. Logic Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. TSOP48 and USOP48 Connections, x8 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. TSOP48 and USOP48 Connections, x16 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. FBGA55 Connections, x8 devices (Top view through package) . . . . . . . . . . . . . . . . . . . 11
Figure 7. FBGA55 Connections, x16 devices (Top view through package). . . . . . . . . . . . . . . . . . 12
Figure 8. FBGA63 Connections, x8 devices (Top view through package) . . . . . . . . . . . . . . . . . . . 13
Figure 9. FBGA63 Connections, x16 devices (Top view through package). . . . . . . . . . . . . . . . . . 14
MEMORY ARRAY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Bad Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4. Valid Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10.Memory Array Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Inputs/Outputs (I/O0-I/O7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Inputs/Outputs (I/O8-I/O15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Chip Enable (E
Read Enable (R
Write Enable (W
Write Protect (WP
Ready/Busy (RB
V
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DD
V
Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SS
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Command Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7
Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Data Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7
Table 6. Address Insertion, x8 Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Table 7. Address Insertion, x16 Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 8. Address Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
COMMAND SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 9. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DEVICE OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Pointer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11.Pointer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 12.Pointer Operations for Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Read Memory Array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Random Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Page Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Sequential Row Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 13.Read (A,B,C) Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 14.Read Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 15.Sequential Row Read Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 16.Sequential Row Read Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5
Figure 17.Page Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Copy Back Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 10. Copy Back Program Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 18.Copy Back Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 19.Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Read Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Write Protection Bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
P/E/R Controller Bit (SR6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Error Bit (SR0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SR5, SR4, SR3, SR2 and SR1 are Reserved. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 11. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 12. Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SOFTWARE ALGORITHMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Bad Block Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Block Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 13. Block Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 20.Bad Block Management Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0
Figure 21.Garbage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Garbage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Wear-leveling Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Error Correction Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 22.Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Hardware Simulation Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
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Behavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
IBIS simulations models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 14. Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 33
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3
Table 15. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 16. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4
Table 17. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 18. DC Characteristics, 1.8V Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 19. DC Characteristics, 3V Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 20. AC Characteristics for Command, Address, Data Input . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 21. AC Characteristics for Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 23.Command Latch AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 24.Address Latch AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 25.Data Input Latch AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 26.Sequential Data Output after Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 27.Read Status Register AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 28.Read Electronic Signature AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 29.Page Read A/ Read B Operation AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 30.Read C Operation, One Page AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 31.Page Program AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 32.Block Erase AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 33.Reset AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Ready/Busy Signal Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 34.Ready/Busy AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 35.Ready/Busy Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 36.Resistor Value Versus Waveform Timings For Ready/Busy Signal . . . . . . . . . . . . . . . . 46
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 37.TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . . 47
Table 22. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 47
Figure 38.USOP48 – lead Plastic Ultra Thin Small Outline,12 x 17mm, Package Outline . . . . . . . 48
Table 23. USOP48 – lead Plastic Ultra Thin Small Outline, 12 x 17mm, Package Mechanical Data48
Figure 39.VFBGA55 8 x 10mm - 6x8 active ball array, 0.80mm pitch, Package Outline . . . . . . . . 49
Table 24. VFBGA55 8 x 10mm - 6x8 ball array, 0.80mm pitch, Package Mechanical Data . . . . . . 49
Figure 40.TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, Package Outline. . . . . . . . 50
Table 25. TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, Package Mechanical Data 50
Figure 41.VFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Outline . . . . . . . . . 51
Table 26. VFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data. . 51
Figure 42.TFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Outline. . . . . . . . . . 52
Table 27. TFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data . . 52
5/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 28. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
APPENDIX A.HARDWARE INTERFACE EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 43.Connection to Microcontroller, Without Glue Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 44.Connection to Microcontroller, With Glue Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 45.Building Storage Modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
RELATED DOCUMENTATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 29. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
6/57
SUMMARY DESCRIPTION
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
The NAND Flash 528 Byte/ 264 Word Page is a
family of non-volatile Flash memories that uses
the Single Level Cell (SLC) NAN D cell technology.
It is referred to as the Small Page family. The devices range from 128Mbits to 1Gbit and operate
with either a 1.8V or 3V voltage supply. The size of
a Page is either 528 Bytes (512 + 16 spare ) or 264
Words (256 + 8 spare) depending on whether the
device has a x8 or x16 bus width.
The address lines ar e multiplexed w ith the Data Input/Output signals on a multiplexed x8 or x16 Input/Output bus. This interface reduces the pin
count and makes it possible to migrate to other
densities without changing the footprint.
Each block can be programmed and erased over
100,000 cycles. To extend the lifetime of NAND
Flash devices it is strongly re commended to implement an Error Correction Code (ECC). A Write
Protect pin is available to give a hardware protection against program and erase operations.
The devices feature an open-drain Ready/Busy
output that can be used to identify if the Program/
Erase/Read (P/E/R) Controller is currently active.
The use of an open- drain output a llows the Ready/
Busy pins from several memo ries to be connect ed
to a single pull-up resistor.
A Copy Back command is availabl e to optimize the
management of defective blocks. When a Page
Program operation fails, the data can be programmed in another page without having to resend the data to be programmed.
The devices are available in the fol l owing pa ckages:
■ TSOP48 12 x 20mm for all products
■ USOP48 12 x 17 x 0.65mm for 128Mb, 256Mb
and 512Mb products
■ VFBGA55 (8 x 10 x 1mm, 6 x 8 ball array,
0.8mm pitch) for 128Mb and 256Mb products
■ TFBGA55 (8 x 10 x 1.2mm, 6 x 8 ball array,
0.8mm pitch) for 512Mb Dual Die product
■ VFBGA63 (9 x 11 x 1mm, 6 x 8 ball array,
0.8mm pitch) for the 512Mb product
■ TFBGA63 (9 x 11 x 1.2mm, 6 x 8 ball array,
0.8mm pitch) for the 1Gb Dual Die product
Two options are available for the NAND Flash
family:
Chip Enable Don’t Care, which allows code to be
directly downloaded by a microcontroller, as Chip
Enable transitions during the latency time do not
stop the read operation.
A Serial Number, which allows each device to be
uniquely identified. The Serial Number options is
subject to an NDA (Non Disclosure Agreement)
and so not described in the datasheet. For more
details of this option contact your near est ST Sales
office.
For information o n how to order thes e options refer
to Table 28., Ordering Information Scheme. De-
vices are shipped from the factory with Block 0 always valid and the memory content bits, in valid
blocks, erased to ’1’.
See Table 2., Product Description, for all the devices available in the family.
7/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Table 2. Product Description
Bus
Page
Reference Part Number Density
NAND128R3A
NAND128-A
NAND256-A
NAND512-A
NAND512-A
NAND01G-A
NAND128W3A 2.7 to 3.6V 12µs 50ns 200µs
NAND128R4A
NAND128W4A 2.7 to 3.6V 12µs 50ns 200µs
NAND256R3A
NAND256W3A 2.7 to 3.6V 12µs 50ns 200µs
NAND256R4A
NAND256W4A 2.7 to 3.6V 12µs 50ns 200µs
NAND512R3A
NAND512W3A 2.7 to 3.6V 12µs 50ns 200µs
(1)
NAND512R4A
NAND512W4A 2.7 to 3.6V 12µs 50ns 200µs
NAND512R3A
NAND512W3A 2.7 to 3.6V 12µs 50ns 200µs
NAND512R4A
NAND512W4A 2.7 to 3.6V 12µs 50ns 200µs
NAND01GR3A
NAND01GW3A 2.7 to 3.6V 12µs 50ns 200µs
NAND01GR4A
NAND01GW4A 2.7 to 3.6V 12µs 50ns 200µs
Note: 1. Dual Die device.
128Mbit
256Mbit
512Mbit
512Mbit
1Gbit
Width
x8
x16
x8
x16
x8
x16
x8
x16
x8
x16
Size
512+16
Bytes
256+8
Words
512+16
Bytes
256+8
Words
512+16
Bytes
256+8
Words
512+16
Bytes
256+8
Words
512+16
Bytes
256+8
Words
Block
16K+512
Bytes
8K+256
Words
16K+512
Bytes
8K+256
Words
16K+512
Bytes
8K+256
Words
16K+512
Bytes
8K+256
Words
16K+512
Bytes
8K+256
Words
Size
Memory
Array
32 Pages x
1024 Blocks
32 Pages x
2048 Blocks
32 Pages x
4096 Blocks
32 Pages x
4096 Blocks
32 Pages x
8192 Blocks
Operating
Voltage
1.7 to 1.95V 12µs 60ns 200µs
1.7 to 1.95V 12µs 60ns 200µs
1.7 to 1.95V 12µs 60ns 200µs
1.7to 1.95V 12µs 60ns 200µs
1.7to 1.95V 12µs 60ns 200µs
1.7 to 1.95V 12µs 60ns 200µs
1.7to 1.95V 15µs 60ns 200µs
1.7 to 1.95V 15µs 60ns 200µs
1.7 to 1.95V 15µs 60ns 200µs
1.7 to 1.95V 15µs 60ns 200µs
Random
Access
Max
Timings
Sequential
Access
Min
Page
Program
Typical
Block
Package
Erase
Typical
TSOP48
2ms
USOP48
VFBGA55
TSOP48
2ms
USOP48
VFBGA55
2ms TFBGA55
TSOP48
2ms
USOP48
VFBGA63
TSOP48
2ms
TFBGA63
Figure 2. Logic Diagram Table 3. Signal Names
I/O8-15 Data Input/Outputs for x16 devices
Data Input/Outputs, Address Inputs,
or Command Inputs for x8 and x16
devices
Chip Enable
Read Enable
Ready/Busy (open-drain output)
Write Enable
Write Protect
Supply Voltage
Ground
E
W
AL
CL
WP
V
DD
I/O8-I/O15, x16
I/O0-7
AL Address Latch Enable
CL Command Latch Enable
I/O0-I/O7, x8/x16
R
NAND Flash
RB
E
R
RB
W
WP
V
DD
V
SS
NC Not Connected Internally
DU Do Not Use
V
SS
AI07557C
8/57
Figure 3. Logic Block Diagram
Address
Register/Counter
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
AL
CL
W
E
WP
R
Command
Interface
Logic
Command Register
P/E/R Controller,
High V oltage
Generator
RB
NAND Flash
Memory Array
X Decoder
Page Buffer
Y Decoder
I/O Buffers & Latches
I/O0-I/O7, x8/x16
I/O8-I/O15, x16
AI07561c
9/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 4. TSOP48 and USO P 48 Connections, x8 devices
V
V
NC
NC
NC
NC
NC
NC
RB
NC
NC
DD
SS
NC
NC
CL
AL
W
WP
NC
NC
NC
NC
NC
1
R
E
NAND Flash
12
13
24 25
(x8)
48
37
36
NC
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
NC
NC
V
DD
V
SS
NC
NC
NC
I/O3
I/O2
I/O1
I/O0
NC
NC
NC
NC
Figure 5. TSOP48 and USOP4 8 Connections, x16 devices
V
V
NC
NC
NC
NC
NC
NC
RB
NC
NC
DD
SS
NC
NC
CL
AL
WP
NC
NC
NC
NC
NC
1
R
E
NAND Flash
12
13
W
24 25
(x16)
48
37
36
V
SS
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
NC
NC
V
DD
NC
NC
NC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
V
SS
10/57
AI07585B
AI07559B
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 6. FBGA55 Connections, x8 devices (Top view through package)
87654321
A
B
C
D
E
F
G
H
DU
WP
NC
NC NC
NC
AL
NCNC
NC
I/O0
V
SS
R
CL
NC NC
NC
NCNC
NC
E
NC
W
NC
NC
NC
NCNC
NCNC
V
RB
NCNC
NC
NC
NC
DD
DU
DU
V
NC
SS
I/O1
I/O2
NC
DD
I/O4I/O3
I/O5V
I/O6
I/O7
V
SS
DUDU
DU
AI09366b
J
K
L
M
DU
11/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 7. FBGA55 Connections, x16 devices (Top view through package)
87654321
A
B
C
D
E
F
G
H
DU
WP
NC
NC NC
I/O8
I/O1
AL
R
NCNC
NC
V
SS
CL
NC NC
NC
NCNC
I/O10
E
NC
V
RB
NCNC
NC
NC
NC
DD
W
NC
NC
NC
I/O7I/O5
I/O14I/O12
DU
DU
12/57
J
K
L
M
DU
I/O0
V
SS
I/O9
I/O2
I/O3
DD
I/O4I/O11
I/O6V
I/O13
I/O15
V
SS
DUDU
DU
AI09365b
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 8. FBGA63 Connections, x8 devices (Top view through package)
87654321
A
B
C
D
E
F
G
DU DU
DU
WP
NC
NCNC
NC NC
NC
AL
DU
DU
V
SS
R
CL
NC
NC
NCNC
NC
NC
E
W
NC
NC
NC
NCNC
RB
NCNC
NC
NC
NC
109
DU
DU
H
J
K
L
M
DU DU
DU
DU
NC
NC
V
SS
I/O0
I/O1
I/O2
NC
NC
NCNC
DD
I/O4I/O3
I/O5V
I/O6
V
I/O7
V
DD
SS
DU DU
DU
DU
AI07586B
13/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 9. FBGA63 Connections, x16 devices (Top view through package)
87654321
A
B
C
D
E
F
G
DU DU
DU
WP
NC
NC NC
AL
NCNC
NC
DU
DU
V
SS
R
CL
NC
NC
NCNC
E
NC
NC
I/O7I/O5
W
NC
NC
NC
RB
NCNC
NC
NC
NC
109
DU
DU
H
J
K
L
M
DU DU
DU
DU
I/O8
I/O0
V
SS
I/O1
I/O9
I/O2
I/O10
I/O3
I/O14I/O12
V
DD
I/O4I/O11
I/O6
I/O13
V
DD
I/O15
V
SS
DU DU
DU
DU
AI07560B
14/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
MEMORY ARRAY ORGANIZATION
The memory array is m ade up of N AND struc tures
where 16 cells are connected in series.
The memory array is organized in blocks where
each block contains 32 pages. The array is split
into two areas, the main area and the spare area.
The main area of the array is used to store data
whereas the spare area is typically used to store
Error correction Codes, software flags or Bad
Block identification.
In x8 devices the pages are split into a main area
with two half pages o f 256 Bytes each a nd a spare
area of 16 Bytes. In the x16 dev ices the p ages ar e
split into a 256 Word main area and an 8 Word
spare area. Refer t o Figure 10., Memory Arr ay Or-
ganization.
Bad Blocks
The NAND Flash 528 Byte/ 264 Wor d Page dev ices may contain Bad Blocks, that is blocks that contain one or more invalid bits wh ose reli ability i s not
guaranteed. Additional Bad Blocks may develop
during the lifetime of the device.
Figure 10. Memory Array Organization
The Bad Block Information is written prior to shipping (refer to Bad Block Management section for
more details).
Table 4. shows the minimum number of valid
blocks in each device. The values shown include
both the Bad Blocks that are pre sent when the device is shipped and the Bad Blocks that could develop later on.
These blocks need to be managed using Bad
Blocks Management, Block Replacement or Error
Correction Codes (refer to SOFTWARE ALGO-
RITHMS section).
Table 4. Valid Blocks
Density of Device Min Max
1Gbit 8032 8192
512Mbits 4016 4096
256Mbits 2008 2048
128Mbits 1004 1024
Block
Page
1st half Page
(256 bytes)
512 Bytes
Page Buffer, 512 Bytes
x8 DEVICES x16 DEVICES
Block = 32 Pages
Page = 528 Bytes (512+16)
16
Bytes
16
Bytes
Spare Area
2nd half Page
(256 bytes)
512 Bytes
Block
Page
8 bits
8 bits
Block = 32 Pages
Page = 264 Words (256+8)
Main Area
256 Words
Page Buffer, 264 Words
256 Words
8
Words
8
Words
Spare Area
16 bits
16 bits
AI07587
15/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram, and Table
3., Signal Names, for a brief overview of the sig-
nals connected to this device. Inputs/Outputs (I/O0-I/O7). Input/Outputs 0 to 7
are used to input the selected address, output the
data during a Read operation or input a co mma nd
or data during a Write operation. The inputs are
latched on the rising edge of Write Enable. I/O0-I/
O7 are left floating when the device is deselected
or the outputs are disabled.
Inputs/Outputs (I/O8-I/O15). Input/Outputs 8 to 15 are only available in x16 devices. They are used to output the data duri ng a Read oper ation or input data during a Write operation. Comma nd and Address Inputs only require I/O0 to I/O7.
The inputs are latched on the rising edge of Write
Enable. I/O8-I/O15 are left floating when the device is deselected or the outputs are disabled.
Address Latch Enable (AL). The Address Latch
Enable activates the latching o f the Address inputs
in the Command Interface. When AL is high, the
inputs are latched on the rising edge of Write Enable.
Command Latch Enable (CL). The Command
Latch Enable activates the latching of the Command inputs in the Command Interface. When CL
is high, the inpu ts are l atched on the ri sing e dge of
Write Enable.
Chip Enable (E
). The Chip Enable input acti-
vates the memory control logic, input buffers, decoders and sense ampl ifiers. When Chip Enable is
low, V
, the device is selected.
IL
While the device is busy programming or erasing,
Chip Enable transitions to High, V
, are ignored
IH
and the device does not revert to the Standby
mode.
While the device is busy reading:
■ the Chip Enable input should be held Low
during the whole busy time (t
BLBH1
) for
devices that do not present the Chip Enable
Don’t Care option. Otherwise, the read
operation in progress is interrupted and the
device reverts to the Standby mode.
■ for devices that feature the Chip Enab le Don't
Care option, Chip Enable going High during
the busy time (t
) will not interrupt the
BLBH1
read operation and t he device will not revert to
the Standby mode.
Read Enable (R
). T he Read Enable, R, controls
the sequential data output during Read opera-
tions. Data is valid t
The falling edge of R
after the falling edge of R.
RLQV
also increments the internal
column address counter by one.
Write Enable (W
). The Write Enable input, W,
controls writing to the Command Interface, Input
Address and Data latches. Both addresses and
data are latched on the rising edge of Write Enable.
During power-up and power- down a rec overy time
of 1µs (min) is required before th e Command Interface is ready to accept a command. It is recommended to keep Write Enable high during the
recovery time.
Write Protect (WP
). The Write Protect pin is an
input that gives a hardware protection against unwanted program or erase operations. When Write
Protect is Low, V
, the device does not accept any
IL
program or erase operations.
It is recommended to keep the Write Protect pin
Low, V
Ready/Busy (RB
, during power-up and power-down.
IL
). The Ready/Busy output, RB,
is an open-drain output that can be used to identify
if the P/E/R Controller is currently active.
When Ready/Busy is Lo w, V
, a read, progra m or
OL
erase operation i s in progress . When the oper ation
completes Ready/Busy goes High, V
OH
.
The use of an open- drain output allows the Ready/
Busy pins from several mem ories to be c onnected
to a single pull-up resist or. A Low will then indicate
that one, or more, of the memories is busy.
Refer to the Ready/Busy Signal Electrical Charac-
teristics section for details on how to calculate the
value of the pull-up resistor.
V
Supply Voltage. VDD provides the power
DD
supply to the internal core of the memory device.
It is the main power suppl y for all ope rations (read,
program and erase).
An internal voltage detector disables all functions
whenever V
is below 2.5V (for 3V devices) or
DD
1.5V (for 1.8V devices) to protect the device from
any involuntary program/erase during power-transitions.
Each device in a system sh ould have V
DD
decoupled with a 0.1µF capaci tor . T he PCB tr ac k widths
should be sufficient to carry the required program
and erase currents
V
Ground. Ground, V
SS
is the reference for
SS,
the power supply. It must be connected to the system ground.
16/57
BUS OPERATIONS
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
There are six standard bus oper ati ons that contr ol
the memory. Each of these is described in this
section, see Table 5., Bus Operations, for a sum-
mary.
Command Input
Command Input bus operations are used to give
commands to the memory. Command are accepted when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable is Low and
Read Enable is High. They are latched on the rising edge of the Write Enable signal.
Only I/O0 to I/O7 are used to input commands.
See Fi gure 23. an d Table 20. for d etails of the tim-
ings requirements.
Address Input
Address Input bus operations are used to input the
memory address. T hree bus cycles are r equired to
input the addresses for the 128Mb and 25 6Mb devices and four bus cycles are requi red to input t he
addresses for the 512Mb and 1Gb devices (refer
to Tables 6 and 7, Address Insertion).
The addresses are accepted when Chi p Enab le is
Low, Address Latch Enable is High, Command
Latch Enable is Low and Read Enable is High.
They are latched on the rising edge of the Write
Enable signal. Only I/O0 to I/O7 are used to input
addresses.
See Fi gure 24. an d Table 20. for d etails of the timings requirements.
Data Input
Data Input bus operations are used to input the
data to be programmed.
Data is accepted only when Chip Enable is Low,
Address Latch Enable is Low, Command Latch
Enable is Low and Read Enable is High. The data
is latched on the rising edge of the Write Enable
signal. The data is input sequentially using the
Write Enable signal.
See Fi gure 25. and Table 20. an d Tabl e 21. for details of the timings requirements.
Data Output
Data Output bus operations are used to read: the
data in the memory ar ra y, the Status Register, the
Electronic Signature and the Serial Number.
Data is output when Chip Enabl e is Low, Write Enable is High, Address Latch Enable is Low, and
Command Latch Enable is Low.
The data is output sequentially using the Read Enable signal.
See Fi gure 26. a nd Table 21. for detail s of the tim-
ings requirements.
Write Protect
Write Protect bus operations are used to protect
the memory against program or erase operations.
When the Write Protect signal is Low the device
will not accept program or erase operations and so
the contents of the memory array cannot be altered. The Write Protect signal is not latched by
Write Enable to ensure protection even during
power-up.
Standby
When Chip Enable is High the memory enters
Standby mode, the device is deselected, outputs
are disabled and power consumption is reduced.
Table 5. Bus Operations
Bus Operation E AL CL R W WP I/O0 - I/O7
Command Input
Address Input
Data Input
Data Ou tput
Write Protect X X X X X
Standby
Note: 1. Only for x16 devices.
WP must be VIH when issuing a program or erase command.
2.
V
IL
V
IL
V
IL
V
IL
V
IH
V
V
IH
V
V
XXXXX X X
V
IL
IL
IL
IH
V
IL
V
IL
V
Falling
IL
V
Rising
IH
V
Rising X Address X
IH
V
Rising X Data Input Data Input
IH
V
IH
(2)
X
X Data Output Data Output
V
IL
Command X
I/O8 - I/O15
XX
(1)
17/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Table 6. Address Insertion, x8 Devices
Bus Cycle I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
st
1
nd
2
rd
3
th(4)
4
Note: 1. A8 is set Low or High by the 00h or 01h Command, see Pointer Operations section.
2. Any additional address input cycles will be ignored.
3. The 4th cycle is only required for 512Mb and 1Gb devices.
Table 7. Address Insertion, x16 Devices
Bus
Cycle
st
1
nd
2
rd
3
th(4)
4
Note: 1. A8 is Don’t Care in x16 devices.
2. Any additional address input cycles will be ignored.
3. The 01h Command is not used in x16 devices.
4. The 4th cycle is only required for 512Mb and 1Gb devices.
A7 A6 A5 A4 A3 A2 A1 A0
A16 A15 A14 A13 A12 A11 A10 A9
A24 A23 A22 A21 A20 A19 A18 A17
V
I/O8-
I/O15
IL
V
IL
V
IL
V
IL
V
IL
V
IL
A26 A25
I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
X A7 A6 A5 A4 A3 A2 A1 A0
X A16 A15 A14 A13 A12 A11 A10 A9
X A24 A23 A22 A21 A20 A19 A18 A17
X
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
A26 A25
Table 8. Address Definitions
Address Definition
A0 - A7 Column Address
A9 - A26 Page Address
A9 - A13 Address in Block
A14 - A26 Block Ad dr ess
A8
A8 is set Low or High by the 00h or 01h Command, and is
Don’t Care in x16 devices
18/57
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