ST NAND04GW3B2B, NAND08GW3B2A User Manual

查询NAND08GW3B2A供应商

Feature summary

■ High density NAND Flash Memory

– up to 8 Gbit memory array – Up to 256 Mbit spare area – Cost effective solution for mass storage

applications

■ NAND Interface

– x8 bus width – Multiplexed Address/ Data

■ Supply voltage

– 3.0 V device : V

■ Page size

– (2048 + 64 spare) Bytes

■ Block size

– (128K + 4K spare) Bytes

■ Page Read/Program

– Random access: 25µs (max) – Sequential access: 30ns (min) – Page program time: 200µs (typ)

■ Copy Back Program mode

– Fast page copy without external buffering

■ Cache Program and Cache Read modes

– Internal Cache Register to improve the

program and read throughputs

■ Fast Block Erase

– Block erase time: 2ms (typ)

■ Status Register

■ Electronic Signature

■ Chip Enable ‘don’t care’

– for simple interface with microcontroller

■ Serial Number option

= 2.7 to 3.6V

NAND04GW3B2B NAND08GW3B2A

4 Gbit, 8 Gbit, 2112 Byte/1056 Word Page

3V, NAND Flash Memories

PRELIMINARY DATA

TSOP48 12 x 20mm

■ Data protection

– Hardware and Software Block Locking – Hardware Program/Erase locked during

Power transitions

■ Data integrity

– 100,000 Program/Erase cycles – 10 years Data Retention

■ ECOPACK

■ Development tools

– Error Correction Code software and

hardware models

– Bad Blocks Management and Wear

Leveling algorithms – File System OS Native reference software – Hardware simulation models

package

May 2006 Rev 2 1/58

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

www.st.com

Contents NAND04GW3B2B, NAND08GW3B2A

Contents

1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1 Bad Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.1 Inputs/Outputs (I/O0-I/O7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2 Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.3 Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.4 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.5 Read Enable (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.6 Power-Up Read Enable, Loc k/Unlock Enab le (PRL) . . . . . . . . . . . . . . . . 13

3.7 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.8 Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.9 Ready/Busy (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.10 V

3.11 V

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.1 Command Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.2 Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.3 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.4 Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.5 Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.6 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5 Command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6 Device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.1 Read Memory Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.1.1 Random Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.1.2 Page Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

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NAND04GW3B2B, NAND08GW3B2A Contents

6.2 Cache Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.3 Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.3.1 Sequential Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.3.2 Random Data Input in page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.4 Copy Back Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.5 Cache Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.6 Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.7 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.8 Read Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.8.1 Write Protection Bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.8.2 P/E/R Controller and Cache Ready/Busy Bit (SR6) . . . . . . . . . . . . . . . 28

6.8.3 P/E/R Controller Bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.8.4 Cache Program Error Bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.8.5 Error Bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.8.6 SR4, SR3 and SR2 are Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.9 Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7 Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.1 Blocks Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.2 Blocks Unlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.3 Blocks Lock-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.4 Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8 Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8.1 Bad Block Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8.2 Block Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8.3 Garbage Collect ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.4 Wear-leveling Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.5 Error Correction Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.6 Hardware simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.6.1 Behavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.6.2 IBIS simulations models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

9 Program and Erase times and endurance cycles . . . . . . . . . . . . . . . . . 40

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Contents NAND04GW3B2B, NAND08GW3B2A

10 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

11 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

11.1 Ready/Busy Signal Electrical Charact e risti cs . . . . . . . . . . . . . . . . . . . . . 53

11.2 Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

12 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

13 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

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NAND04GW3B2B, NAND08GW3B2A List of tables

List of tables

Table 1. Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 3. Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 4. Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 5. Address Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 6. Address Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 7. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 8. Copy Back Program addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 9. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 10. Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 11. Electronic Signature Byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 12. Electronic Signature Byte 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 13. Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 14. Block Failure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 15. Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . . 40

Table 16. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 17. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 18. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 19. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 20. AC Characteristics for Command, Address, Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 21. AC Characteristics for Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 22. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Mechanical Data. . . 55

Table 23. Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 24. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

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List of figures NAND04GW3B2B, NAND08GW3B2A

List of figures

Figure 1. Logic Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 2. Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 3. TSOP48 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 4. Memory Array Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 5. Read Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 6. Random Data Output During Sequential Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 7. Cache Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 8. Page Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 9. Random Data Input During Sequential Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 10. Copy Back Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 11. Page Copy Back Program with Random Data Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 12. Cache Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 13. Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 14. Blocks Unlock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 15. Read Block Lock Status Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 16. Block Protection State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 17. Bad Block Management Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 18. Garbage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 19. Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 20. Equivalent Testing Circuit for AC Characteristics Measurement . . . . . . . . . . . . . . . . . . . . 43

Figure 21. Command Latch AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 22. Address Latch AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 23. Data Input Latch AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 24. Sequential Data Output after Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 25. Read Status Register AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 26. Read Electronic Signature AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 27. Page Read Operation AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 28. Page Program AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 29. Block Erase AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 30. Reset AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 31. Program/Erase Enable Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 32. Program/Erase Disable Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 33. Ready/Busy AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 34. Ready/Busy Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 35. Resistor Value Versus Waveform Timings For Ready/Busy Signal . . . . . . . . . . . . . . . . . . 54

Figure 36. Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 37. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline . . . . . . . . . . 55

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NAND04GW3B2B, NAND08GW3B2A Summary description

1 Summary description

The NAND Flash 2112 Byte/ 1056 Word Page is a family of non-volatile Flash memories that uses NAND cell technology. The NAND04GW3B2B and NAND08GW3B2A have a density of 4 Gbits and 8 Gbits, respectively . The y operate from a 3V voltage supply. The size of a Page is 2112 Bytes (2048 + 64 spare).

The address lines are multiplexed with the Data Input/Output signals on a multiplexed x8 Input/Output bus. This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint.

Each block can be programmed and erased over 100,000 cycles. To extend the lifetime of NAND Flash devices it is strongly recommended to implement an Error Correction Code (ECC).

The device has hardware and software security features:

● A Write Protect pin is available to give a hardware protection against program and

erase operations.

● A Block Locking scheme is available to provide user code and/or data protection.

The device features an open-drain Ready/Busy output that can be used to identify if the Program/Erase/Read (P/E/R) Controller is currently active. The use of an open-drain output allows the Ready/Busy pins from several memories to be connected to a single pull-up resistor.

A Copy Back Program command is available to optimize the management of defective blocks. When a Page Program operation fails, the data can be programmed in another page without having to resend the data to be programmed.

The NAND04GW3B2B and NAND08GW3B2A have Cache Program and Cache Read features which improve the program and read throughputs for large files. During Cache Programming, the device loads the data in a Cache Register while the previous data is transferred to the Page Buffer and programmed into the memory array. During Cache Reading, the device loads the data in a Cache Register while the previous data is transferred to the I/O Buffers to be read.

The device has the Chip Enable Don’t Care feature, which allows code to be directly downloaded by a microcontroller, as Chip Enable transitions during the latency time do not stop the read operation.

The devices have the option of a Unique Identifier (serial number), which allows each device to be uniquely identified.

The Unique Identifier options is subject to an NDA (Non Disclosure Agreement) and so not described in the datasheet. For more details of this option contact your nearest ST Sales office.

The device is available in a TSOP48 (12 x 20mm) package. In order to meet environmental requirements, ST offers the NAND04GW3B2B and NAND08GW3B2A in ECOPACK

package. ECOPACK packages are Lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark.

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Summary description NAND04GW3B2B, NAND08GW3B2A

For information on how to order these options refer to Table 23: Ordering Information

Scheme. Devices are shipped from the factory with Block 0 always valid and the memory

content bits, in valid blocks, erased to ’1’. See Table 1: P ro duct Desc r ip tio n, for all the devices available in the family.

Table 1. Product Description

Part Number Density

NAND04GW3B2B 4 Gb x8

NAND08GW3B2A 8 Gb x8

1. The NAND08GW3B2A is composed of two 4 Gbit dice.

Timings

Bus

Page

Block

Width

Size

2048+

Bytes

Size

128K

+4K

Bytes

Memor y Array

Pages x

Blocks

Pages x

Blocks

4096

8192

Operating

Voltage

2.7 to

3.6V

Random

access

time

(max)

25µs 30ns 200µs 2ms TSOP48

25µs 30ns 200µs 2ms

Sequential

access

time (min)

Page

Program

(typ)

Block Erase

(typ)

Package

TSOP48

(1)

Figure 1. Logic Block Diagram

Address

PRL

Command

Interface

Logic

Command Register

P/E/R Controller,

High V oltage

Generator

NAND Flash

Memory Array

X Decoder

Page Buffer

Cache Register

Y Decoder

I/O Buffers & Latches

I/O0-I/O7

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AI12465

NAND04GW3B2B, NAND08GW3B2A Summary description

Figure 2. Logic Diagram

PRL

Table 2. Signal Names

I/O0-7 Data Input/Outputs, Address Inputs, or Command Inputs

AL Address Latch Enable CL Command Latch Enable

Chip Enable

NAND FLASH

I/O0-I/O7

AI12466b

Read Enable

RB Ready/Busy (open-drain output)

Write Enable

Write Protect PRL Power-Up Read Enable, Loc k /U nlock Enable V

Supply Voltage

Ground

NC Not Connected Internally DU Do Not Use

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Summary description NAND04GW3B2B, NAND08GW3B2A

Figure 3. TSOP48 Connections

NC NC NC NC NC NC RB

NC NC

DD SS

NC NC

CL AL

NC NC NC NC NC

R E

NAND FLASH

24 25

37 36

NC NC NC NC I/O7 I/O6 I/O5 I/O4 NC NC PRL V

NC NC NC I/O3 I/O2

I/O1 I/O0

NC NC NC NC

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AI12467b

NAND04GW3B2B, NAND08GW3B2A Memory array organization

2 Memory array organization

The memory array is made up of NAND structures where 32 cells are connected in series. The memory array is organized in blocks where each block contains 64 pages. The array is

split into two areas, the main area and the spare area. The main area of the array is used to store data whereas the spare area is typically used to store Error correction Codes, software flags or Bad Block identification.

The pages are split into a 2048 Byte main area and a spare area of 64 Bytes. Refer to

Figure 4: Memory Array Organization.

2.1 Bad Blocks

The NAND Flash 2112 Byte/ 1056 Word Page devices may contain Bad Blocks, that is blocks that contain one or more invalid bits whose reliability is not guaranteed. Additional Bad Blocks may develop during the lifetime of the device.

The Bad Block Information is written prior to shipping (refer to Section 8.1: Bad Block

Management for more details). Table 3 shows the minimum number of valid blocks. The values shown include both the Bad

Blocks that are present when the device is shipped and the Bad Blocks that could develop later on.

These blocks need to be managed using Bad Blocks Management, Block Replacement or Error Correction Codes (refer to Section 8: Software algorithms).

Table 3. Valid Blocks

Density of Device Min Max

4 Gbits 4016 4096

(1)

8 Gbits

1. The NAND08GW3B2A is composed of two 4 Gbit dice.

8032 8192

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Memory array organization NAND04GW3B2B, NAND08GW3B2A

Figure 4. Memory Array Organization

x8 bus width Block = 64 Pages Page = 2112 Bytes (2,048 + 64)

Block

Page

Main Area

2048 Bytes

Page Buffer, 2112 Bytes

2,048 Bytes

Bytes

Spare Area

8 bits

AI12468

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NAND04GW3B2B, NAND08GW3B2A Signal descriptions

3 Signal descriptions

See Figure 2: Logic Diagram, and Table 2: Signal Names, for a brief overview of the signals connected to this device.

3.1 Inputs/Outputs (I/O0-I/O7)

Input/Outputs 0 to 7 are used to input the selected address, output the data during a Read operation or input a command or data during a Write operation. The inputs are latched on the rising edge of Write Enable. I/O0-I/O7 are left floating when the device is deselected or the outputs are disabled.

3.2 Address Latch Enable (AL)

The Address Latch Enable activates the latching of the Address inputs in the Command Interface. When AL is high, the inputs are latched on the rising edge of Write Enable.

3.3 Command Latch Enable (CL)

The Command Latch Enable activates the latching of the Command inputs in the Command Interface. When CL is high, the inputs are latched on the rising edge of Write Enable.

3.4 Chip Enable (E)

The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is low, V high, v mode.

, while the device is busy, the device remains selected and does not go into standby

, the device is selected. If Chip Enable goes

3.5 Read Enable (R)

The Read Enable pin, R, controls the sequential data output during Read operations. Data is valid t column address counter by one.

after the falling edge of R. The falling edge of R also increments the internal

RLQV

3.6 Power-Up Read Enable, Lock/Unlock Enable (PRL)

The Power-Up Read Enable, Lock/Unlock Enable input, PRL, is used to enable and disable the lock mechanism. When PRL is High, V

If the Power-Up Read Enable, Lock/Unlock Enable input is not required, the PRL pin should be left unconnected (Not Connected) or connected to V

, the device is in Block Lock mode.

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Signal descriptions NAND04GW3B2B, NAND08GW3B2A

3.7 Write Enable (W)

The Write Enable input, W, controls writing to the Command Interface, Input Address and Data latches. Both addresses and data are latched on the rising edge of Write Enable.

During power-up and power-down a recovery time of 10µs (min) is required before the Command Interface is ready to accept a command. It is recommended to keep Write Enable high during the recovery time.

3.8 Write Protect (WP)

The Write Protect pin is an input that gives a hardware protection against unwanted program or erase operations. When Write Protect is Low, V program or erase operations.

, the device does not accept any

It is recommended to keep the Write Protect pin Low, V

3.9 Ready/Busy (RB)

The Ready/Busy output, RB, is an open-drain output that can be used to identify if the P/E/R Controller is currently active.

When Ready/Busy is Low, V operation completes Ready/Busy goes High, V

The use of an open-drain output allows the Ready/Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy.

Refer to the Section 11.1: Ready/Busy Signal Electrical Characteristics for details on how to calculate the value of the pull-up resistor.

3.10 V

Supply Voltage

VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (read, program and erase).

An internal voltage detector disables all functions whenever V

Table 19) to protect the device from any involuntary program/erase during power-transitions.

, during po we r-u p an d po w er- do wn .

, a read, program or erase operation is in progress. When the

is below V

LKO

(see

Each devi ce in a sys tem sh oul d h a ve V widths should be sufficient to carry the required program and erase currents

3.11 VSS Ground

Ground, V ground.

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is the reference for the power supply. It must be connected to the system

SS,

decoupled with a 0.1µF capacitor. The PCB track

NAND04GW3B2B, NAND08GW3B2A Bus operations

4 Bus operations

There are six standard bus operations that control the memory. Each of these is described in this section, see Table 4: Bus Op eratio n s, for a summary.

Typically, glitches of less than 5 ns on Chip Enable, Write Enable and Read Enable are ignored by the memory and do not affect bus operations.

4.1 Command Input

Command Input bus operations are used to give commands to the memory. The Commands are input on I/O0-I/O7. Commands are accepted when Chip Enable is Low,

Command Latch Enable is High, Address Latch Enable is Low and Read Enable is High. They are latched on the rising edge of the Write Enable signal.

See Figure 21 and Table 20 for details of the timings requirements.

4.2 Address Input

Address Input bus operations are used to input the memory addresses. Addresses are input on I/O0-I/O7. Five bus cycles are required to input the addresses (refer

to Table 5: Address Insertion). The addresses are accepted when Chip Enable is Low, Address Latch Enable is High,

Command Latch Enable is Low and Read Enable is High. They are latched on the rising edge of the Write Enable signal.

See Figure 22 and Table 20 for details of the timings requirements.

4.3 Data Input

Data Input bus operations are used to input the data to be programmed. Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command

Latch Enable is Low and Read Enable is High. The data is latched on the rising edge of the Write Enable signal. The data is input sequentially using the Write Enable signal.

See Figure 23 and Table 20 and Table 21 for details of the timings requirements.

4.4 Data Output

Data Output bus operations are used to read: the data in the memory array, the Status Register, the lock status, the Electronic Signature and the Unique Identifier.

Data is output when Chip Enable is Low , Write Enable is High, Address Latch Enable is Low, and Command Latch Enable is Low.

The data is output sequentially using the Read Enable signal. See Figure 24 and Table 21 for details of the timings requirements.

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Bus operations NAND04GW3B2B, NAND08GW3B2A

4.5 Write Protect

Write Protect bus operations are used to protect the memory against program or erase operations. When the Write Protect signal is Low the device will not accept program or erase operations and so the contents of the memory array cannot be altered. The Write Protect signal is not latched by Write Enable to ensure protection even during power-up.

4.6 Standby

When Chip Enable is High the memory enters Standby mode, the device is deselected, outputs are disabled and power consumption is reduced.

Table 4. Bus Operations

Bus Operation E AL CL R W WP I/O0 - I/O7

Command Input V

Address Input V

Data Input V

Data Output V

IL IL IL IL

V V

IL IH IL IL

V V V

Rising X

Rising X Address

Rising V

Falling V

Write Protect X X X X X V

Standby V

1. WP must be VIH when issuing a program or erase command.

Command set

Table 5. Address Insertion

XXXXV

(1)

Command

Data Input

X Data Output

IL/VDD

X X

Bus

Cycle

1. Any additional address input cycles will be ignored.

2. A30 is only valid for the NAND08GW3B2A.

I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0

(1)

A7 A6 A5 A4 A3 A2 A1 A0

A19 A18 A17 A16 A15 A14 A13 A12 A27 A26 A25 A24 A23 A22 A21 A20

Table 6. Address Definition

Address Definition

A0 - A11 Column Address A12 - A17 Page Address A18 - A29 Block Address (NAND04GW3B2B) A18 - A30 Block Address (NAND08GW3B2A)

A11 A10 A9 A8

A30

(2)

A29 A28

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NAND04GW3B2B, NAND08GW3B2A Command set

5 Command set

All bus write operations to the device are interpreted by the Command Interface. The Commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when the Command Latch Enable signal is high. Device operations are selected by writing specific commands to the Command Register. The two-step command sequences for program and erase operations are imposed to maximize data security.

The Commands are summarized in Table 7.

Table 7. Commands

Read 00h Random Data Output 05h E0h – – Cache Read 00h 31h – – Exit Cache Read 34h – – – Yes Page Program

(Sequential Input def a ult ) Random Data Input 85h – – –

Command

Bus Write Operations

(1)

1st cycle 2nd cycle 3rd cycle 4th cycle

(2)

30h – –

80h 10h – –

Commands

accepted

during busy

(3)

Copy Back Program 00h 35h 85h 10h Cache Program 80h 15h – – Block Erase 60h D0h – – Reset FFh – – – Yes Read Electronic Signature 90h – – – Read Status Register 70h – – – Yes Read Block Lock Status 7Ah – – – Blocks Unlock 23h 24h – – Blocks Lock 2Ah – – – Blocks Lock-Down 2Ch – – –

1. The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or input/output data are not shown.

2. For consecutive Read operations the 00h command does not need to be repeated.

3. Only during Cache Read busy.

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Device operations NAND04GW3B2B, NAND08GW3B2A

6 Device operations

The following section gives the details of the device operations.

6.1 Read Memory Array

At Power-Up the device defaults to Read mode. T o enter Read mode from another mode the Read command must be issued, see Table 7: Commands. Once a Read command is issued, subsequent consecutive Read commands only require the confirm command code (30h).

Once a Read command is issued two types of operations are available: Random Read and Page Read.

6.1.1 Random Read

Each time the Read command is issued the first read is Random Read.

6.1.2 Page Read

After the first Random Read access, the page data (2112 Bytes) are transferred to the Page Buffer in a time of t Ready/Busy signal goes High. The data can then be read out sequentially (from selected column address to last column address) by pulsing the Read Enable signal.

The device can output random data in a page, instead of the consecutive sequential data, by issuing a Random Data Output command.

The Random Data Output command can be used to skip some data during a sequential data output.

The sequential operation can be resumed by changing the column address of the next data to be output, to the address which follows the Random Data Output command.

The Random Data Output command can be issued as many times as required within a page.

The Random Data Output command is not accepted during Cache Read operations.

(refer to Table 21 for value). Once the transfer is complete the

WHBH

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