ST MTC50150 User Manual
MTC50150
Fi
ADSL GATEWAY PROCESSOR
DATA BRIEF
1 GENERAL FEATURES
1.1 WAN modem feature set
■ Embedded transceiver ANSI T1.413, ITU G.dmt
Annex A/B incl. Deutsche Telecom UR-2
compliant, splitterless ITU G.Lite
■ ADSL analog front end compatibility:
– MTC20174, ADSL front end, 7
integrated line driver, DCXO
1.2 WAN connectivity
■ Point to point protocol over Ethernet
■ Point to point protocol over ATM
■ Relay via PPP session control on terminal
■ CIP classical IP over Ethernet
■ Full ICSA firewall
1.3 Session Control
■ PPPoE point to point protocol over Ethernet
■ PPPoA point to point protocol over ATM
■ PPPoA relay via PPP session control on
terminal.
1.4 ATM features
■ Adaptation Layers: AAL5 (data), supported in
hardware
■ Encapsulation: RFC1483 and RFC2684, multi
protocol encapsulation over ATM (MPOA) over
AAL5 bridged and routed modes
■ ATM circuit: 8 PVC
■ Available services (Qos): UBR
th
generation,
gure 1. Package
PBGA208 (17x17x1.97mm)
Table 1. Order Codes
Part Number Package
MTC50150-TB-C2 PBGA208
■ Support up to 128 MAC stations.
■ Embedded http server for configuration
1.6 Configuration and Provisioning
■ Configuration: remote configuration via Java™
enabled browser
■ Firmware update: remote upload via network.
■ Management: SNMP, UNI3.1, ILMI 4.0
(management and auto configuration)
1.7 Customization
■ Customization with comprehensive API set
■ Development tool based on Windows
environment on PC
■ Exposed BSP layer
■ Flexible development licenses based on kernel
software in object or source format.
1.5 LAN feature set
■ 1 Ethernet 10/100 MII (HPNA compa tibl e)
■ 2 UARTs, Bluetooth compatible
■ Bridging: Transparent bridge: IEEE 801.1d,
spanning tree, learning/filter bridge in hardware
■ Embedded router: RIP1, RIP2, static routing
■ NAT/PAT with extended ALG support
■ DHCP server/client
■ IP protocol: TCP/IP, ARP sharing access,
ICMP, IGMP
September 2004
2 APPLICATION
■ Low cost ADSL residential gateway
■ Residential gateway with broadband ADSL
WAN transceiver
■ Wan to LAN bridge and router with ADSL WAN
transceiver and Ethernet MAC
■ Wireless LAN access point with ADSL WAN
transceiver and Ethernet MAC
Rev. 1
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MTC50150
Figure 2. Block diagram
PLL
APB BRIDGE
COMMUNICATION
CONTROLLER
ARM946ES
ADSL
DMT-U
SDRAM INTERFACE
ROM
AAL5
SAR
JTAG
DMA
UART
ISA
(FLASH)
GPIO
10/100
BRIDGE &
MAC
D02TL543
3 DESCRIPTION
The MTC50150 is a low cost ADSL bridge and LAN router. One 10/100Mbits Ethernet port allows the connection of a LAN to the WAN in brid ged or routed mode. Th e data traffic can be route d through a local
terminal by using the LAN port. The presenc e of NAT and DHCP and the A PI slots for firewall fun ctions
allow for a high-speed connection of LAN connected devices, like PC, to the public Internet in an isolated
and secure environment.
The chip is built around an ARM946ES RISC processor. It embeds a complete ADSL transceiver and LAN
interfaces with an MII allowing multiple medium utilization. A comprehensive software package is available
with the SOC soluti on, which has been dev eloped with customizat ion in mind. Several software licens e
plans are available as well as a user friendly development environment.
4 HARDWARE DESCRIPTION
The MTC50150 processor combines a DynaMiTe™ ADSL transceiver with a dedicated ARM946ES RISC
processor. To maintain high data throughput, the RISC proces sor includes 16Kbyte cache mem ory for
programming and 16Kbyte memory for data. Processing of most of the layer 2 protocols on the ATM (SAR
and AAL) and IP (Mac filter and bridge) sides are performed by specific hardware blocks, relieving the processors from these tasks. The chip provides minimal external components and maximum flexibility. In addition, it contains one Ethernet 10/100 Base-T MAC and the exposed MII interface allows the connection
to alternate LAN mediums like HPN A, WLAN, and HPLUG. The MT C-50150 device is targeted for lowcost residential gateways. Its primary design goal is to minimize cost. Secondary design goals are:
– Low system cost using a reduced BOM and optimized SOC technology
– Low power to facilitate primary service capabilities and thermal system issues
– Low EMI to simplify packaging and qualification of systems
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MTC50150
5 HARDWARE FEATURES
– ARM946ES RISC processor dedicated to network processing, API and DSL modem control
– Hardware ATM processor: SAR function with AAL5 processing
– Hardware packet processor: Ethernet MAC, learning and filter bridge
– One 10/100 Base-T Ethernet MACs with MII interface for external PHY or multi-port switch
– One 8 or 16-bit wide Flash port, ISA compatible for up to 16Mbyte addressable memory
– One 32-bit wide SDRAM interface with 32Mbyte addressable memory
– Interface to MTC20174 DynaMiTe™ ADSL analog front end (AFE) chip
– Multi-channel DMA engine integrated with peripherals
– Low power: 1.8V +/-10% core voltage, 3.3V +/- 10% I/O voltage
– 128 instructions (32 bits) of boot ROM
– GPIO with support LED
– Cc-based Multi ICE/compiler support with assembler and debugger
– Software chip and system simulators for software development and debug
– JTAG board-level test interface
– 140MHz system clock (processor cycle clock)
– Sleep mode with wake on LAN wake on WAN feature
– Programmable system frequency clock: 140, 105, 70, 35 and 129MHz (fall back mode).
6 SOFTWARE ARCHITECTURE
The software is organized in 5 clusters:
– User interface API
– System services
– Network services
– TCP/IP socket
– ATM encapsulation
A description of the cluster contents is given in the software features section.
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MTC50150
Figure 3. Embedded software block diagram
USER INTERFACE
SYSTEM
SERVICES
RTOS
MIB
CTRL-E
DOWNLOAD
FLASH MGR
ILMI
UNI3.1
DIAGNOSTIC
D02TL535
NETWORK
SERVICES
HTTP SRV
SNMP
TFTP
DNS
IP SOCKET
ATM ENCAPSULATION
AAL5/SAR
UTOPIA MASTER DRIVER
BRIDGE FIRMWARE
TCP UDP UDP
PPPoE PPPoA PPTPRAS
BRIDGING, SPANNING
ROUTER
RIP1.2
FIREWALL
NAT
DHCP
LEARNING TREE
MAC
MII DRIVER
ROUTER ADD-ON
7 SOFTWARE FEATURES
7.1 User Interface API
A development kit dedicated to the p latform allows acc ess through the API to specific code sections to
allow software customiz atio n. The dev el opm ent ki t prov ide s sou rce c od e for a p ac ket pho ne ap pli c ati on,
drivers and diagnostic software. Other stacks are delivered in the object code. A specific development environment is provided . It includes projec t profiling, managi ng, C compiler/ass embler and tools as well a
source level debugger.
7.2 System Services
MAPI offers an easy interface to control the operations necessary to setup the ADSL link and monitor the
operation conditions . The so ftware provides an o ptimiz ed con trol sequ ence to insure op timum op erati on
of the DynaMiTe™ chip set.
MIB2: RFC 1213: Management Information Bases (MIB2) is implemented in the device.
RTOS: Implemented RTOS is Posix compliant. The user can access various parts of the software blocks
through specific APIs. Alternate RTOS are planned.
Flash Initialization. Software is stored on an external Flash. At boot-up, the stored software is downloaded
to the device. By using co mpilation opti ons, software c an be executed fr om the internal RA M (intensive
operations) or executed from the flash. Execution is optimized by the use of an intermediate cache memory.
Startup initialization: Optional software images can be selected at startup of the device.
Broad Support Program: A BSP layer is provided to allow easy porting of proprietary software on the SOC
architecture. The BSP provides a unique hardware abstraction layer model valid for the entire product line.
This approach allows reuse of the custom solfware through the entire MTC-50xxx product line(*).
(*) starting with MTC-50150
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MTC50150
7.3 Network Services
7.3.1 ILMI
Embedded software provides an I LMI 4.0 im plementatio n which han dles address registration (switch to
end device) and noti fication (end device to swi tch) as well as auto-confi guration. IL MI uses SNMP o ver
AAL-5 for transport.
7.3.2 UNI Signaling
Stackware includes support for standard ATM UNI signaling standards, including UNI 3.1.
7.3.3 RIP1/RIP2 IP Router
IP router software pr ovides implementations o f RIP 1 a nd RIP 2. The IP router is an I Pv4 r ou ter. Su ppor t
for new station discovery is provided.
7.4 TCP/IP Socket
7.4.1 TCP
Transport Control Protocol (TCP) is accessed using a standard socket interface to allow easy integration
of existing Layer 3 and higher software into the basic protocol stack.
7.4.2 IP
Internal protocol: IP a nd IP r outin g are both p art of the net work la ye r (layer 3). I P is ac tually r esp onsible
for delivering packets for which the router defines the direction.
7.4.3 DHCP RFC 2131, 2132
Dynamic Host Control Protocol (DHCP) provides both client & server functions. The client is typically used
to obtain an IP address from an ISP. The DHCP server is used to assign local IP client devices with designated IP addresse s. T he serv er lends addres ses for a li mited time. NAT reg isters loc al termi nal IP addresses and maintai ns a translation table to allow se nding and receiv ing data on the pu blic network b y
sharing only the residential gateway assigned public IP address.
7.4.4 NAT: RFC1631, 2663
The Network Address Tran slator (NAT) impleme nts Network and Port Ad dress Translation (NAT /PAT).
NAT allows a single public IP address on the WAN side to be sha red among m any dev ices on th e LAN
side. Combined with a DHCP serv er local devices are ass igned a private addre ss, hidden to the public
internet and changed frequently. The combination of DHCP and NAT provides a powerful isolation barrier
to external assault. NAT PAT features a number of AGL.
7.5 ATM Encapsulation and spanning-tree
RFC 1483/2684 provides a simple robust method of connecting end stations over an ATM network. User
data in the form of Ethernet packets are enca psulated into AAL-5 PDUs for transport over ATM. RF C
1483/2684 provides no AAA function (authentication, authorization & accounting).
7.5.1 Spanning-tree bridge (802.1d)
Bridge module provides a transparent bridge between two physically disjoint networks with spanning-tree
option. The spanning-tree algorithm handles redundancy and also increases robustness. It provides high
performance as well as flexibility to group interfaces for example to bridge the WAN only to LAN interfaces
but not to other WAN interfaces.
The ATM driver passes data between applicat ion software task s on the processor and a physical AAL5
hardware block.
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MTC50150
7.6 Session Control
7.6.1 PPPoA (RFC 2364)
PPP over ATM provides on the CPE side a termination agent for the transportation for IP packets over an
ATM segment. A PPP session is established between the CPE and the central office (DSLAM). PPP provides AAA function (a uthentication, authorizatio n and accounting). The PPP packets enc apsulated according to RFC 2364 for transmission over an ATM segment. On the CPE side, the IP data can be
delivered to the end user over such technologies as Ethernet.
7.6.2 PPPoE (RFC 2516)
The PPP over Ethernet encap sulation is used to tr ansport Ether net PPP traffi c. The traffic is the n transported over the ATM link by encapsulating traffic using RFC1483/2683. There may be multiple PPP sessions, each termin ated i n th e IA D c lien t de vi ce . P PPoE r el ay agent works as a enhan ce d l ay er 2 brid ge.
It determines that wh ich locally origina ted PPPoE traffic be longs. The relay agent fo rwards that traffic,
without any unnecess ary processin g, only to the correct desti nation. Simi larly, rece ived data is i mmediately relayed only to the appropriate LAN client.
8 DEVELOPMENT ENVIRONMENT
The MTC5015 0 presents a comp rehensive set of software featu res. To allow ma nufacturer s to further customize the system, a s et of A PI func tions ar e mad e avail able. Th is us e of th e API fun ction s re quires the
acquisition of a deve lopment envir onment. T he develop ment environ ment is based on the following elements:
■ -ARM Developer Suite (ADS) v1.1
■ -ATI Development license
■ -ATI EDE (Embedded Development Environment)
■ -MS Developer Studio (VC++) v6.0 or higher
Along with the deve lop ment e nvironm ent a numbe r of tools a re prov ided to allo w th e dia gnostic and the
downloading operation of the executable on the nonvolatile memory of the MTC50150.
9 NOMINAL CHARACTERISTICS
The MTC50150 processor is available in a 208-pin PBGA ( plastic ball grid arra y) package. All I/Os are
3.3V CMOS levels, with all inputs and 3-states having 5V tolerance. Supply voltages are 1.8 and 3.3V. No
pins have internal pull-ups and pull-downs.
Supply – Typical power supply voltage 1.8V
– Typical pad power supp ly vo ltag e 3.3 V
Threshold – Input low voltage -0.5V -1.0V
– Input high voltage 2.3V- 5.5V
Consumption – Core consumption: 1000mW, reduced power mode avail-
able.
Environment – Ambient temperature: 0C - 70C (32F - 158F)
– Industrial grade: -40C - 85C. (-49F - 185F)
Package – 208-pin plastic BGA packa ge
Techno logy – CMOS 0.18 micron
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