ST MK68901 User Manual
68901N04
MK68901
MULTI±FUNCTION PERIPHERAL
.8 INPUT/OUTPUT PINS
•Individually programmable direction
•Individual interrupt source capability
. - Programmable edge selection
16 SOURCE INTERRUPT CONTROLLER
•8 Internal sources
•8 External sources
•Individual source enable
•Individual source masking
•Programmable interrupt service modes
-Polling
-Vector generation
- Optional In-service status
.• Daisy chaining capability
FOUR TIMERS WITH INDIVIDUALLY PROGRAMMABLE PRESCALING
•Two multimode timers
-Delay mode
-Pulse width measurement mode
-Event counter mode
•Two delay mode timers
•Independent clock input
.• Time out output option SINGLE CHANNEL USART
•Full Duplex
•Asynchronous to 65 kbps
•Byte synchronous to 1 Mbps
•Internal/External baud rate generation
•DMA handshake signals
•Modem control
.• Loop back mode
.68000 BUS COMPATIBLE 48 PIN DIP OR 52 PIN PLCC
DESCRIPTION
The MK68901 MFP (Multi-Function Peripheral) is a combination of many of the necessary peripheral functions in a microprocessor system.
Included are :
Eight parallel I/O lines
Interrrupt controller for 16 sources
Four timers
Single channel full duplex USART
The use of the MFP in a system can significantly reduce chip count, thereby reducing system cost. The MFP is completely 68000 bus compatible, and 24 directly addressable internal registers provide the ne-
1
DPIP48 |
PLCC52 |
Figure 1 : Pin connections.
MFP
December 1988 |
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MK68901
necessary control and status interface to the programmer.
The MFP is a derivative of the MK3801 STI, a Z80 family peripheral.
PIN DESCRIPTION
GND : Ground
VCC : +5 volts (± 5%)
CS : Chip Select (input, active, low). CS is u- sed to select the MK68901 MFP for accesses to the internal registers. CS and IACK must not be asserted at the same time.
DS : Data Strobe (input, active low). DS is u- sed as part of the chip select and interrupt acknowledge functions.
R/W : Read/Write (input). R/W is the signal from the bus master indicating whether the current bus cycle is a Read (High) or Write (Low) cycle.
DTACK : Data Transfer Acknowledge. (output, active low, tri-stateable) DTACK is used to signal the bus master that data is ready, or that data has been accepted by the MK68901 MFP.
A1-A5 : Address Bus (inputs). The adress bus is used to adress one of the internal registers during a read or write cycle.
D0-D7 : Data Bus (bi-directional, tri-stateable). The data bus is used to receive data from or transmit data to one of the internal registers during a read or write cycle. It is also used to pass a vector during an interrupt acknowledge cycle.
CLK : Clock (input). This input is used to provide the internal timing for the MK68901 MFP.
RESET : Device reset. (input, active low). Reset disables the USART receiver and transmitter, stops all timers and forces the timer outputs low, disables all interrupt channels and clears any pending interrupts. The General Purpose Interrupt/I/O lines will be placed in the tri-state input mode. All internal registers (except the timer, USART data registers, and transmit status register) will be cleared.
INTR : Interrupt Request (output, active low, o- pen drain). INTR is asserted when the MK68901 MFP is requesting an interrupt. INTR is negated during an interrupt ac-
knowledge cycle or by clearing the pending interrupt(s) through software.
IACK : Interrupt Acknowledge (input, active low). IACK is used to signal the MK68901 MFP that the CPU is acknowledging an interrupt. CS and IACk must not be asserted at the same time.
IEI : Interrupt Enable In (input, active low). IEI is used to signal the MK68901 MFP that no higher priority device is requesting interrupt service.
IEO : Interrupt Enable Out (output, active low). IEO is used to signal lower priority peripherals that neither the MK68901 MFP nor another higher priority peripheral is requesting interrupt service.
10-17 : General Purpose Interrupt I/O lines. These lines may be used as interrupt inputs and/or I/O lines. When used as interrupt inputs, their active edge is programmable. A data direction register is u- sed to define which lines are to be Hi-Z inputs and which lines are to be push-pull TTL compatible outputs.
SO : Serial Output. This is the output of the U- SART transmitter.
SI : Serial Input. This is the input to the U- SART receiver.
RC : Receiver Clock. This input controls the serial bit rate of the USART receiver.
TC : Transmitter Clock. This input controls the serial bit rate of the USART transmitter.
RR: Receiver Ready. (output, active low) DMA output for receiver, which reflects the status of Buffer Full in port number 15.
TR : Transmitter Ready. (output, active low) DMA output for transmitter, which reflects the status of Buffer Empty in port number 16.
TAO,TBO, Timer Outputs. Each of the four timers TCO,TDO:has an output which can produce a square wave. The output will change states each timer cycle ; thus one full period of the timer out signal is equal to two timer cycles. TAO or TBO can be reset (logic ºOº) by a write to TACR, or TBCR
respectively.
XTAL1, |
Timer Clock inputs. A crystal can be |
XTAL2 : |
connected between XTAL1 and XTAL2, |
|
or XTAL1 can be driven with a TTL level |
|
clock. When driving XTAL1 with a TTL le- |
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vel clock, XTAL2 must be allowed to float. When using a crystal, external capacitors are required. See figure 33. All chip accesses are independent of the timer clock.
TAI,TBI : Timer A, B inputs. Used when running the
MK68901
timers in the event count or the pulse width measurement mode. The interrupt channels associated with 14 and 13 are used for TAI and TBI, respectively. Thus, when running a timer in the pulse width
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MK68901
Figure 4 : Register Map.
Address Port N°. |
Abbreviation |
Register N ame |
0 |
GPIP |
GENERAL PURPOSE I/O |
1 |
AER |
ACTIVE EDGE REGISTER |
2 |
DDR |
DATA DIRECTION REGISTER |
3 |
IERA |
INTERRUPT ENABLE REGISTER A |
4 |
IERB |
INTERRUPT ENABLE REGISTER B |
5 |
IPRA |
INTERRUPT PENDING REGISTER A |
6 |
IPRB |
INTERRUPT PENDING REGISTER B |
7 |
ISRA |
INTERRUPT IN-SERVICE REGISTER A |
8 |
ISRB |
INTERRUPT IN-SERVICE REGISTER B |
9 |
IMRA |
INTERRUPT MASK REGISTER A |
A |
IMRB |
INTERRUPT MASK REGISTER B |
B |
VR |
VECTOR REGISTER |
C |
TACR |
TIMER A CONTROL REGISTER |
D |
TBCR |
TIMER B CONTROL REGISTER |
E |
TCDCR |
TIMERS C AND D CONTROL REGISTER |
F |
TADR |
TIMER A DATA REGISTER |
10 |
TBDR |
TIMER B DATA REGISTER |
11 |
TCDR |
TIMER C DATA REGISTER |
12 |
TDDR |
TIMER D DATA REGISTER |
13 |
SCR |
SYNC CHARACTER REGISTER |
14 |
UCR |
USART CONTROL REGISTER |
15 |
RSR |
RECEIVER STATUS REGISTER |
16 |
TSR |
TRANSMITTER STATUS REGISTER |
17 |
UDR |
USART DATA REGISTER |
INTERRUPTS
The General Purpose I/O-Interrupt Port (GPIP) provides eight I/O lines that may be operated either as inputs or outputs under software control. In addition, each line may generate an interrupt in either a positive going edge or a negative going edge of the input signal.
The GPIP has three associated registers. One allows the programmer to specify the Active Edge for each bit that will trigger an interrupt. Another register specifies the Data Direction (input or output) associated with each bit. The third register is the actual data I/O register used to input or output data to the port. These three registers are illstrated in figure 5.
The Active Edge Register (AER) allows each of the General Purpose Interrupts to provide an interrupt on either a 1-0 transition or a 0-1 transition. Writing a zero to the appropriate bit of the AER causes the associated input to produce an interrupt on the 1-0 transition. The edge bit is simply one input to an ex- clusive-or gate, with the other input coming from the input buffer ant the output going to a 1-0 transition detector. Thus, depending upon the state of the input, writing the AER can cause an interrupt-produ- cing transition, which will cause an interrupt on the associated channel, if that channel is enabled. One
would then normally configure the AER before enabling interrupts via IERA and IERB.
Note : Changing the edge bit, with the interrupt enabled, may cause an interrupt on that channel.
The Data Direction Register (DDR) is used to define 10-17 as inputs or as outputs on a bit by bit basis. Writing a zero into a bit of the DDR causes the corresponding Interrupt-I/O pin to be a Hi-Z input. Writing a one into a bit of the DDR causes the corresponding pin to be configured as a push-pull output. When data is written into the GPIP, those pins defined as inputs will remain in the Hi-Z state while those pins defined as outputs will assume the state (high or low) of their corresponding bit in the GPIP. When the GPIP is read, the data read will come directly from the corresponding bit of the GPIPregister for all pins defined as output, while the data read on all pins defined as inputs will come from the input buffers.
Each individual function in the MK68901 is provided with a unique interrupt vector that is presented to the system during the interrupt acknowledge cycle. The interrupt vector returned during the interrupt acknowledge cycle is shown in figure 6, while the vector register is shown in figure 7.
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There are 16 vector addresses generated internally by the MK68901, one for each of the 16 interrupt channels.
The Interrupt Control Registers (figure 8) provide control of interrupt processing for all I/O facilities of the MK68901. These registers allow the program-
Figure 5 : General Purpose I/O Registers.
MK68901
mer to enable or disable any or all of the 16 interrupts, providing masking for any interrupt, and provide access to the pending and in-service status of the interrupt. Optional end-of-interrupt modes are available under software control. All the interrupts are prioritized as shown in figure 9.
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Figure 6 : Interrupt Vector.
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MK68901
Figure 7 : Vector Register.
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Figure 8 : Interrupt Control Registers.
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MK68901
Figure 9 : Interrupt Control Register Definitions
Priority |
Channel |
Description |
HIGHEST |
1111 |
General Purpose Interrupt 7(I7) |
|
1110 |
General Purpose Interrupt 6(I6) |
|
1101 |
Timer A |
|
1100 |
Receive Buffer Full |
|
1011 |
Receive Error |
|
1010 |
Transmit Buffer Empty |
|
1001 |
Transmit Error |
|
1000 |
Timer B |
|
0111 |
General Purpose Interrupt 5(I5) |
|
0110 |
General Purpose Interrupt 4(I4) |
|
0101 |
Timer C |
|
0100 |
Timer D |
|
0011 |
General Purpose Interrupt 3(I3) |
|
0010 |
General Purpose Interrupt 2(I2) |
|
0001 |
General Purpose Interrupt 1(I1) |
LOWEST |
0000 |
General Purpose Interrupt 0(I0) |
Interrupts may be either polled or vectored. Each channel may be individual enabled or disabled by writing a one or a zero in the appropriate bit of Interrupt Enable Registers (IERA, IERB - see figure 8 for all registers in this section). When disabled, an interrupt channel is completely inactive. Any internal or external action which would normally produce an interrupt on that channel is ignored and any pending interrupt on that channel will be cleared by disabling that channel. Disabling an interrupt channel has no effect on the corresponding bit in Interrupt In-Ser- vice Registers (ISRA, ISRB) ; thus, if the In-service Registers are used and an interrupt is in service on that channel when the channel is disabled, it will remain in service until cleared in the normal manner. IERA and IERB are also readable.
When an interrupt is received on an enabled channel, its corresponding bit in the pending register will be set. When that channel is acknowledged it will pass its vector, and the corresponding bit in the Interrupt Pending Register (IPRA or IRPB) will be cleared. IPRA and IPRB are readable ; thus by polling IPRA and IPRB, it can be determined whether a channel has a pending interrupt. IPRA and IPRB are also writeable and a pending interrupt can be cleared without going through the acknowledge sequence by writing a zero to the appropriate bit. This allows any one bit to be cleared, without altering any other bits, simply by writing all ones except for the bit position to be cleared to IPRA or IPRB. Thus a fully polled interrupt scheme is possible. Note : writing a one to IPRA, IPRB has no effect on the interrupt pending register.
The interrupt mask registers (IMRA and IMRB) may be used to block a channel from making an interrupt request. Writing a zero into the corresponding bit of the mask register will still allow the channel to receive an interrupt and latch it into its pending bit (if that channel is enabled), but will prevent that channel from making an interrupt request. If that channel is causing an interrupt request at the time the corresponding bit in the mask register is cleared, the request will cease. If no other channel is making a request, INTR will go inactive. If the mask bit is re-en- abled, any pending interrupt is now free to resume its request unless blocked by a higher priority request for service. IMRA and IMRB are also readable
. A conceptual circuit of an interrupt channel is shown in figure 10.
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MK68901
Figure 10 : A Conceptual Circuit of an Interrupt Channel.
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There are two end-of-interrupt modes : the automatic end-of-interrupt mode and the software end-of-in- terrupt mode. The mode is selected by writing a one or a zero to the S bit of the Vector Register (VR). If the S bit of the VR is a one, all channels operate in the software end-of-interrupt mode. If the S bit is a zero, all channels operate in the automatic end-of- interrupt mode, and a reset is held on all in-service bits. In the automatic end-of-interrupt mode, the pending bit is cleared when that channel passes its vector. At that point, no further history of that interrupt remains in the MK68901 MFP. In the software end-of-interrupt mode, the in-service bit is set and the pending bit is cleared when the channel passes its vector. With the in-service bit set, no lower priority channel is allowed to request an interrupt or to pass its vector during an acknowledge sequence ; however, a lower priority channel may still receive an interrupt and latch it into the pending bit. A higher priority channel may still request an interrupt and be ac-
knowledged. The in-service bit of a particular channel may be cleared by writing a zero to the corresponding bit in ISRA or ISRB. Typically, this will be done at the conclusion of the interrupt routine just before the return. Thus no lower priority channel will be allowed to request service until the higher priority channel is complete, while channels of still higher priority will be allowed to request service. While the in-service bit is set, a second interrupt on that channel maybe received and latched into the pending bit, though no service request will be made in response to the second interrupt until the in-service bit is cleared. ISRA and ISRB may be read at any time. Only a zero may be written into any bit of ISRA and ISRB ; thus the in-service bits may be cleared in software but cannot be set in software. This allows any one bit to be cleared, without altering any other bits, simply by writing all ones except for the bit position to be cleared to ISRA or ISRB, as with IPRA and IPRB.
Figure 11 a : A Conceptual Circuit of the MK68901 MFP Daisy Chaining.
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MK68901
Figure 11 b : Daisy Chaining.
Each interrupt channel responds with a discrete 8- bit vector when acknowledged. The upper four bits of the vector are set by writing the upper four bits of the VR. The four low order bits (bit 3-bit 0) are generated by the interrupting channel.
To acknowledge an interrupt, IACK goes low, the IEI input must go low (or be tied low) and the MK68901 MFP must have an acknowledgeable interrupt pending. The Daisy Chaining capability (figure 11) requires that all parts in a chain have a common IACK. When the common IACK goes low, all parts freeze and prioritize interrupts in parallel. Then priority is passed down the chain, via IEI and IEO, until a part which has a pending interrupt is reached. The part with the pending interrupt, passes a vector, does not propagate IEO, and generates DTACK.
Figure 9 describes the 16 prioritized interrupt channels. As chown, General Purpose Interrupt 7 has the highest priority, while General Purpose Interrupt 0 is assigned the lowest priority. Each of these channels may be reprioritized, in effect, by selectively masking interrupts under software control. The binary numbers under ºchannelº correspond to the modified bits IV3, IV2, IV1 and IV0, respectively, of the Interrupt Vector for each channel (see figure 6).
Each channel has an enable bit contained in IERA or IERB, a pending latch contained in IPRA or IPRB, a mask bit contained in IMRA or IMRB, and an in± service latch contained in ISRA or ISRB. Additionally, the eight General Purpose Interrupts each have an edge bit contained in the Active Edge Register (AER), a bit to define the line as input or output contained in the Data Direction Register (DDR) and
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an I/O bit in the General Purpose Interrupt-I/O Port (GPIP).
TIMERS
There are four timers on the MK68901 MFP. Two of the timers (Timer A and Timer B) are full function timers which can perform the basic delay function and can also perform event counting, pulse width measurement, and waveform generation. The other two timers (Timer C and Timer D) are delay timers only. One or both ofthese timers canbe used to supply the baud rate clocks for the USART. All timers are prescaler/counter timers with a common independent clock input (XTAL1, XTAL2). In addition, all timers have a time-out output, function that toggles each time the timer times out.
The four timers are programmed via three Timer Control Registers and four Timer Data Registers. Timers A and B are controlled by the control registers TACR and TBCR, respectively (see figure 12), and by the data registers TADR and TBDR (figure 13). Timers C and D are controlled by the control register TCDCR (see figure 14) and two data registers TCDR and TDDR. Bits in the control registers allow the selection of operational mode, prescale, and control white the data registers are used to read the timer or write into the time constant register. Timer A and B input pins TAI and TBI, are used for the e- vent and pulse width modes for timers A and B.
With the timer stopped, no counting can occur. The timer contents will remain unaltered while the timer is stopped (unless reloaded by writing the Timer Data Register), but any residual count in the prescaler will be lost.
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MK68901
Figure 12 : Timer A and B Control Registers.
*
In the delay mode, the prescaler is always active. A count pulse will be applied to the main timer unit each time the prescribed number of timer clock cycles has elapsed. Thus, if the prescaler is programmed to divide by ten, a count pulse will be applied to the main counter every ten cycles of the timer clock.
Each time a count pulse is applied to the main counter, it will decrement its contents. The main counter is initially loaded by writing to the Timer Data Register. Each count pulse will cause the current count to decrement. When the timer has decremented down to º01º , the next count pulse will not cause it to decrement to º00º. Instead, the next count pulse will cause the timer to be reloaded from the Timer Data Register. Additionally, a ºTime outº pulse will be produced. This Time Out pulse is coupled to the timer interrupt channel, and, if that channel is enabled, an interrupt will be produced. The Time Out pulse is also coupled to the timer output pin and will cause the pin to change states. The output will remain in this new state until the next Time Out pulse occurs. Thus the output will complete one full cycle for each two Time Out pulses.
If, for example, the prescaler were programmed to divide by ten, and the Timer Data Register were loa-
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ded with 100 (decimal), the main counter would decrement once for every ten cycles of the timer clock. A Time Out pulse will occur (hence an interrupt if that channel is enabled) every 1000 cycles of the timer clock, and the timer output will complete one full cycle every 2000 cycles of the timer clock.
The main counter is an 8-bit binary down counter. It may be read at any time by reading the Timer Data Register. The information read is the information last clocked into the timer read register when the DS pin had last gone high prior to the current read cycle. When written, data is loaded into the Timer Data Register, and the main counter, if the timer is stopped. If the Timer Data Register is written while the timer is running, the new word is not loaded into the timer until it counts through Hº01º. However, if the timer is written while it is counting through Hº01º, an indeterminate value will be written into the timer constant register. This may be circumvented by ensuring that the data register is not written when the count is Hº01º.
If the main counter is loaded with º01º, a Time Out Pulse will occur every time the prescaler presents a count pulse to the main counter. If loaded with º00º, a Time Out pulse will occur every 256 count pulses.
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