ST M95M02-DR User Manual

Features

SO8N (MN)

150 mils width

WLCSP (CS)

■ Compatible with the Serial Peripheral Interface

(SPI) bus

■ Memory array

– 2 Mb (256 Kbytes) of EEPROM
– Page size: 256 bytes

■ Additional Write lockable Page (Identification

page)

■ Write

– Byte Write within 10 ms
– Page Write within 10 ms

■ Write Protect: quarter, half or whole memory

array

■ Clock frequency: 5 MHz

■ Single supply voltage: 1.8 V to 5.5 V

■ More than 1 million Write cycles

■ More than 40-year data retention

■ Enhanced ESD Protection

■ Packages

– RoHS compliant and Halogen-free

(ECOPACK2

®

)

M95M02-DR

2 Mbit serial SPI bus EEPROM

October 2011 Doc ID 18203 Rev 5 1/40

www.st.com

1

Contents M95M02-DR

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.4 Chip Select (S

2.5 Hold (HOLD

2.6 Write Protect (W

2.7 V

2.8 V

supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

CC

ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SS

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1.1 Operating supply voltage V

4.1.2 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1.3 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.2 Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.3 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.5 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.3 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.3.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2/40 Doc ID 18203 Rev 5

M95M02-DR Contents

6.3.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.3.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.3.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.4 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.5 Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.6 Read Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.7 Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.8 Write Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.9 Read Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.10 Lock ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7 ECC (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . 29

8 Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8.2 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

9 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

10 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

11 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

12 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Doc ID 18203 Rev 5 3/40

List of tables M95M02-DR

List of tables

Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 3. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 4. Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 5. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 6. Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 8. Memory cell characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 9. Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 10. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 11. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 12. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 13. AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 14. SO8 narrow – 8 lead plastic small outline, 150 mils body width,

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 15. M95M02-DR WLCSP package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 16. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 17. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4/40 Doc ID 18203 Rev 5

M95M02-DR List of figures

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. SO8N connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3. WLSCP connections (bump side view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 5. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 6. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 7. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 8. Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 9. Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 10. Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 11. Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 12. Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 13. Read Identification Page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 14. Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 15. Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 16. Write Identification Page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 17. Read Lock Status sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 18. Lock ID sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 19. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 20. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 21. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 22. Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 23. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . 36

Figure 24. M95M02-DR WLCSP package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Doc ID 18203 Rev 5 5/40

Description M95M02-DR

AI01789C

S

V

CC

M95xxx

HOLD

V

SS

W

Q

C

D

1 Description

The M95M02-DR device is a 2-Mbit electrically erasable programmable memory (EEPROM)

accessed by an SPI bus. The memory array size is 256 Kbytes. It can also be seen as 1024

pages of 256 bytes each. The M95M02-DR operates from a supply voltage in the range of

1.8 V to 5.5 V.

The M95M02-DR device offers an additional 256-byte page, named the Identification Page,

which can be written and (later) permanently locked in Read-only mode. This Identification

Page offers flexibility in the application board production line, as it can be used to store

unique identification parameters and/or parameters specific to the production line.

Figure 1. Logic diagram

Table 1. Signal names

Signal name Function Direction

C Serial Clock Input

D Serial Data Input Input

Q Serial Data Output Output

S Chip Select Input

Write Protect Input

W

HOLD

Hold Input

V

CC

V

6/40 Doc ID 18203 Rev 5

SS

Supply voltage

Ground

M95M02-DR Description

DV

SS

C

HOLDQ

S V

CC

W

AI01790D

M95xxx

1
2

3

4

8

7
6
5

$

-36

3



.#.#

.#.#

1



7



6

33



$

#

6

##

7

(/,$

!

"

#





Figure 2. SO8N connections

1. See Section 11: Package mechanical data for package dimensions, and how to identify pin-1.

Figure 3. WLSCP connections (bump side view)

1. See Section 11: Package mechanical data for package dimensions, and how to identify pin-1.

2. NC stands for “not connected”. These balls have no electrical function but feature a better package
mechanical robustness after soldering.

Doc ID 18203 Rev 5 7/40

Signal description M95M02-DR

2 Signal description

During all operations, VCC must be held stable and within the specified valid range:
V

(min) to VCC(max).

CC

All of the input and output signals must be held high or low (according to voltages of V
V

, VIL or VOL, as specified in Ta bl e 1 2 ). These signals are described next.

OH

2.1 Serial Data output (Q)

This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).

2.2 Serial Data input (D)

This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be written. Values are latched on the rising edge of Serial Clock
(C).

,

IH

2.3 Serial Clock (C)

This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) changes after the falling edge of Serial Clock (C).

2.4 Chip Select (S)

When this input signal is high, the device is deselected and Serial Data Output (Q) is at high
impedance. Unless an internal Write cycle is in progress, the device will be in the Standby
Power mode. Driving Chip Select (S
mode.

After Power-up, a falling edge on Chip Select (S
instruction.

2.5 Hold (HOLD)

The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.

During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.

To start the Hold condition, the device must be selected, with Chip Select (S

) low selects the device, placing it in the Active Power

) is required prior to the start of any

) driven low.

8/40 Doc ID 18203 Rev 5

M95M02-DR Signal description

2.6 Write Protect (W)

The main purpose of this input signal is to freeze the size of the area of memory that is
protected against Write instructions (as specified by the values in the BP1 and BP0 bits of
the Status Register).

This pin must be driven either high or low, and must be stable during all write instructions.

2.7 VCC supply voltage

VCC is the supply voltage.

2.8 VSS ground

VSS is the reference for the VCC supply voltage.

Doc ID 18203 Rev 5 9/40

Connecting to the SPI bus M95M02-DR

30)BUSMASTER

3$/

3$)

3#+

#1$

#1$#1$

#3 #3 #3

30)INTERFACEWITH
#0/,#0(!

OR

30)MEMORY
DEVICE

3

7

(/,$

222

6

##

6

##

6

##

6

##

-36

6

33

30)MEMORY
DEVICE

3

7

(/,$

30)MEMORY
DEVICE

3

7

(/,$

3 Connecting to the SPI bus

These devices are fully compatible with the SPI protocol.

All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S

All output data bytes are shifted out of the device, most significant bit first. The Serial Data
Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction
(such as the Read from Memory Array and Read Status Register instructions) have been
clocked into the device.

Figure 4. Bus master and memory devices on the SPI bus

) goes low.

1. The Write Protect (W) and Hold (HOLD) signals should be driven high or low as appropriate.

Figure 4 shows an example of three memory devices connected to an MCU, on an SPI bus.

Only one device is selected at a time, so only one device drives the Serial Data Output (Q)
line at a time, the other devices are high impedance.

A pull-up resistor connected on each S

input (represented in Figure 4) ensures that each

device is not selected if the bus master leaves the S

In applications where the bus master might enter a state where the whole input/output SPI
bus is high-impedance at a given time (for example, if the bus master is reset during the
transmission of an instruction), the clock line (C) must be connected to an external pull­down resistor so that, if all inputs/outputs become high impedance, the C line is pulled low
(while the S
time, and so, that the t

10/40 Doc ID 18203 Rev 5

line is pulled high). This ensures that S and C do not become high at the same

requirement is met.

SHCH

line in the high impedance state.

M95M02-DR Connecting to the SPI bus

AI01438B

C

MSB

CPHA

D

0

1

CPOL

0

1

Q

C

MSB

3.1 SPI modes

These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:

● CPOL=0, CPHA=0

● CPOL=1, CPHA=1

For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).

The difference between the two modes, as shown in Figure 5, is the clock polarity when the
bus master is in Standby mode and not transferring data:

● C remains at 0 for (CPOL=0, CPHA=0)

● C remains at 1 for (CPOL=1, CPHA=1)

Figure 5. SPI modes supported

Doc ID 18203 Rev 5 11/40

Operating features M95M02-DR

4 Operating features

4.1 Supply voltage (VCC)

4.1.1 Operating supply voltage V

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [V

(min), VCC(max)] range must be applied (see Ta bl e 9 .). This voltage

CC

must remain stable and valid until the end of the transmission of the instruction and, for a
Write instruction, until the completion of the internal write cycle (t
stable DC supply voltage, it is recommended to decouple the V
capacitor (usually of the order of 10 nF to 100 nF) close to the V

4.1.2 Device reset

In order to prevent inadvertent write operations during power-up, a power on reset (POR)
circuit is included. At power-up, the device does not respond to any instruction until V
reaches the internal reset threshold voltage (this threshold is lower than the minimum V
operating voltage defined in Ta b l e 9 .

When V

● in Standby Power mode

● deselected (note that, to be executed, an instruction must be preceded by a falling

● Status Register value:

passes over the POR threshold, the device is reset and in the following state:

CC

edge on Chip Select (S

))

– the Write Enable Latch (WEL) is reset to 0
– Write In Progress (WIP) is reset to 0
– The SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits)

CC

). In order to secure a

W

line with a suitable

CC

CC/VSS

package pins.

CC

CC

When V

passes over the POR threshold, the device is reset and enters the Standby

CC

Power mode. The device must not be accessed until V
voltage within the specified [V

(min), VCC(max)] range defined in Ta b le 9 .

CC

4.1.3 Power-up conditions

When the power supply is turned on, VCC rises continuously from VSS to VCC. During this
time, the Chip Select (S
therefore recommended to connect the S

Figure 4).

In addition, the Chip Select (S
sensitive as well as level-sensitive: after power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S
(S

) must have been high, prior to going low to start the first operation.

The V

voltage has to rise continuously from 0 V up to the minimum VCC operating voltage

CC

defined in Ta bl e 9 and the rise time must not vary faster than 1 V/µs.

12/40 Doc ID 18203 Rev 5

) line is not allowed to float but should follow the VCC voltage, it is

line to VCC via a suitable pull-up resistor (see

) input offers a built-in safety feature, as the S input is edge-

reaches a valid and stable VCC

CC

). This ensures that Chip Select

M95M02-DR Operating features

AI02029D

HOLD

C

Hold

Condition

Hold

Condition

4.1.4 Power-down

During power-down (continuous decrease in the VCC supply voltage below the minimum
V

operating voltage defined in Ta b le 9 ), the device must be:

CC

● deselected (Chip Select S should be allowed to follow the voltage applied on V

● in Standby Power mode (there should not be any internal write cycle in progress).

CC

)

4.2 Active Power and Standby Power modes

When Chip Select (S) is low, the device is selected, and in the Active Power mode. The
device consumes I

When Chip Select (S

, as specified in Ta bl e 1 2 .

CC

) is high, the device is deselected. If a Write cycle is not currently in
progress, the device then goes in to the Standby Power mode, and the device consumption
drops to I

CC1

.

4.3 Hold condition

The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.

During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.

To enter the Hold condition, the device must be selected, with Chip Select (S

) low.

Normally, the device is kept selected, for the whole duration of the Hold condition.
Deselecting the device while it is in the Hold condition, has the effect of resetting the state of
the device, and this mechanism can be used if it is required to reset any processes that had
been in progress.

The Hold condition starts when the Hold (HOLD

) signal is driven low at the same time as

Serial Clock (C) already being low (as shown in Figure 6).

The Hold condition ends when the Hold (HOLD

) signal is driven high at the same time as

Serial Clock (C) already being low.

Figure 6 also shows what happens if the rising and falling edges are not timed to coincide

with Serial Clock (C) being low.

Figure 6. Hold condition activation

Doc ID 18203 Rev 5 13/40

Operating features M95M02-DR

4.4 Status Register

Figure 7 shows the position of the Status Register in the control logic of the device. The

Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a
detailed description of the Status Register bits

4.5 Data protection and protocol control

Non-volatile memory devices can be used in environments that are particularly noisy, and
within applications that could experience problems if memory bytes are corrupted.
Consequently, the device features the following data protection mechanisms:

● Write and Write Status Register instructions are checked that they consist of a number

of clock pulses that is a multiple of eight, before they are accepted for execution.

● All instructions that modify data must be preceded by a Write Enable (WREN)

instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:

–Power-up
– Write Disable (WRDI) instruction completion
– Write Status Register (WRSR) instruction completion
– Write (WRITE) instruction completion

● The Block Protect (BP1, BP0) bits in the Status Register allow part of the memory to be

configured as read-only.

● The Write Protect (W) signal allows the Block Protect (BP1, BP0) bits of the Status

Register to be protected.

For any instruction to be accepted, and executed, Chip Select (S

) must be driven high after
the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising
edge of Serial Clock (C).

Two points need to be noted in the previous sentence:

● The ‘last bit of the instruction’ can be the eighth bit of the instruction code, or the eighth

bit of a data byte, depending on the instruction (except for Read Status Register
(RDSR) and Read (READ) instructions).

● The ‘next rising edge of Serial Clock (C)’ might (or might not) be the next bus

transaction for some other device on the SPI bus.

Table 2. Write-protected block size

Status Register bits

Protected block

BP1 BP0

0 0 none none

0 1 Upper quarter 3 0000h - 3 FFFFh

1 0 Upper half 2 0000h - 3 FFFFh

1 1 Whole memory 0 0000h - 3 FFFFh

Array addresses

protected

14/40 Doc ID 18203 Rev 5

M95M02-DR Memory organization

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5 Memory organization

The memory is organized as shown in Figure 7.

Figure 7. Block diagram

Doc ID 18203 Rev 5 15/40

Instructions M95M02-DR

6 Instructions

Each instruction starts with a single-byte code, as summarized in Ta b le 3 .

If an invalid instruction is sent (one not contained in Ta b le 3 ), the device automatically
deselects itself.

Table 3. Instruction set

Instruction Description Instruction format

WREN Write Enable 0000 0110

WRDI Write Disable 0000 0100

RDSR Read Status Register 0000 0101

WRSR Write Status Register 0000 0001

READ Read from Memory Array 0000 0011

WRITE Write to Memory Array 0000 0010

Read Identification Page Reads the page dedicated to identification 1000 0011

(1)

Write Identification
Page

Read Lock Status Reads the lock status of the Identification Page 1000 0011

Lock ID Locks the Identification page in read-only mode 1000 0010

1. Address bit A10 must be 0, all other address bits are Don't Care.

2. Address bit A10 must be 1, all other address bits are Don't Care.

Writes the page dedicated to identification 1000 0010

6.1 Write Enable (WREN)

The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.

As shown in Figure 8, to send this instruction to the device, Chip Select (S
and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then
enters a wait state. It waits for a the device to be deselected, by Chip Select (S
high.

(1)

(2)

(2)

) is driven low,

) being driven

16/40 Doc ID 18203 Rev 5

M95M02-DR Instructions

C

D

AI02281E

S

Q

21 34567

High Impedance

0

Instruction

C

D

AI03750D

S

Q

21 34567

High Impedance

0

Instruction

Figure 8. Write Enable (WREN) sequence

6.2 Write Disable (WRDI)

One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.

As shown in Figure 9, to send this instruction to the device, Chip Select (S

) is driven low,

and the bits of the instruction byte are shifted in, on Serial Data Input (D).

The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S

) being driven high.

The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:

● Power-up

● WRDI instruction execution

● WRSR instruction completion

● WRITE instruction completion.

Figure 9. Write Disable (WRDI) sequence

Doc ID 18203 Rev 5 17/40

Instructions M95M02-DR

6.3 Read Status Register (RDSR)

The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Write or Write Status Register cycle
is in progress. When one of these cycles is in progress, it is recommended to check the
Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible
to read the Status Register continuously, as shown in Figure 10.

The status and control bits of the Status Register are as follows:

6.3.1 WIP bit

The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.

6.3.2 WEL bit

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write or Write Status Register instruction is accepted.

6.3.3 BP1, BP0 bits

The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to
1, the relevant memory area (as defined in Ta bl e 4 ) becomes protected against Write
(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set.

6.3.4 SRWD bit

The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W
signal allow the device to be put in the Hardware Protected mode (when the Status Register
Write Disable (SRWD) bit is set to 1, and Write Protect (W
non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the
Write Status Register (WRSR) instruction is no longer accepted for execution.

Table 4. Status Register format

b7 b0

SRWD 0 0 0 BP1 BP0 WEL WIP

Status Register Write Protect

) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)

) is driven low). In this mode, the

Block Protect Bits

Write Enable Latch Bit

Write In Progress Bit

18/40 Doc ID 18203 Rev 5

M95M02-DR Instructions

C

D

S

21 3456789101112131415

Instruction

0

AI02031E

Q

7 6543210

Status Register Out

High Impedance

MSB

7 6543210

Status Register Out

MSB

7

Figure 10. Read Status Register (RDSR) sequence

6.4 Write Status Register (WRSR)

The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed. After the Write Enable (WREN) instruction has been decoded and
executed, the device sets the Write Enable Latch (WEL).

The Write Status Register (WRSR) instruction is entered by driving Chip Select (S

) low,

followed by the instruction code and the data byte on Serial Data Input (D).

The instruction sequence is shown in Figure 11.

The Write Status Register (WRSR) instruction has no effect on b6, b5, b4, b1 and b0 of the
Status Register. b6, b5 and b4 are always read as 0.

Chip Select (S

) must be driven high after the rising edge of Serial Clock (C) that latches in
the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise,
the Write Status Register (WRSR) instruction is not properly executed. As soon as Chip
Select (S

) is driven high, the self-timed Write Status Register cycle (whose duration is tW) is
initiated. While the Write Status Register cycle is in progress, the Status Register may still
be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP)
bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed.
When the cycle is completed, the Write Enable Latch (WEL) is reset.

Doc ID 18203 Rev 5 19/40

Instructions M95M02-DR

C

D

AI02282D

S

Q

21 3456789101112131415

High Impedance

Instruction Status

Register In

0

765432 0

1

MSB

Figure 11. Write Status Register (WRSR) sequence

Table 5. Protection modes

W

SRWD

Signal

Bit

10

00

11

Mode

Software

Protected

(SPM)

Write Protection of the

Status Register

Status Register is Writable
(if the WREN instruction
has set the WEL bit)

The values in the BP1 and
BP0 bits can be changed

Protected area

Write Protected

Memory content

(1)

Unprotected area

Ready to accept
Write instructions

(1)

Status Register is

Hardware

01

Protected

(HPM)

Hardware write protected
The values in the BP1 and

BP0 bits cannot be

Write Protected

Ready to accept
Write instructions

changed

1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 5.

The Write Status Register (WRSR) instruction allows the user to change the values of the
Block Protect (BP1, BP0) bits, to define the size of the area that is to be treated as read­only, as defined in Ta bl e 4 .

The Write Status Register (WRSR) instruction also allows the user to set or reset the Status
Register Write Disable (SRWD) bit in accordance with the Write Protect (W
Status Register Write Disable (SRWD) bit and Write Protect (W

) signal allow the device to

) signal. The

be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR)
instruction is not executed once the Hardware Protected Mode (HPM) is entered.

The contents of the Status Register Write Disable (SRWD) and Block Protect (BP1, BP0)
bits are frozen at their current values from just before the start of the execution of Write
Status Register (WRSR) instruction. The new, updated, values take effect at the moment of
completion of the execution of Write Status Register (WRSR) instruction.

The protection features of the device are summarized in Ta bl e 2 .

20/40 Doc ID 18203 Rev 5

M95M02-DR Instructions

When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of the whether Write Protect (W

) is driven high or low.

When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two
cases need to be considered, depending on the state of Write Protect (W

● If Write Protect (W) is driven high, it is possible to write to the Status Register provided

):

that the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction.

● If Write Protect (W) is driven low, it is not possible to write to the Status Register even if

the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN)
instruction. (Attempts to write to the Status Register are rejected, and are not accepted
for execution). As a consequence, all the data bytes in the memory area that are
software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register,
are also hardware protected against data modification.

Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be
entered:

● by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W)

low

● or by driving Write Protect (W) low after setting the Status Register Write Disable

(SRWD) bit.

The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write
Protect (W

If Write Protect (W

) high.

) is permanently tied high, the Hardware Protected Mode (HPM) can
never be activated, and only the Software Protected Mode (SPM), using the Block Protect
(BP1, BP0) bits of the Status Register, can be used.

Doc ID 18203 Rev 5 21/40

Instructions M95M02-DR

C

D

AI13878

S

Q

23

21 345678910 2829303132333435

2221 3210

36 37 38

76543 1 7

0

High Impedance

Data Out 1

Instruction 24-bit address

0

MSB

MSB

2

39

Data Out 2

6.5 Read from Memory Array (READ)

As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data
Input (D). The address is loaded into an internal address register, and the byte of data at
that address is shifted out, on Serial Data Output (Q).

If Chip Select (S

) continues to be driven low, the internal address register is automatically

incremented, and the byte of data at the new address is shifted out.

When the highest address is reached, the address counter rolls over to zero, allowing the
Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a
single READ instruction.

The Read cycle is terminated by driving Chip Select (S
Select (S

) signal can occur at any time during the cycle.

) high. The rising edge of the Chip

The first byte addressed can be any byte within any page.

The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.

Figure 12. Read from Memory Array (READ) sequence

1. As shown in Table 6, the most significant address bits are Don’t Care.

Table 6. Address range bits

(1)

M95M02-DR

Address bits A17-A0

1. Bits A23 to A18 are Don’t Care.

22/40 Doc ID 18203 Rev 5

M95M02-DR Instructions

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6.6 Read Identification Page

The Identification Page (256 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode.

Reading this page is achieved with the Read Identification Page instruction (see Tab le 3 ).
The Chip Select signal (S) is first driven low, the bits of the instruction byte and address
bytes are then shifted in, on Serial Data input (D). Address bit A10 must be 0, address bits
[A17:A11] and [A9:A8] are Don't Care, and the data byte pointed to by [A7:A0] is shifted out
on Serial Data output (Q).

If Chip Select (S

) continues to be driven low, the internal address register is automatically

incremented, and the byte of data at the new address is shifted out.

Note: The number of bytes to read from the ID page must not exceed the page boundary (e.g.:

when reading the ID page from location 100d, the number of bytes should be less than or
equal to 156d, as the ID page is 256 bytes wide).

The read cycle is terminated by driving Chip Select (S
Select (S

) signal can occur at any time during the cycle. The first byte addressed can be any

) high. The rising edge of the Chip

byte within any page.

The instruction is not accepted, and is not executed, if a write cycle is currently in progress.

Figure 13. Read Identification Page sequence

Doc ID 18203 Rev 5 23/40

Instructions M95M02-DR

C

D

AI13879

S

Q

23

21 345678910 2829303132333435

1413 3210

36 37 38

High Impedance

Instruction 24-bit address

0

765432 0

1

Data byte

39

6.7 Write to Memory Array (WRITE)

As shown in Figure 14, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte, address byte, and at least one data byte are then shifted
in, on Serial Data Input (D).

The instruction is terminated by driving Chip Select (S

) high at a byte boundary of the input
data. In the case of Figure 14, this occurs after the eighth bit of the data byte has been
latched in, indicating that the instruction is being used to write a single byte. The self-timed
Write cycle starts, and continues for a period t

(as specified in Ta bl e 1 3), at the end of

WC

which the Write in Progress (WIP) bit is reset to 0.

If, though, Chip Select (S

) continues to be driven low, as shown in Figure 15, the next byte of
input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal Write cycle. The self­timed Write cycle starts, and continues, for a period t

(as specified in Ta b le 1 3 ), at the

WC

end of which the Write in Progress (WIP) bit is reset to 0.

Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If the number of data bytes sent to the device exceeds the page
boundary, the internal address counter rolls over to the beginning of the page, and the
previous data there are overwritten with the incoming data. (The page size is 256 bytes).

The instruction is not accepted, and is not executed, under the following conditions:

● if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable

instruction just before)

● if a Write cycle is already in progress

● if the device has not been deselected, by Chip Select (S) being driven high, at a byte

boundary (after the eighth bit, b0, of the last data byte that has been latched in)

● if the addressed page is in the region protected by the Block Protect (BP1 and BP0)

bits.

Note: The self-timed write cycle, t

, is internally executed as a sequence of two consecutive

W

events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is
read as “0” and a programmed bit is read as “1”.

Figure 14. Byte Write (WRITE) sequence

24/40 Doc ID 18203 Rev 5

1. As shown in Table 6, the most significant address bits are Don’t Care.

M95M02-DR Instructions

C

D

AI13880

S

3433 35 36 37 38 39 40 41 42 44 45 46 4732

C

D

S

15

21 345678910 2829303132333435

1413 3210

36 37 38

Instruction 24-bit address

0

765432 0

1

Data byte 1

39

43

765432 0

1

Data byte 2

765432 0

1

Data byte 3

65432 0

1

Data byte N

Figure 15. Page Write (WRITE) sequence

1. As shown in Table 6, the most significant address bits are Don’t Care.

Doc ID 18203 Rev 5 25/40

Instructions M95M02-DR

6.8 Write Identification Page

The Identification Page (256 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode. Writing this page is achieved with the Write
Identification Page instruction (see Ta bl e 3 ), the Chip Select signal (S) is first driven low. The
bits of the instruction byte, address byte, and at least one data byte are then shifted in on
Serial Data input (D). Address bit A10 must be 0, address bits [A23:A11] and [A9:A8] are
Don't Care, the [A7:A0] address bits define the byte address inside the identification page.

The instruction is terminated by driving Chip Select (S
data. The self-timed write cycle triggered by the rising edge of Chip Select (S
a period t

(as specified in Ta bl e 1 3), at the end of which the Write in Progress (WIP) bit is

W

) high at a byte boundary of the input

) continues for

reset to 0.

In the case of Figure 16, Chip Select (S

) is driven high after the eighth bit of the data byte
has been latched in, indicating that the instruction is being used to write a single byte.
However, if Chip Select (S

) continues to be driven low, as shown in Figure 16, the next byte
of input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal write cycle. Each time
a new data byte is shifted in, the least significant bits of the internal address counter are
incremented.

The instruction is not accepted, and is not executed, under the following conditions:

● if the Write Enable Latch (WEL) bit has not been set to 1 (by previously executing a

Write Enable instruction)

● if Status register bits (BP1, BP0) = (1, 1)

● if a write cycle is already in progress

● if the device has not been deselected, by Chip Select (S) being driven high, at a byte

boundary (after the eighth bit, b0, of the last data byte that was latched in)

● if the Identification page is locked by the Lock Status bit

Figure 16. Write Identification Page sequence

3

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6.9 Read Lock Status

The Read Lock Status instruction (see Ta bl e 3 ) is used to check if the Identification Page is
locked (or not) in read-only mode. The Read Lock Status sequence is defined with the Chip
Select (S) first driven low. The bits of the instruction byte and address bytes are then shifted
in on Serial Data input (D). Address bit A10 must be 1, all other address bits are Don't Care.
The Lock bit is the LSB (least significant bit) of the byte read on Serial Data output (Q). It is
at ‘1’ when the lock is active and at ‘0’ when the lock is not active. If Chip Select (S
continues to be driven low, the same data byte is shifted out. The read cycle is terminated by
driving Chip Select (S

) high.

Figure 17. Read Lock Status sequence

)

6.10 Lock ID

The Lock ID instruction permanently locks the Identification Page in read-only mode. Before
this instruction can be accepted, a Write Enable (WREN) instruction must have been
executed. The Lock ID instruction (see Ta b le 3 ) is issued by driving Chip Select (S
sending the instruction code, the address and a data byte on Serial Data input (D), and
driving Chip Select (S

) high. In the address sent, A10 must be equal to 1, all other address
bits are Don't Care. The data byte sent must be equal to the binary value xxxx xx1x, where x
= Don't Care.

Chip Select (S

) must be driven high after the rising edge of Serial Clock (C) that latches in
the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise,
the Lock ID instruction is not executed.

Driving Chip Select (S
cycle whose duration is t

) high at a byte boundary of the input data triggers the self-timed write

(specified in Tab le 1 3 ).

W

Doc ID 18203 Rev 5 27/40

) low,

Instructions M95M02-DR

The instruction is not accepted, and so not executed, under the following conditions:

● if the Write Enable Latch (WEL) bit has not been set to 1 (by previously executing a

Write Enable instruction)

● if Status register bits (BP1,BP0) = (1,1)

● if a write cycle is already in progress

● if the device has not been deselected, by Chip Select (S) being driven high, at a byte

boundary (after the eighth bit, b0, of the last data byte that was latched in)

● if the Identification page is locked by the Lock Status bit

Figure 18. Lock ID sequence

3

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28/40 Doc ID 18203 Rev 5

M95M02-DR ECC (error correction code) and write cycling

7 ECC (error correction code) and write cycling

The error correction code (ECC) is an internal reliability feature which is transparent for the
SPI communication protocol.

The ECC logic compares each group of four bytes
ECC. As a result, if a single bit out of these four bytes happens to be erroneous during a
read operation, the ECC detects it and replaces it with the correct value. The read reliability
is therefore much improved.

When a single byte has to be written, the ECC function refreshes the three other bytes of the
same group. Single bytes can be written/cycled independently, making sure that the total
cycling of each group does not exceed the cycling limit defined in Table 8: Memory cell

characteristics.

8 Power-up and delivery state

8.1 Power-up state

After power-up, the device is in the following state:

● Standby Power mode

● Deselected (after power-up, a falling edge is required on Chip Select (S) before any

instructions can be started).

● Not in the Hold condition

● Write Enable Latch (WEL) is reset to 0

● Write In Progress (WIP) is reset to 0

with its associated six EEPROM bits of

The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous
power-down (they are non-volatile bits).

8.2 Initial delivery state

The device is delivered with the memory array set at all 1s (FFh). The Status Register Write
Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.

Doc ID 18203 Rev 5 29/40

Maximum rating M95M02-DR

9 Maximum rating

Stressing the device outside the ratings listed in Ta bl e 7 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. Refer also to the STMicroelectronics SURE Program and other relevant
quality documents.

Table 7. Absolute maximum ratings

Symbol Parameter Min. Max. Unit

Ambient temperature with power applied –40 130 °C

T

STG

T

LEAD

V

V

V

CC

I

OL

I

OH

V

ESD

1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®

7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU

2. Positive and negative pulses applied on pin pairs, according to the AEC-Q100-002 (compliant with

JEDEC Std JESD22-A114, C1=100 pF, R1=1500 Ω, R2=500 Ω).

Storage temperature –65 150 °C

Lead temperature during soldering See note

Output voltage –0.50 VCC+0.6 V

O

Input voltage –0.50 6.5 V

I

Supply voltage –0.50 6.5 V

DC output current (Q = 0) 5 mA

DC output current (Q = 1) –5 mA

Electrostatic discharge voltage (human body model)

(2)

(1)

°C

3000 V

30/40 Doc ID 18203 Rev 5

M95M02-DR DC and AC parameters

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10 DC and AC parameters

This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device.

Table 8. Memory cell characteristics

Symbol Parameter Test condition Min. Max. Unit

(1)

Ncycle

1. The Write cycle performance is defined for each EEPROM cell. A Write cycle is executed when either a

Page Write, a Byte Write, or a WRSR instruction is decoded. When using the Byte Write or Page Write,
refer also to Section 7: ECC (error correction code) and write cycling.

2. This parameter is not tested but established by characterization and qualification. For endurance estimates

in a specific application, please refer to AN2014.

Table 9. Operating conditions

Write cycle

endurance

TA = 25 °C, 1.8 V < VCC < 5.5 V 1,000,000 Write cycle

(2)

Symbol Parameter Min. Max. Unit

V

CC

T

A

Table 10. AC measurement conditions

Supply voltage 1.8 5.5 V

Ambient operating temperature –40 85 °C

Symbol Parameter Min. Max. Unit

C

Load capacitance 30 pF

L

Input rise and fall times 25 ns

Input pulse voltages 0.2 V

Input and output timing reference voltages 0.3 V

to 0.8 V

CC

to 0.7 V

CC

CC

CC

V

V

Figure 19. AC measurement I/O waveform

Table 11. Capacitance

Symbol Parameter Test condition Min. Max. Unit

C

OUT

C

IN

1. Not 100% tested.

(1)

Output capacitance (Q) V

= 0 V 8 pF

OUT

Input capacitance (D) VIN = 0 V 8 pF

Input capacitance (other
pins)

= 0 V 6 pF

V

IN

Doc ID 18203 Rev 5 31/40

DC and AC parameters M95M02-DR

Table 12. DC characteristics

Symbol Parameter

I

Input leakage current V

LI

Output leakage current S = VCC, V

I

LO

I

Supply current (Read)

CC

(1)

I

CC0

I

V

Supply current (Write) During tW, S = VCC,3mA

Supply current

CC1

(Standby Power mode)

Input low voltage

V

IL

V

Input high voltage

IH

Output low voltage

OL

Test condition (in addition to the

conditions defined in Tab l e 9)

= VSS or V

IN

OUT

C=0.1V

1.8 V ≤ V

S = VCC, V

S

= VCC, V

/0.9 V

CC

≤ 5.5 V, Q = open

CC

IN

V

= 1.8 V

CC

IN

1.8 V ≤ V

= VCC, V

S

IN

2.5 V ≤ V

1.8 V ≤ V

2.5 V ≤ V

1.8 V ≤ V

2.5 V ≤ V

= 0.15 mA, VCC = 1.8 V 0.3 V

I

OL

= 2.5 V, IOL = 1.5 mA or VCC =

V

CC

CC

= VSS or V

CC

= VSS or V

CC

at 5 MHz,

,

CC

= VSS or VCC,

< 2.5 V

CC

= VSS or VCC,

≤ 5.5 V

CC

< 2.5 V –0.45 0.25 V

CC

≤ 5.5 V –0.45 0.3 V

CC

< 2.5 V 0.75 V

CC

≤ 5.5 V 0.7 V

CC

Min Max Unit

CCVCC

CC

5V, IOL = 2 mA

± 2 µA

± 2 µA

3mA

3µA

5µA

5µA

CC

V

CC

+1

V

VCC+1

0.4 V

I

OH

V

1. Characterized value, not tested in production.

Output high voltage

OH

V

= 2.5 V, IOH = –0.4 mA or VCC

CC

= –0.1 mA, VCC = 1.8 V

= 5 V, IOH = –2 mA

0.8 V

CC

V

32/40 Doc ID 18203 Rev 5

M95M02-DR DC and AC parameters

Table 13. AC characteristics

Test conditions specified in Tabl e 9 and Tabl e 10

Symbol Alt. Parameter Min. Max. Unit

f

C

t

SLCH

t

SHCH

t

SHSL

t

CHSH

t

CHSL

(1)

t

CH

(1)

t

CL

(2)

t

CLCH

(2)

t

CHCL

t

DVCH

t

CHDX

t

HHCH

t

HLCH

t

CLHL

t

CLHH

(2)

t

SHQZ

(3)

t

CLQV

t

CLQX

(2)

t

QLQH

(2)

t

QHQL

t

HHQV

(2)

t

HLQZ

t

W

1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max)

2. Value guaranteed by characterization, not 100% tested in production.

3. t

must be compatible with tCL (clock low time): if the SPI bus master offers a read setup time tSU =

CLQV

0ns, tCL can be equal to (or greater than) t
t

CLQV+tSU

f

SCK

t

CSS1

t

CSS2

t

t

CSH

Clock frequency D.C. 5 MHz

S active setup time 60 ns

S not active setup time 60 ns

S deselect time 90 ns

CS

S active hold time 60 ns

S not active hold time 60 ns

t

t

t

t

t

DSU

t

t

t

t

t

t

t

.

Clock high time 90 ns

CLH

Clock low time 90 ns

CLL

Clock rise time 2 µs

RC

Clock fall time 2 µs

FC

Data in setup time 20 ns

Data in hold time 20 ns

DH

Clock low hold time after HOLD
not active

Clock low hold time after HOLD
active

Clock low setup time before

active

HOLD

Clock low setup time before
HOLD not active

Output Disable time 80 ns

DIS

t

Clock low to output valid 80 ns

V

Output hold time 0 ns

HO

Output rise time 80 ns

RO

Output fall time 80 ns

FO

t

HOLD high to output valid 80 ns

LZ

HOLD low to output high-Z 80 ns

HZ

Write time 10 ms

WC

; in all other cases, tCL must be equal to (or greater than)

CLQV

60 ns

60 ns

0ns

0ns

Doc ID 18203 Rev 5 33/40

DC and AC parameters M95M02-DR

C

D

AI01447d

S

MSB IN

Q

tDVCH

High impedance

LSB IN

tSLCH

tCHDX

tCLCH

tSHCH

tSHSL

tCHSHtCHSL

tCH

tCL

tCHCL

C

Q

AI01448c

S

HOLD

tCLHL

tHLCH

tHHCH

tCLHH

tHHQVtHLQZ

Figure 20. Serial input timing

Figure 21. Hold timing

34/40 Doc ID 18203 Rev 5

M95M02-DR DC and AC parameters

C

Q

AI01449f

S

D

ADDR

LSB IN

tSHQZ

tCH

tCL

tQLQH
tQHQL

tCHCL

tCLQX

tCLQV

tSHSL

tCLCH

Figure 22. Serial output timing

Doc ID 18203 Rev 5 35/40

Package mechanical data M95M02-DR

SO-A

E1

8

ccc

b

e

A

D

c

1

E

h x 45˚

A2

k

0.25 mm

L

L1

A1

GAUGE PLANE

11 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK®

®

is an ST trademark.

Figure 23. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package

outline

1. Drawing is not to scale.

Table 14. SO8 narrow – 8 lead plastic small outline, 150 mils body width,

package mechanical data

millimeters inches

Symbol

Typ Min Max Typ Min Max

(1)

A 1.750 0.0689

A1 0.100 0.250 0.0039 0.0098

A2 1.250 0.0492

b 0.280 0.480 0.0110 0.0189

c 0.170 0.230 0.0067 0.0091

ccc 0.100 0.0039

D 4.900 4.800 5.000 0.1929 0.1890 0.1969

E 6.000 5.800 6.200 0.2362 0.2283 0.2441

E1 3.900 3.800 4.000 0.1535 0.1496 0.1575

e 1.270 – – 0.0500 - -

h 0.250 0.500 0.0098 0.0197

k0°8° 0°8°

L 0.400 1.270 0.0157 0.0500

36/40 Doc ID 18203 Rev 5

L1 1.040 0.0409

1. Values in inches are converted from mm and rounded to 4 decimal digits.

M95M02-DR Package mechanical data

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Figure 24. M95M02-DR WLCSP package outline

1. Preliminary information.

Table 15. M95M02-DR WLCSP package mechanical data

millimeters inches

Symbol

Min Typ Max Min Typ Max

(1)

(2)

A 0.260 0.290 0.320 0.0102 0.0114 0.0126

A1 0.090 0.100 0.110 0.0035 0.0039 0.0043

A2 0.180 0.195 0.210 0.0071 0.0077 0.0083

B (ball

diameter)

0.096 0.126 0.156 0.0038 0.0050 0.0062

D 3.536 3.556 3.576 0.1392 0.1400 0.1408

E 1.991 2.011 2.031 0.0784 0.0792 0.0800

e 0.500 0.0197

e1 2.100 0.0827

e2 1.000 0.0394

e3 1.400 0.0551

e4 3.250 0.128

1. Preliminary information.

2. Values in inches are converted from mm and rounded to 4 decimal digits.

Doc ID 18203 Rev 5 37/40

Part numbering M95M02-DR

12 Part numbering

Table 16. Ordering information scheme

Example: M95M02-D R MN 6 T P

Device type

M95 = SPI serial access EEPROM

Device function

M02-D = 2048 Kbits (262 144 × 8) EEPROM with
additional identification page

Operating voltage

R = V

= 1.8 V to 5.5 V

CC

Package

MN = SO8N (150 mils width)

CS = WLCSP

Device grade

6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow

Option

blank = standard packing

T = tape and reel packing

Plating technology

P or G = ECOPACK2

®

(RoHS compliant and Halogen-free)

For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.

38/40 Doc ID 18203 Rev 5

M95M02-DR Revision history

13 Revision history

Table 17. Document revision history

Date Revision Changes

15-Nov-2010 1 Initial release.

10-Dec-2010 2

10-Jan-2011 3 Updated ordering information.

10-May-2011 4

19-Oct-2011 5

Updated DC and AC characteristics according to characterization test
results.

Updated Table 13: AC characteristics and related text, and Table 12: DC

characteristics.

Changed datasheet status to full datasheet.
Modified Section 1: Description.
Added Figure 3: WLSCP connections (bump side view).
Updated Figure 4: Bus master and memory devices on the SPI bus and

Figure 7: Block diagram.

Modified Section 7: ECC (error correction code) and write cycling.
Updated Note 2 in Table 7: Absolute maximum ratings.
Added Table 8: Memory cell characteristics.
Updated Figure 24: M95M02-DR WLCSP package outline and Ta bl e 1 5 :

M95M02-DR WLCSP package mechanical data.

Updated disclaimer on last page.

Doc ID 18203 Rev 5 39/40

M95M02-DR

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40/40 Doc ID 18203 Rev 5