ST M95M01-DF, M95M01-R User Manual

M95M01-DF M95M01-R

1-Mbit serial SPI bus EEPROM

Features

■Compatible with the Serial Peripheral Interface (SPI) bus

■Memory array

–1 Mb (128 Kbytes) of EEPROM

–Page size: 256 bytes

■Write

–Byte Write within 5 ms

–Page Write within 5 ms

■Additional Write lockable page (Identification page)

■Write Protect: quarter, half or whole memory array

■High-speed clock: 16 MHz

■Single supply voltage:

–1.8 V to 5.5 V for M95M01-R

–1.7 V to 5.5 V for M95M01-DF

■Operating temperature range: from -40°C up to +85°C

■Enhanced ESD protection

■More than 4 million Write cycles

■More than 200-year data retention

■Packages

–RoHS compliant and halogen-free (ECOPACK®)

Datasheet − production data

SO8 (MN) 150 mil width

TSSOP8 (DW) 169 mil width

WLCSP (CS) (preliminary data)

July 2012

Doc ID 13264 Rev 10

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This is information on a product in full production.

www.st.com

Contents	M95M01-DF M95M01-R

Contents

1	Description .			. . .	.	.	. .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 6
2	Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .								8
3	Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .								9
	3.1	Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .							9
	3.2	Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .							9
	3.3	Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .							9
	3.4								9
		Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
	3.5	Hold							9
			(HOLD)
	3.6	Write Protect							10
							(W)
	3.7	VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .							10
	3.8	VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .							10
4	Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .								11
	4.1	SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .							12
5	Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .								13
	5.1	Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .							13
		5.1.1		Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					13
		5.1.2		Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					13
		5.1.3		Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					13
		5.1.4		Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					14
	5.2	Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . .							14
	5.3	Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .							14
	5.4	Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .							15
	5.5	Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . .							15
6	Instructions			. . .	.	.	. .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
	6.1	Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .							17
	6.2	Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .							18
	6.3	Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .							19
		6.3.1		WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					19

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6.3.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.4	Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		20
6.5	Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		22
6.6	Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		23
	6.6.1	Cycling with Error Correction Code (ECC) . . . . . . . . . . . . . . . . . . . . . .	25

6.7 Read Identification Page (available only in M95M01-D devices) . . . . . . . 26 6.8 Write Identification Page (available only in M95M01-D devices) . . . . . . . 27 6.9 Read Lock Status (available only in M95M01-Ddevices) . . . . . . . . . . . . . 28 6.10 Lock ID (available only in M95M01-D devices) . . . . . . . . . . . . . . . . . . . . . 29

7	Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		30
	7.1	Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30
	7.2	Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30
8	Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		31
9	DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		32
10	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		38
11	Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		42
12	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		43

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List of tables	M95M01-DF M95M01-R

List of tables

Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 3. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 4. M95M01-D instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 5. Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 6. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 7. Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 8. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 9. Operating conditions (M95M01-R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 10. Operating conditions (M95M01-DF, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 11. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 12. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 13. Cycling performance by groups of four bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 14. Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 15. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 16. AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 17. SO8N – 8-lead plastic small outline, 150 mils body width, mechanical data . . . . . . . . . . . 38 Table 18. TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 39 Table 19. M95M01-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package mechanical data 41 Table 20. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 21. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

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M95M01-DF M95M01-R	List of figures

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. 8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. WLCSP connections for M95M01-DFCS6TP/K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 5. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 6. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 7. Hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 8. Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 9. Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 10. Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 11. Write Status Register (WRSR) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 12. Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 13. Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 14. Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 15. Read Identification Page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 16. Write identification page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 17. Read Lock Status sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 18. Lock ID sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 19. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 20. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 21. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 22. Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 23. SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 38 Figure 24. TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 25. M95M01-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package outline . . . . . . . . 40

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Description	M95M01-DF M95M01-R

1 Description

The M95M01 devices are Electrically Erasable PROgrammable Memories (EEPROMs) organized as 131072 x 8 bits, accessed through the SPI bus.

The M95M01-R devices can operate with a supply range from 1.8 V up to 5.5 V, the M95M01-DF devices can operate with a supply range from 1.7 V up to 5.5 V. These devices are guaranteed over the -40 °C/+85 °C temperature range.

The M95M01-DF offers an additional page, named the Identification Page (256 bytes). The Identification Page can be used to store sensitive application parameters which can be (later) permanently locked in Read-only mode.

Figure 1. Logic diagram

	VCC
D	Q
C
S	M95xxx
W
HOLD

VSS

AI01789C

The SPI bus signals are C, D and Q, as shown in Figure 1 and Table 1. The device is selected when Chip Select (S) is driven low. Communications with the device can be interrupted when the HOLD is driven low.

Table 1.					Signal names
				Signal name		Function	Direction
	C					Serial Clock	Input
	D					Serial Data Input	Input
	Q					Serial Data Output	Output
						Chip Select	Input
	S
						Write Protect	Input
	W
						Hold	Input
	HOLD
	VCC					Supply voltage
	VSS					Ground

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M95M01-DF M95M01-R	Description

Figure 2. 8-pin package connections (top view)

							M95xxx
							1	8		VCC
		S
	Q					2		7		HOLD
W						3		6		C
VSS					4			5		D
								AI01790D

1. See Section 10: Package mechanical data section for package dimensions, and how to identify pin 1.

Figure 3. WLCSP connections for M95M01-DFCS6TP/K

$6##

(/,$

# 1

7

633 3

-3 6

Caution: As EEPROM cells lose their charge (and so their binary value) when exposed to ultra violet (UV) light, EEPROM dice delivered in wafer form or in WLCSP package by STMicroelectronics must never be exposed to UV light.

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Memory organization	M95M01-DF M95M01-R

2 Memory organization

The memory is organized as shown in the following figure.

Figure 4. Block diagram

	(/,$						(IGH VOLTAGE
7					#ONTROLTLOGIC
							GENERATOR

	3
	#
	$	) / SHIFTSREGISTER
	1
	!DDRESSRREGISTER	$ATA
	ANDNCOUNTER	REGISTER
		3TATUS
		REGISTER
			3IZEEOF THE
	99DECODER
			2EAD ONLY
			%%02/-
			AREA
		PAGE
		)DENTIFICATION PAGE
		88DECODER
			-3 6

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M95M01-DF M95M01-R	Signal description

3 Signal description

During all operations, VCC must be held stable and within the specified valid range: VCC(min) to VCC(max).

All of the input and output signals must be held high or low (according to voltages of VIH, VOH, VIL or VOL, as specified in Section 9: DC and AC parameters). These signals are described next.

3.1Serial Data Output (Q)

This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C).

3.2Serial Data Input (D)

This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be written. Values are latched on the rising edge of Serial Clock

(C).

3.3Serial Clock (C)

This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) change from the falling edge of Serial Clock (C).

3.4Chip Select (S)

When this input signal is high, the device is deselected and Serial Data Output (Q) is at high impedance. The device is in the Standby Power mode, unless an internal Write cycle is in progress. Driving Chip Select (S) low selects the device, placing it in the Active Power mode.

After power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction.

3.5Hold (HOLD)

The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device.

During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don’t Care.

To start the Hold condition, the device must be selected, with Chip Select (S) driven low.

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Signal description	M95M01-DF M95M01-R

3.6Write Protect (W)

The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register).

This pin must be driven either high or low, and must be stable during all Write instructions.

3.7VCC supply voltage

VCC is the supply voltage.

3.8VSS ground

VSS is the reference for all signals, including the VCC supply voltage.

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M95M01-DF M95M01-R	Connecting to the SPI bus

4 Connecting to the SPI bus

All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C) after Chip Select (S) goes low.

All output data bytes are shifted out of the device, most significant bit first. The Serial Data Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction (such as the Read from Memory Array and Read Status Register instructions) have been clocked into the device.

Figure 5. Bus master and memory devices on the SPI bus

VSS

VCC

R

SDO

SPI Interface with

SDI

(CPOL, CPHA) =

SCK

(0, 0) or (1, 1)

C Q D VCC

C Q D

VCC

C Q D VCC

SPI Bus Master

VSS

VSS

VSS

R

SPI Memory

R

SPI Memory

R

SPI Memory

Device

Device

Device

CS3

CS2 CS1

S

W

HOLD

S

W

HOLD

S

W

HOLD

AI12836b

1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.

Figure 5 shows an example of three memory devices connected to an SPI bus master. Only one memory device is selected at a time, so only one memory device drives the Serial Data Output (Q) line at a time. The other memory devices are high impedance.

The pull-up resistor R (represented in Figure 5) ensures that a device is not selected if the Bus Master leaves the S line in the high impedance state.

In applications where the Bus Master may leave all SPI bus lines in high impedance at the same time (for example, if the Bus Master is reset during the transmission of an instruction), the clock line (C) must be connected to an external pull-down resistor so that, if all inputs/outputs become high impedance, the C line is pulled low (while the S line is pulled high): this ensures that S and C do not become high at the same time, and so, that the tSHCH requirement is met. The typical value of R is 100 kΩ..

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Connecting to the SPI bus	M95M01-DF M95M01-R

4.1SPI modes

These devices can be driven by a microcontroller with its SPI peripheral running in either of the following two modes:

●CPOL=0, CPHA=0

●CPOL=1, CPHA=1

For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C).

The difference between the two modes, as shown in Figure 6, is the clock polarity when the bus master is in Stand-by mode and not transferring data:

●C remains at 0 for (CPOL=0, CPHA=0)

●C remains at 1 for (CPOL=1, CPHA=1)

Figure 6. SPI modes supported

CPOL CPHA
0	0	C
1	1	C
		D	MSB
		Q	MSB
			AI01438B

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M95M01-DF M95M01-R	Operating features

5 Operating features

5.1Supply voltage (VCC)

5.1.1Operating supply voltage VCC

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions in Section 9: DC and AC parameters). This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS device pins.

5.1.2Device reset

In order to prevent erroneous instruction decoding and inadvertent Write operations during power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not respond to any instruction until VCC reaches the POR threshold voltage. This threshold is lower than the minimum VCC operating voltage (see Operating conditions in Section 9: DC and AC parameters).

At power-up, when VCC passes over the POR threshold, the device is reset and is in the following state:

●in Standby Power mode,

●deselected,

●Status Register values:

–The Write Enable Latch (WEL) bit is reset to 0.

–The Write In Progress (WIP) bit is reset to 0.

–The SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits).

It is important to note that the device must not be accessed until VCC reaches a valid and stable level within the specified [VCC(min), VCC(max)] range, as defined under Operating conditions in Section 9: DC and AC parameters.

5.1.3Power-up conditions

When the power supply is turned on, VCC rises continuously from VSS to VCC. During this

time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage. It is

therefore recommended to connect the S line to VCC via a suitable pull-up resistor (see

Figure 5).

In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edgesensitive as well as level-sensitive: after power-up, the device does not become selected until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select

(S) must have been high, prior to going low to start the first operation.

The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage defined under Operating conditions in Section 9: DC and AC parameters, and the rise time must not vary faster than 1 V/µs.

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Operating features	M95M01-DF M95M01-R

5.1.4Power-down

During power-down (continuous decrease of the VCC supply voltage below the minimum VCC operating voltage defined under Operating conditions in Section 9: DC and AC parameters), the device must be:

●deselected (Chip Select S should be allowed to follow the voltage applied on VCC),

●in Standby Power mode (there should not be any internal write cycle in progress).

5.2Active Power and Standby Power modes

When Chip Select (S) is low, the device is selected, and in the Active Power mode. The device consumes ICC.

When Chip Select (S) is high, the device is deselected. If a Write cycle is not currently in progress, the device then goes into the Standby Power mode, and the device consumption drops to ICC1, as specified in DC characteristics (see Section 9: DC and AC parameters).

5.3Hold condition

The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence.

To enter the Hold condition, the device must be selected, with Chip Select (S) low.

During the Hold condition, the Serial Data Output (Q) is high impedance, and the Serial Data Input (D) and the Serial Clock (C) are Don’t Care.

Normally, the device is kept selected for the whole duration of the Hold condition. Deselecting the device while it is in the Hold condition has the effect of resetting the state of

the device, and this mechanism can be used if required to reset any processes that had been in progress.(a)(b)

Figure 7. Hold condition activation

c
HOLD
Hold	Hold
condition	condition
	ai02029E

The Hold condition starts when the Hold (HOLD) signal is driven low when Serial Clock (C) is already low (as shown in Figure 7).

a.This resets the internal logic, except the WEL and WIP bits of the Status Register.

b.In the specific case where the device has shifted in a Write command (Inst + Address + data bytes, each data byte being exactly 8 bits), deselecting the device also triggers the Write cycle of this decoded command.

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