查询M95080-RMN1T供应商
64Kbit and 32Kbit Serial SPI Bus EEPROM
FEATURES SUMMARY
■ Compatible with SPI Bus Serial Interface
(Positive Clock SPI Modes)
■ Single Supply Voltage:
– 4.5 to 5.5V for M95xxx
– 2.5 to 5.5V for M95xxx-W
– 1.8 to 5.5V for M95xxx-R
■ 10MHz, 5MHz or 2MHz clock rate (depending
on ordering options)
■ 5ms or 10ms Write Time (depending on
ordering options)
■ Status Register
■ Hardware Protection of the Status Register
■ BYTE and PAGE WRITE (up to 32 Byte s)
■ Self-Tim ed P ro g ra m ming Cycle
■ Adjustable Size Read-Only EEPR OM Area
■ Enhanced ESD Protection
■ More than 100,000 or 1 million Erase/Write
Cycles (depending on ordering options)
■ More than 40 Year Data Retention
M95640
M95320
With High Speed Clock
Figure 1. Packages
8
1
PDIP8 (BN)
0.25 mm frame
8
1
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
TSSOP14 (DL)
169 mil width
1/39November 2003
M95640, M95320
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. DIP and SO Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. TSSOP14 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Write Protect (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
CONNECTING TO THE SPI BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. Bus Master and Memory Devices on the SPI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
OPERATING FEATURES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power On Reset: VCC Lock-Out Write Protect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Active Power and Stand-by Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Hold Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Hold Condition Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2. Status Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Protection and Protocol Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Write-Protected Block Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2/39
M95640, M95320
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. Write Enable (WREN) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10. Write Disable (WRDI) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Write Disable (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. Read Status Register (RDSR) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read Status Register (RDSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 12. Write Status Register (WRSR) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Protection Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Address Range Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 13. Read from Memory Array (READ) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 14. Byte Write (WRITE) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Write to Memory Array (WRITE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 15. Page Write (WRITE) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
POWER-UP AND DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power-up State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 8. Operating Conditions (M95xxx). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 9. Operating Conditions (M95xxx-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 10. Operating Conditions (M95xxx-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 11. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 16. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 12. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 13. DC Characteristics (M95xxx, temperature range 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 14. DC Characteristics (M95xxx, temperature range 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 15. DC Characteristics (M95xxx-W, temperature range 6) . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 16. DC Characteristics (M95xxx-W, temperature range 3) . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 17. DC Characteristics (M95xxx-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 18. AC Characteristics (M95xxx, temperature range 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3/39
M95640, M95320
Table 19. AC Characteristics (M95xxx, temperature range 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 20. AC Characteristics (M95xxx-W, temperature range 6) . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 21. AC Characteristics (M95xxx-W, temperature range 3) . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 22. AC Characteristics (M95xxx-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Figure 17. Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1
Figure 18. Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 19. Output Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 20. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . . 33
Table 23. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mecha nical Data. . . . . . . . . . 33
Figure 21. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline. . . . 34
Table 24. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
34
Figure 22. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outlin e . . . . . . . . . . . . . . . . . . . 35
Table 25. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mec hanical Data . . . . . . . . . . . . 35
Figure 23. TSSOP14 - 14 lead Thin Shrink Small Outline, Package Outlin e . . . . . . . . . . . . . . . . . 36
Table 26. TSSOP14 - 14 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . 36
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 27. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 28. How to Identify Current and Forthcoming Products by the Process Identification Letter 37
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 29. Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
4/39
SUMMARY DESCRIPTION
These electrically erasable programmable mem ory (EEPROM) devices are accessed by a high
speed SPI-compatible bus. The memory array is
organized as 8192 x 8 bit (M95640), and 4096 x 8
bit (M95320).
The device is accessed by a simple serial interface
that is SPI-compatible. The bus signa ls are C, D
and Q, as shown in Table 1 and Figure 2.
The device is selected when Chip Select (S
) is taken Low. Communications with the devi ce can be
interrupted using Hold (HOLD
).
Figure 2. Logic Diagram
V
CC
M95640, M95320
Figure 3. DIP and SO Connections
M95xxx
1
SV
2
3
W
4
SS
Note: 1. See page 33 (onwards) for package dimensions, and how
to identify pin-1.
8
7
6
5
AI01790D
CC
HOLDQ
C
DV
W
HOLD
D
Q
Figure 4. TSSOP14 Con nections
C
S
M95xxx
V
SS
AI01789C
Note: 1. See page 33 (onwards) for package dimensions, and how
to identify pin-1.
2. NC = Not Connected
M95xxx
1
2
3
4
5
6
7
14
13
12
11
10
9
8
AI02346C
V
CC
HOLD
NC
NC
NC
DV
S
Q
NC
NC
NC
WC
SS
Table 1. Signal Names
C Serial Clock
D Serial Data Input
Q Serial Data Output
S
W
Write Protect
HOLD
Hold
V
CC
V
SS
Chip Select
Supply Voltage
Ground
5/39
M95640, M95320
SIGNAL DESCRIPTION
During all operations, V
within the specified valid range: V
V
(max).
CC
All of the input and output signals must be he ld
High or Low (according to voltages of V
or VOL, as specified in Tables 13 to 17). These signals are described next.
Serial Data Output (Q). This output signal is
used to transfer data serially out of the device.
Data is shifted out on the falling edge of Serial
Clock (C).
Serial Data Input (D). This input signal is used to
transfer data serially into the device. It receives instructions, addresses, and the data to be written.
Values are latched on the rising edge of Serial
Clock (C).
Serial Clock (C). This input signal provides the
timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are
latched on the rising edge of Serial Clock (C). Data
on Serial Data Output (Q) changes after the falling
edge of Serial Clock (C).
Chip Select (S
). When this input signal is High,
the device is des elected and Serial Data Output
must be held stable and
CC
(min) to
CC
, VOH, V
IH
(Q) is at high impedance. Unless an internal Write
cycle is in progress, the device will be in the Standby mode. Driving Chip Select (S
) Low enables the
device, placing it in the active power mode.
After Power-up, a falling edge on Chip Select (S
IL
is required prior to the start of any instruction.
Hold (HOLD
). The Hold (HOLD) signal is used to
pause any serial communications with the device
without deselecting the device.
During the Hold condition, the Serial Data Output
(Q) is high impedanc e, and Serial D ata Input (D)
and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be se-
lected, wit h C h ip S e lec t (S
Write Protect (W
). The main purpose of this in-
) driven Low.
put signal is to freeze the size of the area of memory that is protected against Write instructions (as
specified by the values in the BP1 and BP0 bits of
the Status Register).
This pin must be driven e ither High or Low, and
must be stable during all write operations.
)
6/39
CONNECTING TO THE SPI BUS
These devices are fully compatible with the SPI
protocol.
All instructions, addresses and input data bytes
are shifted in to the device, most significant bit
first. The Serial Data Input (D) is sampled on the
first rising edge of the Serial Clock (C) after Chip
Selec t ( S
) goes Low.
All output data bytes are shifted out of the device,
most significant bit first. The Serial Data Output
(Q) is latched on the first fa lling edge of the Serial
Clock (C) after the instruction (such as the Read
from Memory Array and Read S tatus Register instructions) have been clocked into the device.
Figure 5 shows three devices, connected to an
MCU, on a SPI bus. Only one device is selected at
a time, so only one de vice drives the Serial Data
Output (Q) line at a time, all the o thers be ing h igh
impedance.
Figure 5. Bus Master and Memory Devices on the SPI Bus
M95640, M95320
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
Bus Master
(ST6, ST7, ST9,
ST10, Others)
CS3 CS2 CS1
Note: 1. The Write Protect (W) a nd Hold (HOLD) s i gnals should be driven, High or Low as appropri ate.
SPI Modes
These devices can be drive n by a microcont roller
with its SPI periphe ral running in ei the r of the two
following modes:
– CPOL=0, CPHA=0
– CPOL=1, CPHA=1
For these two modes, input dat a is latched in on
SDO
SDI
SCK
CQD
SPI Memory
Device
S
CQD
SPI Memory
Device
HOLD
W
S
HOLD
W
is availa ble from t he falling e dge of Se rial Clock
(C).
The difference between the two modes, as shown
in Figure 6, is the clock polarity when the bus master is in Stand-by mode and not transferring data:
– C remains at 0 for (CPOL=0, CPHA=0)
– C remains at 1 for (CPOL=1, CPHA=1)
the rising edge of Serial Clock (C), and output data
CQD
SPI Memory
Device
S
W
AI03746D
HOLD
7/39
M95640, M95320
Figure 6. SPI Mo de s S upported
CPHA
CPOL
0
0
1
1
C
C
D
Q
MSB
MSB
AI01438B
8/39
OPERATING FEATURES
Power-up
When the power supply is turned on, V
from V
During this time, the Chip Select (S
lowed to follow the V
to VCC.
SS
) must be al-
voltage. It must not be al-
CC
lowed to float, but should be connected to V
CC
rises
via
CC
a suitable pull-up resistor.
As a built in safety feature, Chip Select (S
) is edge
sensitive as well as level se nsitive. After Powerup, the device does not become s elected until a
falling edge has first been detected on Chip Select
(S
). This ensures that Chip Sele ct (S) must have
been High, prior to going Low to start the first operation.
Power On Reset: V
Lock-Out Write Protect
CC
In order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included. The internal reset
is held active until V
has reached the POR
CC
threshold value, and all operations are disabled –
the device will not respond to any command. In the
same way, when V
drops from the operating
CC
voltage, below the POR threshold value , all operations are disabled and the device will not respond
to any command.
A stable and valid V
must be applied before ap-
CC
plying any logic signal.
Power-down
At Power-down, the device must be deselected.
Chip Select (S
voltage applied on V
) should be allowed to follow the
.
CC
M95640, M95320
Active Power and Stand-by Power Modes
When Chip Select (S
abled, and in the Active Power mode. The dev ice
consumes I
, as specified in Tables 13 to 17.
CC
When Chip Select (S
abled. If an Erase/Write cycle is not currently in
progress, the device then goes in to the Stand-by
Power mode, and the device consumpt ion drops
to I
CC1
.
Hold Condition
The Hold (HOLD
rial communications with the device without resetting the clocking sequence.
During the Hold condition, the Serial Data Output
(Q) is high impedanc e, and Serial D ata Input (D)
and Serial Clock (C) are Don’t Care.
To enter the Hold condition, the device must be
selected , wit h Ch ip Select (S
Normally, the device is kept selected, for the whole
duration of the Hold condition. Deselecting the device while it is in the Hold condition, has the effect
of resetting the state of the device, and this mechanism can be used if it is required to reset any processes that had been in progress.
The Hold condition starts when the Hold (H OLD
signal is driven Low at the same time as Serial
Clock (C) already being Low (as shown in Figure
7).
The Hold condition ends when the Hold (HOLD
signal is driven High at the same time as Serial
Clock (C) already being Low.
Figure 7 also shows what happens if the rising and
falling edges are not timed to coincide with Serial
Clock (C) being Low.
) is Low, the device is en-
) is High, the device is dis-
) signal is used to pause any se-
) Low.
)
)
Figure 7. Hold Condition Activation
C
HOLD
Hold
Condition
Hold
Condition
AI02029D
9/39
M95640, M95320
Status Register
Figure 8 shows the position of the Status Register
in the control logic of the d evice. The Stat us Register contains a number of status and c ontrol bits
that can be read or set (as appropriate) by specific
instruction s.
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write or Write
Status Register cycle.
WEL bit. Th e Write Enable Latch (WEL ) bit indicates the status of the internal Write Enable Latch.
BP1, BP0 bits. The Block Protect (BP1, BP0) bits
are non-volatile. They define the size of the area to
be software protected against Write instructions.
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W
) signal. The Status Register
Write Disable (SRWD) bit an d Write Protect (W
signal allow the device to be put in the Hardware
Protected mode. In this mode, the non-volatile bits
of the Status Register (SRWD, BP1, BP0) become
read-only bits.
Table 2. Status Register Format
b7 b0
SRWD 0 0 0 BP1 BP0 WEL WIP
Status Register Write Protect
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
Data Protection and Protocol Control
Non-volatile memory devices can be used in environments that are particularly noisy, and within applications that could experience problems if
memory bytes are corrupted. Consequently, the
device features the following data protection
mechanisms:
■ Write and Write Status Register instructions are
checked that they consist of a number of clock
pulses that is a multiple of eight, before they are
accepted for execution.
■ All instructions that modify data must be
preceded by a Write Enable (WREN) instruction
to set the Write Enable Latch (WEL) bit . This bit
is returned to its reset state by the following
events:
– Power-up
– Write Disable (WRDI) instruction completion
– Write Status Register (WRSR) instruction
completion
– Write (WRITE) instruction completion
■ The Block Protect (BP1, BP0) bits allow part of
)
the memory to be configured as read-only. This
is the Software Protected Mode (SPM).
■ The Write Protect (W) signal allows the Block
Protect (BP1, BP0) bits to be protected. This is
the Hardware Protected Mode (HPM).
For any instruction to be accepted, and executed,
Chip Select (S
) must be driven High after the rising
edge of Serial Clock (C) for the last bit of the instruction, and before the next rising edge of Serial
Clock (C).
Two points need to be no ted in the p revious sentence:
– The ‘last bit of the instruction’ can be the eighth
bit of the instruction cod e, or the eig hth bit of a
data byte, dependin g on the instruction (except
for Read Status Register (RDSR) and Read
(READ) instructions).
– The ‘next rising edge of S erial Clock (C)’ might
(or might not) be the next bus transaction for
some other device on the SPI bus.
Table 3. Write-Protected Block Size
Status Register Bits
Protected Block
BP1 BP0 M95640 M95320
0 0 none none none
0 1 Upper quarter 1800h - 1FFFh 0C00h - 0FFFh
1 0 Upper half 1000h - 1FFFh 0800h - 0FFFh
1 1 Whole memory 0000h - 1FFFh 0000h - 0FFFh
10/39
Array Addresses Protected
MEMORY OR GANIZATION
The memory is organized as shown in Figure 8.
Figure 8. Block Diagram
M95640, M95320
HOLD
W
S
C
D
Q
Control Logic
I/O Shift Register
Address Register
and Counter
Y Decoder
High Voltage
Generator
Data
Register
1 Page
Status
Register
Size of the
Read only
EEPROM
area
X Decoder
AI01272C
11/39
M95640, M95320
INSTRUCTIONS
Each instruction starts with a single-byte code, as
summarized in Table 4.
If an invalid instruction is sent (on e not con tained
in Table 4), the device au tomatically deselects itself.
Figure 9. Write Enable (WREN) Sequence
S
0
C
Table 4. Instruction Set
Instruc
tion
WREN Write Enable 0000 0110
WRDI Write Disable 0000 0100
RDSR Read Status Register 0000 0101
WRSR Write Status Register 0000 0001
READ Read from Memory Array 0000 0011
WRITE Write to Memory Array 0000 0010
21 34567
Instruction
Description
Instruction
Format
D
High Impedance
Q
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only
way to do this is to send a Write Enable instruction
to the device.
AI02281E
As shown in Figure 9, to send this instruction to the
device, Chip Select (S
) is driven Low, and the bits
of the instruction byte are shifted in, on Serial Data
Input (D). The device then enters a wait state. It
waits for a the device t o be deselected, by Chip
Selec t ( S
) being driven High.
12/39
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