Automotive 16-Kbit serial SPI bus EEPROM
TSSOP8 (DW)
169 mil width
Features
■ Compatible with SPI bus serial interface
(positive clock SPI modes)
■ Extended operating temperature range:
– Device grade 4: –40 °C to +145 °C
■ Single supply voltage:
– 2.5 V to 5.5 V
■ High speed: 5 MHz
■ Status Register
■ Hardware protection of the Status Register
■ Byte and page write (up to 32 bytes)
■ Self-timed programming cycle
■ Adjustable size read-only EEPROM area
■ Enhanced ESD protection
■ More than 1 million write cycles
■ More than 40-year data retention
■ Package
– RoHS compliant and halogen-free
(ECOPACK2
®
)
M95160-145
with high-speed clock
November 2011 Doc ID 022470 Rev 1 1/35
www.st.com
1
Contents M95160-145
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Chip Select (S
2.5 Hold (HOLD
2.6 Write Protect (W
2.7 V
2.8 V
supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CC
ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SS
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Implementing devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.1 Operating supply voltage V
4.1.2 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.3 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.3 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/35 Doc ID 022470 Rev 1
M95160-145 Contents
6.3.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.5 Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.6 Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7 Delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.1 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
11 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Doc ID 022470 Rev 1 3/35
List of tables M95160-145
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 6. Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 8. Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 9. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 10. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 11. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 12. AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 13. TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 32
Table 14. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 15. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4/35 Doc ID 022470 Rev 1
M95160-145 List of figures
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. TSSOP8-lead package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Hold mode activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9. Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10. Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 11. Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12. Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 13. Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 14. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 15. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 16. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 17. Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 18. TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 32
Doc ID 022470 Rev 1 5/35
Description M95160-145
AI01789C
S
V
CC
M95xxx
HOLD
V
SS
W
Q
C
D
1 Description
The M95160-145 is an EEPROM (Electrically Erasable PROgrammable Memory) accessed
by a high-speed SPI bus.
The memory array is organized as 2048 × 8 bits.
The M95160-145 is the first EEPROM device in a TSSOP package qualified at 145 °C.
The M95160-145 device is designed to be compliant with the very high level of reliability
defined by the Automotive standard AEC-Q100 grade 0.
Figure 1. Logic diagram
Table 1. Signal names
Signal name Function Direction
C Serial Clock Input
D Serial Data input Input
Q Serial Data output Output
S
W
Hold Input
HOLD
V
CC
V
SS
6/35 Doc ID 022470 Rev 1
Chip Select Input
Write Protect Input
Supply voltage
Ground
M95160-145 Description
DV
SS
C
HOLDQ
SV
CC
W
AI01790D
M95xxx
1
2
3
4
8
7
6
5
Figure 2. TSSOP8-lead package connections (top view)
1. See Package mechanical data section for package dimensions, and how to identify pin-1.
Doc ID 022470 Rev 1 7/35
Signal description M95160-145
2 Signal description
During all operations, VCC must be held stable and within the specified valid range:
V
(min) to VCC(max).
CC
All of the input and output signals must be held high or low (according to voltages of V
V
, VIL or VOL, as specified in Ta bl e 1 0 . These signals are described next.
OH
2.1 Serial Data output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
2.2 Serial Data input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be written. Values are latched on the rising edge of Serial Clock
(C).
,
IH
2.3 Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
2.4 Chip Select (S)
When this input signal is high, the device is deselected and Serial Data Output (Q) is at high
impedance. Unless an internal Write cycle is in progress, the device will be in the Standby
Power mode. Driving Chip Select (S
mode.
After Power-up, a falling edge on Chip Select (S
instruction.
2.5 Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
2.6 Write Protect (W)
) low selects the device, placing it in the Active Power
) is required prior to the start of any
The main purpose of this input signal is to freeze the size of the area of memory that is
protected against Write instructions (as specified by the values in the BP1 and BP0 bits of
the Status Register).
This pin must be driven either high or low, and must be stable during all write instructions.
8/35 Doc ID 022470 Rev 1
M95160-145 Signal description
2.7 VCC supply voltage
VCC is the supply voltage.
2.8 VSS ground
VSS is the reference for the VCC supply voltage.
Doc ID 022470 Rev 1 9/35
Implementing devices on the SPI bus M95160-145
3 Implementing devices on the SPI bus
Figure 3 shows an example of three devices, connected to the SPI bus master. Only one
device is selected at a time, so that only the selected device drives the Serial Data output
(Q) line. All the other devices outputs are then in high impedance.
Figure 3. Bus master and memory devices on the SPI bus
6
##
30)INTERFACEWITH
#0/,#0(!
OR
30)BUSMASTER
#3 #3 #3
1. The Write Protect (W) and Hold (HOLD) signals must be driven high or low as appropriate.
A pull-up resistor connected on each S input (represented in Figure 3) ensures that each
device is not selected if the bus master leaves the S
3.1 SPI modes
3$/
3$)
3#+
6
##
222
30)MEMORY
DEVICE
3
7
(/,$
#1$#1$
30)MEMORY
3
DEVICE
7
6
(/,$
##
#1$
30)MEMORY
line in the high impedance state.
DEVICE
3
7
6
##
(/,$
6
33
-36
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
● CPOL=0, CPHA=0
● CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 4, is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
● C remains at 0 for (CPOL=0, CPHA=0)
● C remains at 1 for (CPOL=1, CPHA=1)
10/35 Doc ID 022470 Rev 1
M95160-145 Implementing devices on the SPI bus
AI01438B
C
MSB
CPHA
D
0
1
CPOL
0
1
Q
C
MSB
Figure 4. SPI modes supported
Doc ID 022470 Rev 1 11/35
Operating features M95160-145
4 Operating features
4.1 Supply voltage (VCC)
4.1.1 Operating supply voltage V
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [V
(min), VCC(max)] range must be applied (see Ta bl e 8 ). This voltage
CC
must remain stable and valid until the end of the transmission of the instruction and, for a
Write instruction, until the completion of the internal write cycle (t
In order to secure a stable DC supply voltage, it is recommended to decouple the V
with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the V
package pins.
4.1.2 Device reset
In order to prevent inadvertent write operations during power-up, a power on reset (POR)
circuit is included. At power-up, the device does not respond to any instruction until V
reaches the internal reset threshold voltage (this threshold is lower than the minimum V
operating voltage defined in Ta b le 8 ).
When V
● in Standby Power mode
● deselected (note that, to be executed, an instruction must be preceded by a falling
● Status Register value:
passes over the POR threshold, the device is reset and in the following state:
CC
edge on Chip Select (S
))
– the Write Enable Latch (WEL) is reset to 0
– Write In Progress (WIP) is reset to 0
– The SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits)
CC
).
W
line
CC
CC
CC
CC/VSS
When V
passes over the POR threshold, the device is reset and enters the Standby
CC
Power mode. The device must not be accessed until V
voltage within the specified [V
(min), VCC(max)] range defined in Ta b le 8 .
CC
4.1.3 Power-up conditions
When the power supply is turned on, VCC rises continuously from VSS to VCC. During this
time, the Chip Select (S
therefore recommended to connect the S
Figure 3).
In addition, the Chip Select (S
sensitive as well as level-sensitive: after power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S
(S
) must have been high, prior to going low to start the first operation.
The V
voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
CC
defined in Ta bl e 8 and the rise time must not vary faster than 1 V/µs.
12/35 Doc ID 022470 Rev 1
) line is not allowed to float but should follow the VCC voltage, it is
line to VCC via a suitable pull-up resistor (see
) input offers a built-in safety feature, as the S input is edge-
reaches a valid and stable VCC
CC
). This ensures that Chip Select
M95160-145 Operating features
(/,$
#
(OLD
CONDITION
#
N
(OLD
CONDITION
-36
4.1.4 Power-down
During power-down (continuous decrease of VCC below the minimum VCC operating voltage
defined in Ta bl e 8 ), the device must be:
● deselected (Chip Select S should be allowed to follow the voltage applied on V
● in Standby Power mode (there should not be any internal write cycle in progress).
CC
)
4.2 Active Power and Standby Power modes
When Chip Select (S) is low, the device is selected, and in the Active Power mode. The
device consumes I
When Chip Select (S
, as specified in Ta bl e 1 0 .
CC
) is high, the device is deselected. If a Write cycle is not currently in
progress, the device then goes into the Standby Power mode, and the device consumption
drops to I
CC1
.
4.3 Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
The Hold mode starts when the Hold (HOLD) signal is driven low and the Serial Clock (C) is
low (as shown in Figure 5). During the Hold mode, the Serial Data output (Q) is high
impedance, and Serial Data input (D) and Serial Clock (C) are Don’t Care. The Hold mode
ends when the Hold (HOLD) signal is driven high and the Serial Clock (C) is or becomes
low.
Figure 5. Hold mode activation
Deselecting the device while it is in Hold mode resets the paused communication.
4.4 Status Register
Figure 6. shows the position of the Status Register in the control logic of the device. The
Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a
detailed description of the Status Register bits
ONDITIO
Doc ID 022470 Rev 1 13/35
Operating features M95160-145
4.5 Data protection and protocol control
Non-volatile memory devices can be used in environments that are particularly noisy, and
within applications that could experience problems if memory bytes are corrupted.
Consequently, the device features the following data protection mechanisms:
● Write and Write Status Register instructions are checked that they consist of a number
of clock pulses that is a multiple of eight, before they are accepted for execution.
● All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–Power-up
– Write Disable (WRDI) instruction completion
– Write Status Register (WRSR) instruction completion
– Write (WRITE) instruction completion
● The Block Protect (BP1, BP0) bits in the Status Register allow part of the memory to be
configured as read-only.
● The Write Protect (W) signal allows the Block Protect (BP1, BP0) bits of the Status
Register to be protected.
For any instruction to be accepted, and executed, Chip Select (S
) must be driven high after
the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising
edge of Serial Clock (C).
Two points need to be noted in the previous sentence:
● The “last bit of the instruction” can be the eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction (except for Read Status Register
(RDSR) and Read (READ) instructions).
● The “next rising edge of Serial Clock (C)” might (or might not) be the next bus
transaction for some other device on the SPI bus.
Table 2. Write-protected block size
Status Register bits
Protected block Protected array addresses
BP1 BP0
0 0 none none
0 1 Upper quarter 0600h - 07FFh
1 0 Upper half 0400h - 07FFh
1 1 Whole memory 0000h - 07FFh
14/35 Doc ID 022470 Rev 1
M95160-145 Memory organization
AI01272d
HOLD
S
W
Control logic
High voltage
generator
I/O shift register
Address register
and counter
Data
register
1 page
X decoder
Y decoder
C
D
Q
Size of the
read-only
EEPROM
area
Status
Register
5 Memory organization
The memory is organized as shown in Figure 6.
Figure 6. Block diagram
Doc ID 022470 Rev 1 15/35
Instructions M95160-145
C
D
AI02281E
S
Q
21 34567
High Impedance
0
Instruction
6 Instructions
Each instruction starts with a single-byte code, as summarized in Table 3.
If an invalid instruction is sent (one not contained in Table 3.), the device automatically
deselects itself.
Table 3. Instruction set
Instruction Description Instruction format
WREN Write Enable 0000 0110
WRDI Write Disable 0000 0100
RDSR Read Status Register 0000 0101
WRSR Write Status Register 0000 0001
READ Read from Memory Array 0000 0011
WRITE Write to Memory Array 0000 0010
6.1 Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in Figure 7., to send this instruction to the device, Chip Select (S
) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then
enters a wait state. It waits for the device to be deselected, by Chip Select (S
) being driven
high.
Figure 7. Write Enable (WREN) sequence
16/35 Doc ID 022470 Rev 1
M95160-145 Instructions
C
D
AI03750D
S
Q
21 34567
High Impedance
0
Instruction
6.2 Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in Figure 8., to send this instruction to the device, Chip Select (S
) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S
) being driven high.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
● Power-up
● WRDI instruction execution
● WRSR instruction completion
● WRITE instruction completion.
Figure 8. Write Disable (WRDI) sequence
Doc ID 022470 Rev 1 17/35
Instructions M95160-145
6.3 Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Write or Write Status Register cycle
is in progress. When one of these cycles is in progress, it is recommended to check the
Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible
to read the Status Register continuously, as shown in Figure 9.
The status and control bits of the Status Register are as follows:
6.3.1 WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.
6.3.2 WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write or Write Status Register instruction is accepted.
6.3.3 BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to
1, the relevant memory area (as defined in Table 4.) becomes protected against Write
(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set.
6.3.4 SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W
signal allow the device to be put in the Hardware Protected mode (when the Status Register
Write Disable (SRWD) bit is set to 1, and Write Protect (W
non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the
Write Status Register (WRSR) instruction is no longer accepted for execution.
Table 4. Status Register format
b7 b0
SRWD 0 0 0 BP1 BP0 WEL WIP
Status register write protect
) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
) is driven low). In this mode, the
Block protect bits
Write enable latch bit
Write in progress bit
18/35 Doc ID 022470 Rev 1
M95160-145 Instructions
C
D
S
21 3456789101112131415
Instruction
0
AI02031E
Q
7 6543210
Status Register Out
High Impedance
MSB
7 6543210
Status Register Out
MSB
7
Figure 9. Read Status Register (RDSR) sequence
Doc ID 022470 Rev 1 19/35
Instructions M95160-145
6.4 Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must have been
previously executed.
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S
) low,
followed by the instruction code, the data byte on Serial Data input (D) and the Chip Select
(S
) driven high. Chip Select (S) must be driven high after the rising edge of Serial Clock (C)
that latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock
(C). Otherwise, the Write Status Register (WRSR) instruction is not executed.
Driving the Chip Select (S
timed write cycle that takes t
) signal high at a byte boundary of the input data triggers the self-
to complete (as specified in Ta bl e 1 2).
W
The instruction sequence is shown in Figure 10.
While the Write Status Register cycle is in progress, the Status Register may still be read to
check the value of the Write In Progress (WIP) bit: the WIP bit is 1 during the self-timed write
cycle t
reset at the end of the write cycle t
, and is 0 when the write cycle is complete. The WEL bit (Write Enable Latch) is also
W
.
W
The Write Status Register (WRSR) instruction allows the user to change the values of the
BP1, BP0 bits and the SRWD bit:
● The Block Protect (BP1, BP0) bits define the size of the area that is to be treated as
read only, as defined in Tab le 5 .
● The SRWD bit (Status Register Write Disable bit), in accordance with the signal read
on the Write Protect pin (W
), allows the user to set or reset the write protection mode of
the Status Register itself. When in Write-protected mode, the Write Status Register
(WRSR) instruction is not executed.
The contents of the SRWD and BP1, BP0 bits are updated after the completion of the
WRSR instruction, including the t
Write cycle.
W
The Write Status Register (WRSR) instruction has no effect on bits b6, b5, b4, b1, b0 of the
Status Register. Bits b6, b5, b4 are always read as 0.
Table 5. Protection modes
W
SRWD
signal
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 4.
20/35 Doc ID 022470 Rev 1
bit
10
00
11
01
Mode
Software-
protected
(SPM)
Hardware-
protected
(HPM)
Write protection of the
Status Register
Status Register is
Writable (if the WREN
instruction has set the
WEL bit)
The values in the BP1
and BP0 bits can be
changed
Status Register is
Hardware write protected
The values in the BP1
and BP0 bits cannot be
changed
Memory content
Protected area
Write-protected
Write-protected
(1)
Unprotected area
Ready to accept
Write instructions
Ready to accept
Write instructions
(1)
M95160-145 Instructions
The protection features of the device are summarized in Table 2.
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of whether Write Protect (W
) is driven high or low.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two
cases need to be considered, depending on the state of Write Protect (W
● If Write Protect (W) is driven high, it is possible to write to the Status Register provided
):
that the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction.
● If Write Protect (W) is driven low, it is not possible to write to the Status Register even if
the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN)
instruction. (Attempts to write to the Status Register are rejected, and are not accepted
for execution). As a consequence, all the data bytes in the memory area that are
software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register,
are also hardware protected against data modification.
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be
entered:
● by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W)
low
● or by driving Write Protect (W) low after setting the Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write
Protect (W
If Write Protect (W
) high.
) is permanently tied high, the Hardware Protected Mode (HPM) can
never be activated, and only the Software Protected Mode (SPM), using the Block Protect
(BP1, BP0) bits of the Status Register, can be used.
Table 6. Address range bits
Device M95160-145
Address bits A10-A0
1. b15 to b11 are Don’t Care.
(1)
Doc ID 022470 Rev 1 21/35
Instructions M95160-145
C
D
AI02282D
S
Q
21 3456789101112131415
High Impedance
Instruction Status
Register In
0
765432 0
1
MSB
Figure 10. Write Status Register (WRSR) sequence
22/35 Doc ID 022470 Rev 1
M95160-145 Instructions
C
D
AI01793D
S
Q
15
21 345678910 2021222324252627
1413 3210
28 29 30
76543 1 7
0
High Impedance
Data Out 1
Instruction 16-Bit Address
0
MSB
MSB
2
31
Data Out 2
6.5 Read from Memory Array (READ)
As shown in Figure 11., to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data
Input (D). The address is loaded into an internal address register, and the byte of data at
that address is shifted out, on Serial Data Output (Q).
If Chip Select (S
) continues to be driven low, the internal address register is automatically
incremented, and the byte of data at the new address is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the
Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a
single READ instruction.
The Read cycle is terminated by driving Chip Select (S
Select (S
) signal can occur at any time during the cycle.
The first byte addressed can be any byte within any page.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
Figure 11. Read from Memory Array (READ) sequence
) high. The rising edge of the Chip
1. Depending on the memory size, as shown in Table 6., the most significant address bits are Don’t Care.
Doc ID 022470 Rev 1 23/35
Instructions M95160-145
C
D
AI01795D
S
Q
15
21 345678910 2021222324252627
1413 3210
28 29 30
High Impedance
Instruction 16-Bit Address
0
765432 0
1
Data Byte
31
6.6 Write to Memory Array (WRITE)
As shown in Figure 12., to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte, address byte, and at least one data byte are then shifted
in, on Serial Data Input (D).
The instruction is terminated by driving Chip Select (S
data. The self-timed Write cycle, triggered by the Chip Select (S
period t
(as specified in Ta bl e 1 2), at the end of which the Write in Progress (WIP) bit is
W
) high at a byte boundary of the input
) rising edge, continues for a
reset to 0.
In the case of Figure 12., Chip Select (S
) is driven high after the eighth bit of the data byte
has been latched in, indicating that the instruction is being used to write a single byte. If,
though, Chip Select (S
) continues to be driven low, as shown in Figure 13., the next byte of
input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If the number of data bytes sent to the device exceeds the page
boundary, the internal address counter rolls over to the beginning of the page, and the
previous data there are overwritten with the incoming data. (The page size of these devices
is 32 bytes).
The instruction is not accepted, and is not executed, under the following conditions:
● if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before)
● if a Write cycle is already in progress
● if the device has not been deselected, by Chip Select (S) being driven high, at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in)
● if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits.
Figure 12. Byte Write (WRITE) sequence
1. Depending on the memory size, as shown in Table 6., the most significant address bits are Don’t Care.
24/35 Doc ID 022470 Rev 1
M95160-145 Instructions
C
D
AI01796D
S
3433 35 36 37 38 39 40 41 42 44 45 46 4732
C
D
S
15
21 345678910 2021222324252627
1413 3210
28 29 30
Instruction 16-Bit Address
0
765432 0
1
Data Byte 1
31
43
765432 0
1
Data Byte 2
765432 0
1
Data Byte 3
65432 0
1
Data Byte N
Figure 13. Page Write (WRITE) sequence
1. Depending on the memory size, as shown in Table 6., the most significant address bits are Don’t Care.
Doc ID 022470 Rev 1 25/35
Delivery state M95160-145
7 Delivery state
7.1 Initial delivery state
The device is delivered with the memory array set at all 1s (FFh). The Status Register Write
Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.
8 Absolute maximum ratings
Stressing the device outside the ratings listed in Ta bl e 7 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 7. Absolute maximum ratings
Symbol Parameter Min. Max. Unit
T
STG
T
AMR
T
LEAD
V
O
V
I
OL
I
OH
V
CC
V
ESD
1. Compliant with JEDEC Std J-STD-020 (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU
2. Positive and negative pulses applied on pin pairs, in accordance with AEC-Q100-002 (compliant with
JEDEC Std JESD22-A114, C1=100 pF, R1=1500 Ω, R2=500 Ω)
Storage temperature –65 150 °C
Ambient operating temperature –40 150 °C
Lead temperature during soldering See note
Voltage on Q pin –0.50 VCC+0.6 V
Input voltage –0.50 6.5 V
I
DC output current (Q = 0) 5 mA
DC output current (Q = 1) –5 mA
Supply voltage –0.50 6.5 V
Electrostatic pulse (Human Body Model)
(2)
(1)
4000 V
°C
26/35 Doc ID 022470 Rev 1
M95160-145 DC and AC parameters
!)#
6
##
6
##
6
##
6
##
)NPUTANDOUTPUT
TIMINGREFERENCELEVELS
)NPUTVOLTAGELEVELS
9 DC and AC parameters
This section summarizes the operating and measurement conditions, and the dc and ac
characteristics of the device. The parameters in the dc and ac characteristic tables that
follow are derived from tests performed under the measurement conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 8. Operating conditions
Symbol Parameter Min. Max. Unit
V
T
Table 9. AC measurement conditions
Supply voltage 2.5 5.5 V
CC
Ambient operating temperature (device grade 4) –40 145 °C
A
Symbol Parameter Min. Typ. Max. Unit
C
Load capacitance 30 or 100 pF
L
Input rise and fall times 50 ns
Input pulse voltages 0.2V
Input and output
1. Output Hi-Z is defined as the point where data out is no longer driven.
(1)
timing reference voltages
to 0.8V
CC
0.3VCC to 0.7V
CC
CC
Figure 14. AC measurement I/O waveform
V
V
Table 10. Capacitance
Symbol Parameter Test condition Min. Max. Unit
C
OUT
C
IN
1. Sampled only, not 100% tested, at T
(1)
Output capacitance (Q) V
= 0 V 8 pF
OUT
Input capacitance (D) VIN = 0 V 8 pF
Input capacitance (other pins) V
= 25 °C and a frequency of 5 MHz.
A
= 0 V 6 pF
IN
Doc ID 022470 Rev 1 27/35
DC and AC parameters M95160-145
Table 11. DC characteristics
Test conditions (in addition to those
Symbol Parameter
Input leakage
I
LI
current
I
I
I
CC1
V
V
V
V
1. Preliminary data.
Output leakage
LO
current
Supply current
CC
Supply current
(Standby)
Input low voltage –0.45 0.3 V
IL
Input high voltage 0.7 V
IH
Output low voltage IOL = 1.5 mA, VCC = 2.5 V 0.4 V
OL
Output high voltage IOH = –0.4 mA, VCC = 2.5 V 0.8 V
OH
V
IN
S
= VCC, V
C=0.1V
VCC= 2.5 V, Q = open
= VCC, V
S
S
= VCC, V
(1)
specified in Table 8, Ta ble 9 and
Tabl e 1 0 )
= VSS or V
CC
= VSS or V
OUT
/0.9VCC at 5 MHz,
CC
= 2.5 V, V
CC
= 5.5 V, V
CC
CC
= VSS or V
IN
= VSS or V
IN
Min. Max. Unit
CC
CC
CCVCC
CC
± 2 µA
± 2 µA
2mA
10 µA
10 µA
V
CC
+1 V
V
28/35 Doc ID 022470 Rev 1
M95160-145 DC and AC parameters
Table 12. AC characteristics
Test conditions specified in Table 8, Table 9 and Tabl e 1 0
Symbol Alt. Parameter Min. Max. Unit
f
C
t
SLCH
t
SHCH
t
SHSL
t
CHSH
t
CHSL
(1)
t
CH
(1)
t
CL
(2)
t
CLCH
(2)
t
CHCL
t
DVC H
t
CHDX
t
HHCH
t
HLCH
t
CLHL
t
CLHH
(2)
t
SHQZ
(3)
t
CLQV
t
CLQX
(2)
t
QLQH
(2)
t
QHQL
t
HHQV
(2)
t
HLQZ
t
W
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max). See also Note 3.
2. Value guaranteed by characterization, not 100% tested in production.
3. t
must be compatible with tCL (clock low time): if the SPI bus master offers a Read setup time tSU =
CLQV
0ns, tCL can be equal to (or greater than) t
t
CLQV+tSU
f
t
CSS1
t
CSS2
t
Clock frequency D.C. 5 MHz
SCK
S active setup time 60 ns
S not active setup time 60 ns
t
S deselect time 90 ns
CS
S active hold time 60 ns
CSH
S not active hold time 60 ns
t
t
t
Clock high time 75 ns
CLH
Clock low time 75 ns
CLL
t
Clock rise time 1 µs
RC
t
Clock fall time 1 µs
FC
Data in setup time 20 ns
DSU
t
Data in hold time 20 ns
DH
Clock low hold time after HOLD not active 60 ns
Clock low hold time after HOLD active 60 ns
Clock low setup time before HOLD active 0 ns
Clock low setup time before HOLD not active 0 ns
t
Output disable time 80 ns
DIS
Clock low to output valid (CL = 30 pF) 55 ns
t
V
Clock low to output valid (C
t
Output hold time 0 ns
HO
t
Output rise time 80 ns
RO
t
Output fall time 80 ns
FO
t
HOLD high to output valid 80 ns
LZ
t
HOLD low to output high-Z 80 ns
HZ
t
Write time 5 ms
WC
.
CLQV
= 100 pF) 80 ns
L
; in all other cases, tCL must be equal to (or greater than)
Doc ID 022470 Rev 1 29/35
DC and AC parameters M95160-145
C
D
AI01447d
S
MSB IN
Q
tDVCH
High impedance
LSB IN
tSLCH
tCHDX
tCLCH
tSHCH
tSHSL
tCHSHtCHSL
tCH
tCL
tCHCL
C
Q
AI01448c
S
HOLD
tCLHL
tHLCH
tHHCH
tCLHH
tHHQVtHLQZ
Figure 15. Serial input timing
Figure 16. Hold timing
30/35 Doc ID 022470 Rev 1
M95160-145 DC and AC parameters
C
Q
AI01449f
S
D
ADDR
LSB IN
tSHQZ
tCH
tCL
tQLQH
tQHQL
tCHCL
tCLQX
tCLQV
tSHSL
tCLCH
Figure 17. Serial output timing
Doc ID 022470 Rev 1 31/35
Package mechanical data M95160-145
TSSOP8AM
1
8
CP
c
L
EE1
D
A2A
α
eb
4
5
A1
L1
10 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
Figure 18. TSSOP8 – 8-lead thin shrink small outline, package outline
1. Drawing is not to scale.
Table 13. TSSOP8 – 8-lead thin shrink small outline, package mechanical data
millimeters inches
Symbol
Typ Min Max Typ Min Max
(1)
A 1.2 0.0472
A1 0.05 0.15 0.002 0.0059
A2 1 0.8 1.05 0.0394 0.0315 0.0413
b 0.19 0.3 0.0075 0.0118
c 0.09 0.2 0.0035 0.0079
CP 0.1 0.0039
D 3 2.9 3.1 0.1181 0.1142 0.122
e 0.65 - - 0.0256 - -
E 6.4 6.2 6.6 0.252 0.2441 0.2598
E1 4.4 4.3 4.5 0.1732 0.1693 0.1772
L 0.6 0.45 0.75 0.0236 0.0177 0.0295
L1 1 0.0394
α 0° 8° 0° 8°
N (number of leads) 8 8
1. Values in inches are converted from mm and rounded to 4 decimal digits.
32/35 Doc ID 022470 Rev 1
M95160-145 Part numbering
11 Part numbering
Table 14. Ordering information scheme
Example: M95160 – W DW 4 T P /SC
Device type
M95 = SPI serial access EEPROM
Device function
160 = 16 Kbit (2048 × 8)
Operating voltage
W = V
Package
DW = TSSOP8
= 2.5 to 5.5 V
CC
Device grade
4 = Device tested with high reliability certified flow
(1)
.
Automotive temperature range (–40 to 145 °C)
Option
blank = Standard packing
T = Tape and reel packing
Plating technology
G or P = ECOPACK2
®
(RoHS compliant and halogen-free)
Process
/SC = F6SP36%
1. The high reliability certified flow (HRCF) is described in quality note QNEE9801. Please ask your nearest
ST sales office for a copy.
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
Doc ID 022470 Rev 1 33/35
Revision history M95160-145
12 Revision history
Table 15. Document revision history
Date Revision Changes
28-Nov-2011 1 Initial release.
34/35 Doc ID 022470 Rev 1
M95160-145
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