ST M950x0, M950x0-W, M950x0-R User Manual
4 Kbit, 2 Kbit and 1 Kbit serial SPI bus EEPROM
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
UFDFPN8 (MB or MC)
2 × 3 mm
Features
■ Compatible with SPI bus serial interface
(Positive clock SPI modes)
■ Single supply voltage:
– 4.5 V to 5.5 V for M950x0
– 2.5 V to 5.5 V for M950x0-W
– 1.8 V to 5.5 V for M950x0-R
■ High speed
– 10 MHz Clock rate, 5 ms write time
■ Status Register
■ Byte and Page Write (up to 16 bytes)
■ Self-timed programming cycle
■ Adjustable size read-only EEPROM area
■ Enhanced ESD protection
■ More than 1 Million write cycles
■ More than 40-year data retention
■ Packages
– RoHS-compliant and Halogen-free
(ECOPACK2
Table 1. Device summary
®
)
M950x0
M950x0-W M950x0-R
with high-speed clock
Reference Part number
M95040
M95040
M95020
M95010
M95040-W
M95040-R
M95020
M95020-W
M95020-R
M95010
M95010-W
M95010-R
February 2012 Doc ID 6512 Rev 10 1/44
www.st.com
1
Contents M950x0 M950x0-W M950x0-R
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Chip Select (S
2.5 Hold (HOLD
2.6 Write Protect (W
2.7 V
ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SS
2.8 Supply voltage (V
2.9 Supply voltage (V
2.9.1 Operating supply voltage V
2.9.2 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.9.3 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.9.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CC
CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.3 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/44 Doc ID 6512 Rev 10
M950x0 M950x0-W M950x0-R Contents
6.3.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.5 Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.6 Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7 Power-up and delivery states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.2 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
11 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Doc ID 6512 Rev 10 3/44
List of tables M950x0 M950x0-W M950x0-R
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 6. Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 8. Operating conditions (M950x0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 9. Operating conditions (M950x0-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 10. Operating conditions (M950x0-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 11. AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 12. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 13. DC characteristics (M950x0, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 14. DC characteristics (M950x0-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 15. DC characteristics (M950x0-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 16. DC characteristics (M950x0-R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 17. AC characteristics (M950x0, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 18. AC characteristics (M950x0-W, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 19. AC characteristics (M950x0-W, device grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 20. AC characteristics (M950x0-R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 21. SO8N — 8-lead plastic small outline, 150 mils body width, package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 22. TSSOP8 — 8-lead thin shrink small outline, package mechanical data . . . . . . . . . . . . . . . 38
Table 23. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 × 3mm, data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 24. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 25. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4/44 Doc ID 6512 Rev 10
M950x0 M950x0-W M950x0-R List of figures
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9. Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10. Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 12. Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13. Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14. AC test measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 15. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 16. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 17. Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 18. SO8N — 8-lead plastic small outline 150 mils body width, package outline. . . . . . . . . . . . 37
Figure 19. TSSOP8 — 8-lead thin shrink small outline, package outline. . . . . . . . . . . . . . . . . . . . . . . 38
Figure 20. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 × 3mm, outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Doc ID 6512 Rev 10 5/44
Description M950x0 M950x0-W M950x0-R
AI01789C
S
V
CC
M95xxx
HOLD
V
SS
W
Q
C
D
DV
SS
C
HOLDQ
SV
CC
W
AI01790D
M95xxx
1
2
3
4
8
7
6
5
1 Description
The M95040 is a 4 Kbit (512 x 8) electrically erasable programmable memory (EEPROM),
accessed by a high-speed SPI-compatible bus. The other members of the family (M95020
and M95010) are identical, though proportionally smaller (2 and 1 Kbit, respectively).
Each device is accessed by a simple serial interface that is SPI-compatible. The bus signals
are C, D and Q.
The device is selected when Chip Select (S
can be interrupted using Hold (HOLD
(W
).
). WRITE instructions are disabled by Write Protect
Figure 1. Logic diagram
Figure 2. 8-pin package connections
) is taken low. Communications with the device
1. See Section 10: Package mechanical data for package dimensions, and how to identify pin-1.
6/44 Doc ID 6512 Rev 10
M950x0 M950x0-W M950x0-R Description
Table 2. Signal names
Signal name Function
C Serial Clock
D Serial Data input
Q Serial Data output
S Chip Select
Write Protect
W
Hold
HOLD
V
CC
V
SS
Supply voltage
Ground
Doc ID 6512 Rev 10 7/44
Signal description M950x0 M950x0-W M950x0-R
2 Signal description
During all operations, VCC must be held stable and within the specified valid range:
V
(min) to VCC(max).
CC
All of the input and output signals can be held high or low (according to voltages of V
V
or VOL, as specified in Table 13: DC characteristics (M950x0, device grade 3) to
IL
Table 16: DC characteristics (M950x0-R, device grade 6)). These signals are described
next.
2.1 Serial Data output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
2.2 Serial Data input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be written. Values are latched on the rising edge of Serial Clock
(C).
, VOH,
IH
2.3 Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
2.4 Chip Select (S)
When this input signal is high, the device is deselected and Serial Data Output (Q) is at high
impedance. Unless an internal Write cycle is in progress, the device will be in the Standby
Power mode. Driving Chip Select (S
mode.
After Power-up, a falling edge on Chip Select (S
instruction.
2.5 Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S
) low selects the device, placing it in the Active Power
) is required prior to the start of any
) driven low.
8/44 Doc ID 6512 Rev 10
M950x0 M950x0-W M950x0-R Signal description
2.6 Write Protect (W)
This input signal is used to control whether the memory is write protected. When Write
Protect (W
enabled. Write Protect (W
) is held low, writes to the memory are disabled, but other operations remain
) must either be driven high or low, but must not be left floating.
2.7 VSS ground
VSS is the reference for the VCC supply voltage.
2.8 Supply voltage (VCC)
2.9 Supply voltage (V
CC
)
2.9.1 Operating supply voltage V
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [V
(min), VCC(max)] range must be applied (see Table 8: Operating
CC
conditions (M950x0), Table 9: Operating conditions (M950x0-W) and Table 10: Operating
conditions (M950x0-R)). This voltage must remain stable and valid until the end of the
transmission of the instruction and, for a Write instruction, until the completion of the internal
write cycle (t
decouple the V
close to the V
). In order to secure a stable DC supply voltage, it is recommended to
W
line with a suitable capacitor (usually of the order of 10 nF to 100 nF)
CC
CC/VSS
package pins.
2.9.2 Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included. At power-up, the device does not respond to any instruction until V
reaches the internal reset threshold voltage (this threshold is defined in Table 8: Operating
conditions (M950x0), Table 9: Operating conditions (M950x0-W) and Table 10: Operating
conditions (M950x0-R) as V
When V
● in Standby Power mode
● deselected (note that, to be executed, an instruction must be preceded by a falling
passes over the POR threshold, the device is reset and is in the following state:
CC
edge on Chip Select (S
● Status register value:
– the Write Enable Latch (WEL) is reset to 0
– Write In Progress (WIP) is reset to 0
– The SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits)
RES
))
).
CC
CC
When V
Power mode. The device must not be accessed until V
voltage within the specified [V
passes over the POR threshold, the device is reset and enters the Standby
CC
(min), VCC(max)] range defined in Table 8: Operating
CC
reaches a valid and stable VCC
CC
conditions (M950x0), Table 9: Operating conditions (M950x0-W) and Table 10: Operating
conditions (M950x0-R).
Doc ID 6512 Rev 10 9/44
Signal description M950x0 M950x0-W M950x0-R
2.9.3 Power-up conditions
When the power supply is turned on, VCC rises continuously from VSS to VCC. During this
time, the Chip Select (S
therefore recommended to connect the S
Figure 3: Bus master and memory devices on the SPI bus).
) line is not allowed to float but should follow the VCC voltage. It is
line to VCC via a suitable pull-up resistor (see
In addition, the Chip Select (S
sensitive as well as level sensitive: after power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S
(S
) must have been high, prior to going low to start the first operation.
The V
voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
CC
defined in Table 8: Operating conditions (M950x0), Table 9: Operating conditions (M950x0-
W) and Table 10: Operating conditions (M950x0-R) and the rise time must not vary faster
than 1 V/µs.
2.9.4 Power-down
During power-down (continuous decrease in the VCC supply voltage below the minimum
V
operating voltage defined in Table 8: Operating conditions (M950x0), Ta b le 9 :
CC
Operating conditions (M950x0-W) and Table 10: Operating conditions (M950x0-R)), the
device must be:
● deselected (Chip Select S should be allowed to follow the voltage applied on V
● in Standby Power mode (there should not be any internal write cycle in progress).
) input offers a built-in safety feature, as the S input is edge
). This ensures that Chip Select
)
CC
10/44 Doc ID 6512 Rev 10
M950x0 M950x0-W M950x0-R Connecting to the SPI bus
AI12304b
Bus master
SPI memory
device
SDO
SDI
SCK
CQD
S
SPI memory
device
CQD
S
SPI mmory
device
CQD
S
CS3 CS2 CS1
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
W
HOLD
W
HOLD
W
HOLD
RRR
V
CC
V
CC
V
CC
V
CC
V
SS
V
SS
V
SS
V
SS
R
3 Connecting to the SPI bus
The device is fully compatible with the SPI protocol.
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction
(such as the Read from Memory Array and Read Status Register instructions) have been
clocked into the device.
Figure 3: Bus master and memory devices on the SPI bus shows an example of three
memory devices connected to an MCU, on an SPI bus. Only one memory device is selected
at a time, so only one memory device drives the Serial Data output (Q) line at a time, the
other memory devices are high impedance.
The pull-up resistor R (represented in Figure 3: Bus master and memory devices on the SPI
bus) ensures that a device is not selected if the bus master leaves the S
impedance state.
In applications where the bus master might enter a state where all SPI bus inputs/outputs
would be in high impedance at the same time (for example, if the bus master is reset during
the transmission of an Instruction), the clock line (C) must be connected to an external pull-
down resistor so that, if all inputs/outputs become high impedance, the C line is pulled low
(while the S
line is pulled high): this ensures that S and C do not become high at the same
time, and so, that the t
) goes low.
requirement is met. The typical value of R is 100 kΩ.
SHCH
line in the high
Figure 3. Bus master and memory devices on the SPI bus
1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.
Doc ID 6512 Rev 10 11/44
Connecting to the SPI bus M950x0 M950x0-W M950x0-R
AI01438B
C
MSB
CPHA
D
0
1
CPOL
0
1
Q
C
MSB
3.1 SPI modes
The device can be driven by a microcontroller with its SPI peripheral running in either of the
two following modes:
● CPOL=0, CPHA=0
● CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 4: SPI modes supported, is the
clock polarity when the bus master is in Stand-by mode and not transferring data:
● C remains at 0 for (CPOL=0, CPHA=0)
● C remains at 1 for (CPOL=1, CPHA=1)
Figure 4. SPI modes supported
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M950x0 M950x0-W M950x0-R Operating features
AI02029D
HOLD
C
Hold
Condition
Hold
Condition
4 Operating features
4.1 Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To enter the Hold condition, the device must be selected, with Chip Select (S
) low.
Normally, the device is kept selected, for the whole duration of the Hold condition.
Deselecting the device while it is in the Hold condition has the effect of resetting the state of
the device, and this mechanism can be used if it is required to reset any processes that had
been in progress.
The Hold condition starts when the Hold (HOLD
) signal is driven low at the same time as
Serial Clock (C) already being low (as shown in Figure 5: Hold condition activation).
The Hold condition ends when the Hold (HOLD
) signal is driven high at the same time as
Serial Clock (C) already being low.
Figure 5: Hold condition activation also shows what happens if the rising and falling edges
are not timed to coincide with Serial Clock (C) being low.
Figure 5. Hold condition activation
4.2 Status register
Figure 6: Block diagram shows the position of the Status register in the control logic of the
device. This register contains a number of control bits and status bits, as shown in Ta bl e 5 :
Status register format. For a detailed description of the Status register bits, see Section 6.3:
Read Status Register (RDSR).
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Operating features M950x0 M950x0-W M950x0-R
4.3 Data protection and protocol control
To help protect the device from data corruption in noisy or poorly controlled environments, a
number of safety features have been built in to the device. The main security measures can
be summarized as follows:
● The WEL bit is reset at power-up.
● Chip Select (S) must rise after the eighth clock count (or multiple thereof) in order to
start a non-volatile Write cycle (in the memory array or in the Status register).
● Accesses to the memory array are ignored during the non-volatile programming cycle,
and the programming cycle continues unaffected.
● Invalid Chip Select (S) and Hold (HOLD) transitions are ignored.
For any instruction to be accepted and executed, Chip Select (S
) must be driven high after
the rising edge of Serial Clock (C) that latches the last bit of the instruction, and before the
next rising edge of Serial Clock (C).
For this, “the last bit of the instruction” can be the eighth bit of the instruction code, or the
eighth bit of a data byte, depending on the instruction (except in the case of RDSR and
READ instructions). Moreover, the “next rising edge of CLOCK” might (or might not) be the
next bus transaction for some other device on the bus.
When a Write cycle is in progress, the device protects it against external interruption by
ignoring any subsequent READ, WRITE or WRSR instruction until the present cycle is
complete.
Table 3. Write-protected block size
Status register bits
Protected block
BP1 BP0 M95040 M95020 M95010
0 0 none none none none
0 1 Upper quarter 180h - 1FFh C0h - FFh 60h - 7Fh
1 0 Upper half 100h - 1FFh 80h - FFh 40h - 7Fh
1 1 Whole memory 000h - 1FFh 00h - FFh 00h - 7Fh
Protected array addresses
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