The M95080 devices are Electrically Erasable PROgrammable Memories (EEPROMs)
organized as 1024 x 8 bits, accessed through the SPI bus.
The M95080 devices can operate with a supply range from 1.8 V up to 5.5 V, and are
guaranteed over the -40 °C/+85 °C temperature range.
Figure 1.Logic diagram
The SPI bus signals are C, D and Q, as shown in Figure 1 and Tab l e 1 . The device is
selected when Chip Select (S
interrupted when the HOLD
Table 1.Signal names
Signal nameFunctionDirection
CSerial ClockInput
DSerial Data InputInput
QSerial Data OutputOutput
S
W
HoldInput
HOLD
V
CC
V
SS
) is driven low. Communications with the device can be
is driven low.
Chip SelectInput
Write ProtectInput
Supply voltage
Ground
6/42Doc ID 022540 Rev 1
M95080 M95080-W M95080-RDescription
DV
SS
C
HOLDQ
SV
CC
W
AI01790D
M95xxx
1
2
3
4
8
7
6
5
Figure 2.8-pin package connections (top view)
1. See Section 10: Package mechanical data section for package dimensions, and how to identify pin 1.
Doc ID 022540 Rev 17/42
Memory organizationM95080 M95080-W M95080-R
AI01272d
HOLD
S
W
Control logic
High voltage
generator
I/O shift register
Address register
and counter
Data
register
1 page
X decoder
Y decoder
C
D
Q
Size of the
read-only
EEPROM
area
Status
Register
2 Memory organization
The memory is organized as shown in the following figure.
Figure 3.Block diagram
8/42Doc ID 022540 Rev 1
M95080 M95080-W M95080-RSignal description
3 Signal description
During all operations, VCC must be held stable and within the specified valid range:
V
(min) to VCC(max).
CC
All of the input and output signals must be held high or low (according to voltages of V
V
, VIL or VOL, as specified in Section 9: DC and AC parameters). These signals are
OH
described next.
3.1 Serial Data Output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
3.2 Serial Data Input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be written. Values are latched on the rising edge of Serial Clock
(C).
,
IH
3.3 Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) change from the falling edge of Serial Clock (C).
3.4 Chip Select (S)
When this input signal is high, the device is deselected and Serial Data Output (Q) is at high
impedance. The device is in the Standby Power mode, unless an internal Write cycle is in
progress. Driving Chip Select (S
After power-up, a falling edge on Chip Select (S
instruction.
3.5 Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S
) low selects the device, placing it in the Active Power mode.
) is required prior to the start of any
) driven low.
Doc ID 022540 Rev 19/42
Signal descriptionM95080 M95080-W M95080-R
3.6 Write Protect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is
protected against Write instructions (as specified by the values in the BP1 and BP0 bits of
the Status Register).
This pin must be driven either high or low, and must be stable during all Write instructions.
3.7 V
supply voltage
CC
VCC is the supply voltage.
3.8 VSS ground
VSS is the reference for all signals, including the VCC supply voltage.
10/42Doc ID 022540 Rev 1
M95080 M95080-W M95080-RConnecting to the SPI bus
AI12836b
SPI Bus Master
SPI Memory
Device
SDO
SDI
SCK
CQD
S
SPI Memory
Device
CQD
S
SPI Memory
Device
CQD
S
CS3CS2 CS1
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
W
HOLD
W
HOLD
W
HOLD
RR R
V
CC
V
CC
V
CC
V
CC
V
SS
V
SS
V
SS
V
SS
R
4 Connecting to the SPI bus
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction
(such as the Read from Memory Array and Read Status Register instructions) have been
clocked into the device.
Figure 4.Bus master and memory devices on the SPI bus
) goes low.
1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.
Figure 4 shows an example of three memory devices connected to an SPI bus master. Only
one memory device is selected at a time, so only one memory device drives the Serial Data
Output (Q) line at a time. The other memory devices are high impedance.
The pull-up resistor R (represented in Figure 4) ensures that a device is not selected if the
Bus Master leaves the S
line in the high impedance state.
In applications where the Bus Master may leave all SPI bus lines in high impedance at the
same time (for example, if the Bus Master is reset during the transmission of an instruction),
the clock line (C) must be connected to an external pull-down resistor so that, if all
inputs/outputs become high impedance, the C line is pulled low (while the S
high): this ensures that S
t
requirement is met. The typical value of R is 100 kΩ..
SHCH
and C do not become high at the same time, and so, that the
Doc ID 022540 Rev 111/42
line is pulled
Connecting to the SPI busM95080 M95080-W M95080-R
AI01438B
C
MSB
CPHA
D
0
1
CPOL
0
1
Q
C
MSB
4.1 SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the following two modes:
●CPOL=0, CPHA=0
●CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 5, is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
●C remains at 0 for (CPOL=0, CPHA=0)
●C remains at 1 for (CPOL=1, CPHA=1)
Figure 5.SPI modes supported
12/42Doc ID 022540 Rev 1
M95080 M95080-W M95080-ROperating features
5 Operating features
5.1 Supply voltage (VCC)
5.1.1 Operating supply voltage V
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [V
(min), VCC(max)] range must be applied (see Operating conditions
CC
in Section 9: DC and AC parameters). This voltage must remain stable and valid until the
end of the transmission of the instruction and, for a Write instruction, until the completion of
the internal write cycle (t
recommended to decouple the V
10 nF to 100 nF) close to the V
). In order to secure a stable DC supply voltage, it is
W
CC
CC/VSS
5.1.2 Device reset
In order to prevent erroneous instruction decoding and inadvertent Write operations during
power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not
respond to any instruction until VCC reaches the POR threshold voltage. This threshold is
lower than the minimum V
and AC parameters).
At power-up, when V
CC
following state:
●in Standby Power mode,
●deselected,
●Status Register values:
–The Write Enable Latch (WEL) bit is reset to 0.
–The Write In Progress (WIP) bit is reset to 0.
–The SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits).
operating voltage (see Operating conditions in Section 9: DC
CC
passes over the POR threshold, the device is reset and is in the
CC
line with a suitable capacitor (usually of the order of
device pins.
It is important to note that the device must not be accessed until V
stable level within the specified [V
conditions in Section 9: DC and AC parameters.
5.1.3 Power-up conditions
When the power supply is turned on, VCC rises continuously from VSS to VCC. During this
time, the Chip Select (S
therefore recommended to connect the S
Figure 4).
In addition, the Chip Select (S
sensitive as well as level-sensitive: after power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S
(S
) must have been high, prior to going low to start the first operation.
The V
voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
CC
defined under Operating conditions in Section 9: DC and AC parameters, and the rise time
must not vary faster than 1 V/µs.
) line is not allowed to float but should follow the VCC voltage. It is
reaches a valid and
(min), VCC(max)] range, as defined under Operating
CC
CC
line to VCC via a suitable pull-up resistor (see
) input offers a built-in safety feature, as the S input is edge-
). This ensures that Chip Select
Doc ID 022540 Rev 113/42
Operating featuresM95080 M95080-W M95080-R
AI02029D
HOLD
C
Hold
Condition
Hold
Condition
5.1.4 Power-down
During power-down (continuous decrease of the VCC supply voltage below the minimum
V
operating voltage defined under Operating conditions in Section 9: DC and AC
CC
parameters), the device must be:
●deselected (Chip Select S should be allowed to follow the voltage applied on V
●in Standby Power mode (there should not be any internal write cycle in progress).
CC
),
5.2 Active Power and Standby Power modes
When Chip Select (S) is low, the device is selected, and in the Active Power mode. The
device consumes I
When Chip Select (S
.
CC
) is high, the device is deselected. If a Write cycle is not currently in
progress, the device then goes into the Standby Power mode, and the device consumption
drops to I
, as specified in DC characteristics (see Section 9: DC and AC parameters).
CC1
5.3 Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
To enter the Hold condition, the device must be selected, with Chip Select (S
) low.
During the Hold condition, the Serial Data Output (Q) is high impedance, and the Serial
Data Input (D) and the Serial Clock (C) are Don’t Care.
Normally, the device is kept selected for the whole duration of the Hold condition.
Deselecting the device while it is in the Hold condition has the effect of resetting the state of
the device, and this mechanism can be used if required to reset any processes that had
been in progress.
(a)(b)
Figure 6.Hold condition activation
The Hold condition starts when the Hold (HOLD) signal is driven low when Serial Clock (C)
is already low (as shown in Figure 6).
a. This resets the internal logic, except the WEL and WIP bits of the Status Register.
b. In the specific case where the device has shifted in a Write command (Inst + Address + data bytes, each data
byte being exactly 8 bits), deselecting the device also triggers the Write cycle of this decoded command.
14/42Doc ID 022540 Rev 1
M95080 M95080-W M95080-ROperating features
The Hold condition ends when the Hold (HOLD) signal is driven high when Serial Clock (C)
is already low.
Figure 6 also shows what happens if the rising and falling edges are not timed to coincide
with Serial Clock (C) being low.
5.4 Status Register
The Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a
detailed description of the Status Register bits.
5.5 Data protection and protocol control
The device features the following data protection mechanisms:
●Before accepting the execution of the Write and Write Status Register instructions, the
device checks whether the number of clock pulses comprised in the instructions is a
multiple of eight.
●All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit.
●The Block Protect (BP1, BP0) bits in the Status Register are used to configure part of
the memory as read-only.
●The Write Protect (W) signal is used to protect the Block Protect (BP1, BP0) bits in the
Status Register.
For any instruction to be accepted, and executed, Chip Select (S
) must be driven high after
the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising
edge of Serial Clock (C).
Two points should be noted in the previous sentence:
●The “last bit of the instruction” can be the eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction (except for Read Status Register
(RDSR) and Read (READ) instructions).
●The “next rising edge of Serial Clock (C)” might (or might not) be the next bus
transaction for some other device on the SPI bus.
Table 2.Write-protected block size
Status Register bits
Protected block Protected array addresses
BP1 BP0
0 0 nonenone
0 1 Upper quarter0300h - 03FFh
1 0 Upper half 0200h - 03FFh
1 1 Whole memory0000h - 03FFh
Doc ID 022540 Rev 115/42
InstructionsM95080 M95080-W M95080-R
C
D
AI02281E
S
Q
2134567
High Impedance
0
Instruction
6 Instructions
Each instruction starts with a single-byte code, as summarized in Ta b le 3 .
If an invalid instruction is sent (one not contained in Ta bl e 3 ), the device automatically
deselects itself.
Table 3.Instruction set
InstructionDescriptionInstruction format
WREN Write Enable0000 0110
WRDI Write Disable0000 0100
RDSR Read Status Register 0000 0101
WRSR Write Status Register 0000 0001
READ Read from Memory Array0000 0011
WRITE Write to Memory Array 0000 0010
Table 4.Address range bits
Address significant bitsA9-A0
1. Upper MSBs are Don’t Care.
(1)
6.1 Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in Figure 7, to send this instruction to the device, Chip Select (S
and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then
enters a wait state. It waits for the device to be deselected, by Chip Select (S
high.
Figure 7.Write Enable (WREN) sequence
) is driven low,
) being driven
16/42Doc ID 022540 Rev 1
M95080 M95080-W M95080-RInstructions
C
D
AI03750D
S
Q
2134567
High Impedance
0
Instruction
6.2 Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in Figure 8, to send this instruction to the device, Chip Select (S
) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S
) being driven high.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
●Power-up
●WRDI instruction execution
●WRSR instruction completion
●WRITE instruction completion.
Figure 8.Write Disable (WRDI) sequence
Doc ID 022540 Rev 117/42
InstructionsM95080 M95080-W M95080-R
C
D
S
213456789101112131415
Instruction
0
AI02031E
Q
7 6543210
Status Register Out
High Impedance
MSB
7 6543210
Status Register Out
MSB
7
6.3 Read Status Register (RDSR)
The Read Status Register (RDSR) instruction is used to read the Status Register. The
Status Register may be read at any time, even while a Write or Write Status Register cycle
is in progress. When one of these cycles is in progress, it is recommended to check the
Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible
to read the Status Register continuously, as shown in Figure 9.
Figure 9.Read Status Register (RDSR) sequence
The status and control bits of the Status Register are as follows:
6.3.1 WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0, no such
cycle is in progress.
6.3.2 WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1, the internal Write Enable Latch is set. When set to 0, the internal Write
Enable Latch is reset, and no Write or Write Status Register instruction is accepted.
The WEL bit is returned to its reset state by the following events:
●Power-up
●Write Disable (WRDI) instruction completion
●Write Status Register (WRSR) instruction completion
●Write (WRITE) instruction completion
6.3.3 BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non volatile. They define the size of the area to be
software-protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set
to 1, the relevant memory area (as defined in Ta bl e 2 ) becomes protected against Write
18/42Doc ID 022540 Rev 1
(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set.
M95080 M95080-W M95080-RInstructions
6.3.4 SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W
signal enable the device to be put in the Hardware Protected mode (when the Status
Register Write Disable (SRWD) bit is set to 1, and Write Protect (W
mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits
and the Write Status Register (WRSR) instruction is no longer accepted for execution.
Table 5.Status Register format
Status Register Write Protect
) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
) is driven low). In this
b7 b0
SRWD0 0 0 BP1 BP0 WEL WIP
Block Protect bits
Write Enable Latch bit
Write In Progress bit
Doc ID 022540 Rev 119/42
InstructionsM95080 M95080-W M95080-R
C
D
AI02282D
S
Q
213456789101112131415
High Impedance
InstructionStatus
Register In
0
7654320
1
MSB
6.4 Write Status Register (WRSR)
The Write Status Register (WRSR) instruction is used to write new values to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must have been
previously executed.
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S
followed by the instruction code, the data byte on Serial Data input (D) and Chip Select (S
driven high. Chip Select (S
) must be driven high after the rising edge of Serial Clock (C) that
) low,
)
latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C).
Otherwise, the Write Status Register (WRSR) instruction is not executed.
The instruction sequence is shown in Figure 10.
Figure 10. Write Status Register (WRSR) sequence
Driving the Chip Select (S
timed Write cycle that takes t
) signal high at a byte boundary of the input data triggers the self-
to complete (as specified in AC tables under Section 9: DC
W
and AC parameters).
While the Write Status Register cycle is in progress, the Status Register may still be read to
check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed
Write cycle t
also reset at the end of the Write cycle t
, and 0 when the Write cycle is complete. The WEL bit (Write Enable Latch) is
W
W
The Write Status Register (WRSR) instruction enables the user to change the values of the
BP1, BP0 and SRWD bits:
●The Block Protect (BP1, BP0) bits define the size of the area that is to be treated as
read-only, as defined in Ta bl e 2 .
●The SRWD (Status Register Write Disable) bit, in accordance with the signal read on
the Write Protect pin (W
), enables the user to set or reset the Write protection mode of
the Status Register itself, as defined in Tab l e 6 . When in Write-protected mode, the
Write Status Register (WRSR) instruction is not executed.
The contents of the SRWD and BP1, BP0 bits are updated after the completion of the
WRSR instruction, including the t
Write cycle.
W
The Write Status Register (WRSR) instruction has no effect on the b6, b5, b4, b1, b0 bits in
the Status Register. Bits b6, b5, b4 are always read as 0.
20/42Doc ID 022540 Rev 1
.
M95080 M95080-W M95080-RInstructions
Table 6.Protection modes
W
SRWD
signal
10
00
11
01
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register. See Table 2.
bit
Mode
Softwareprotected
(SPM)
Hardware-
protected
(HPM)
Write protection of the
Status Register
Status Register is
writable (if the WREN
instruction has set the
WEL bit).
The values in the BP1
and BP0 bits can be
changed.
Status Register is
Hardware writeprotected.
The values in the BP1
and BP0 bits cannot be
changed.
Protected area
Write-protected
Write-protected
Memory content
(1)
Unprotected area
Ready to accept
Write instructions
Ready to accept
Write instructions
The protection features of the device are summarized in Tab l e 6 .
When the Status Register Write Disable (SRWD) bit in the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register (provided that the WEL bit has
previously been set by a WREN instruction), regardless of the logic level applied on the
Write Protect (W
) input pin.
(1)
When the Status Register Write Disable (SRWD) bit in the Status Register is set to 1, two
cases should be considered, depending on the state of the Write Protect (W
●If Write Protect (W) is driven high, it is possible to write to the Status Register (provided
) input pin:
that the WEL bit has previously been set by a WREN instruction).
●If Write Protect (W) is driven low, it is not possible to write to the Status Register even if
the WEL bit has previously been set by a WREN instruction. (Attempts to write to the
Status Register are rejected, and are not accepted for execution). As a consequence,
all the data bytes in the memory area, which are Software-protected (SPM) by the
Block Protect (BP1, BP0) bits in the Status Register, are also hardware-protected
against data modification.
Regardless of the order of the two events, the Hardware-protected mode (HPM) can be
entered by:
●either setting the SRWD bit after driving the Write Protect (W) input pin low,
●or driving the Write Protect (W) input pin low after setting the SRWD bit.
Once the Hardware-protected mode (HPM) has been entered, the only way of exiting it is to
pull high the Write Protect (W
If the Write Protect (W
) input pin is permanently tied high, the Hardware-protected mode
) input pin.
(HPM) can never be activated, and only the Software-protected mode (SPM), using the
Block Protect (BP1, BP0) bits in the Status Register, can be used.
Doc ID 022540 Rev 121/42
InstructionsM95080 M95080-W M95080-R
C
D
AI01793D
S
Q
15
21345678910 2021222324252627
1413 3210
28 29 30
7654317
0
High Impedance
Data Out 1
Instruction16-Bit Address
0
MSB
MSB
2
31
Data Out 2
6.5 Read from Memory Array (READ)
As shown in Figure 11, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data
Input (D). The address is loaded into an internal address register, and the byte of data at
that address is shifted out, on Serial Data Output (Q).
Figure 11. Read from Memory Array (READ) sequence
1. Depending on the memory size, as shown in Table 4, the most significant address bits are Don’t Care.
If Chip Select (S) continues to be driven low, the internal address register is incremented
automatically, and the byte of data at the new address is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the
Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a
single READ instruction.
The Read cycle is terminated by driving Chip Select (S
Select (S
) signal can occur at any time during the cycle.
) high. The rising edge of the Chip
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
22/42Doc ID 022540 Rev 1
M95080 M95080-W M95080-RInstructions
C
D
AI01795D
S
Q
15
21345678910 2021222324252627
1413 3210
28 29 30
High Impedance
Instruction16-Bit Address
0
7654320
1
Data Byte
31
6.6 Write to Memory Array (WRITE)
As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte, address byte, and at least one data byte are then shifted
in, on Serial Data Input (D).
The instruction is terminated by driving Chip Select (S
data. The self-timed Write cycle, triggered by the Chip Select (S
period t
(as specified in AC characteristics in Section 9: DC and AC parameters), at the
W
) high at a byte boundary of the input
) rising edge, continues for a
end of which the Write in Progress (WIP) bit is reset to 0.
Figure 12. Byte Write (WRITE) sequence
1. Depending on the memory size, as shown in Table 4, the most significant address bits are Don’t Care.
In the case of Figure 12, Chip Select (S) is driven high after the eighth bit of the data byte
has been latched in, indicating that the instruction is being used to write a single byte.
However, if Chip Select (S
) continues to be driven low, as shown in Figure 13, the next byte
of input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If the number of data bytes sent to the device exceeds the page
boundary, the internal address counter rolls over to the beginning of the page, and the
previous data there are overwritten with the incoming data. (The page size of these devices
is 32 bytes).
The instruction is not accepted, and is not executed, under the following conditions:
●if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before),
●if a Write cycle is already in progress,
●if the device has not been deselected, by driving high Chip Select (S), at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in),
●if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits.
Note:The self-timed write cycle t
is internally executed as a sequence of two consecutive
W
events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is
read as “0” and a programmed bit is read as “1”.
Doc ID 022540 Rev 123/42
InstructionsM95080 M95080-W M95080-R
C
D
AI01796D
S
343335 36 37 38 39 40 41 4244 45 46 4732
C
D
S
15
21345678910 2021222324252627
1413 3210
28 29 30
Instruction16-Bit Address
0
7654320
1
Data Byte 1
31
43
7654320
1
Data Byte 2
7654320
1
Data Byte 3
654320
1
Data Byte N
Figure 13. Page Write (WRITE) sequence
1. Depending on the memory size, as shown in Table 4, the most significant address bits are Don’t Care.
24/42Doc ID 022540 Rev 1
M95080 M95080-W M95080-RPower-up and delivery state
7 Power-up and delivery state
7.1 Power-up state
After power-up, the device is in the following state:
●Standby power mode,
●deselected (after power-up, a falling edge is required on Chip Select (S) before any
instructions can be started),
●not in the Hold condition,
●the Write Enable Latch (WEL) is reset to 0,
●Write In Progress (WIP) is reset to 0.
The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous
power-down (they are non-volatile bits).
7.2 Initial delivery state
The device is delivered with the memory array set to all 1s (each byte = FFh). The Status
Register Write Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.
Doc ID 022540 Rev 125/42
Maximum ratingM95080 M95080-W M95080-R
8 Maximum rating
Stressing the device outside the ratings listed in Ta bl e 7 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 7.Absolute maximum ratings
SymbolParameterMin.Max.Unit
Ambient operating temperature–40130°C
T
STG
T
LEAD
V
V
V
I
OL
I
OH
V
ESD
1. Compliant with JEDEC Std J-STD-020 (for small body, Sn-Pb or Pb assembly), with the ST ECOPACK®
7191395 specification, and with the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU.
2. Positive and negative pulses applied on pin pairs, according to AEC-Q100-002 (compliant with JEDEC Std
JESD22-A114, C1=100 pF, R1=1500 Ω, R2=500 Ω).
O
CC
Storage temperature–65150°C
Lead temperature during solderingSee note
Output voltage–0.50VCC+0.6V
Input voltage–0.506.5V
I
Supply voltage–0.506.5V
DC output current (Q = 0)5mA
DC output current (Q = 1)5mA
Electrostatic discharge voltage (human body model)
(2)
4000V
(1)
°C
26/42Doc ID 022540 Rev 1
M95080 M95080-W M95080-RDC and AC parameters
!)#
6
##
6
##
6
##
6
##
)NPUTANDOUTPUT
TIMINGREFERENCELEVELS
)NPUTVOLTAGELEVELS
9 DC and AC parameters
This section summarizes the operating conditions and the DC/AC characteristics of the
device.
End of life products: these values apply only to M95080-WMN6TP/S
and M95080-WDW6TP/S devices)
Test conditions specified in Tab l e 9 and Ta b l e 1 1
SymbolAlt.ParameterMin.Max.Unit
f
C
t
SLCH
t
SHCH
t
SHSL
t
CHSH
t
CHSL
(1)
t
CH
(1)
t
CL
(2)
t
CLCH
(2)
t
CHCL
t
DVCH
t
CHDX
t
HHCH
t
HLCH
t
CLHL
t
CLHH
t
SHQZ
t
CLQV
t
CLQX
t
QLQH
t
QHQL
t
HHQV
(2)
t
HLQZ
t
W
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
2. Characterized only, not tested in production.
(2)
(2)
(2)
f
SCK
t
CSS1
t
CSS2
t
CS
t
CSH
t
CLH
t
CLL
t
RC
t
FC
t
DSU
t
DH
t
DIS
t
t
HO
t
RO
t
FO
t
LZ
t
HZ
t
WC
Clock frequencyD.C.5MHz
S active setup time90ns
S not active setup time90ns
S deselect time100ns
S active hold time90ns
S not active hold time90ns
Clock high time90ns
Clock low time90ns
Clock rise time1µs
Clock fall time1µs
Data in setup time20ns
Data in hold time30ns
Clock low hold time after HOLD not active70ns
Clock low hold time after HOLD active40ns
Clock low set-up time before HOLD active0ns
Clock low set-up time before HOLD not active0ns
Output disable time100ns
Clock low to output valid60ns
V
Output hold time0ns
Output rise time50ns
Output fall time50ns
HOLD high to output valid50ns
HOLD low to output high-Z100ns
Write time5ms
34/42Doc ID 022540 Rev 1
M95080 M95080-W M95080-RDC and AC parameters
C
Q
AI01448c
S
HOLD
tCLHL
tHLCH
tHHCH
tCLHH
tHHQVtHLQZ
Figure 15. Serial input timing
tSHSL
S
tSLCH
C
tDVCH
tCHCL
tCHDX
tCH
tCL
tCHSHtCHSL
tCLCH
tSHCH
D
Q
High impedance
Figure 16. Hold timing
MSB IN
LSB IN
AI01447d
Doc ID 022540 Rev 135/42
DC and AC parametersM95080 M95080-W M95080-R
C
Q
AI01449f
S
D
ADDR
LSB IN
tSHQZ
tCH
tCL
tQLQH
tQHQL
tCHCL
tCLQX
tCLQV
tSHSL
tCLCH
Figure 17. Serial output timing
36/42Doc ID 022540 Rev 1
M95080 M95080-W M95080-RPackage mechanical data
SO-A
E1
8
ccc
b
e
A
D
c
1
E
h x 45˚
A2
k
0.25 mm
L
L1
A1
GAUGE PLANE
10 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
Figure 18. SO8N – 8-lead plastic small outline, 150 mils body width, package outline
1. Drawing is not to scale.
Table 20.SO8N – 8-lead plastic small outline, 150 mils body width, mechanical data
millimetersinches
Symbol
TypMinMaxTypMinMax
(1)
A1.7500.0689
A10.1000.2500.00390.0098
A21.2500.0492
b0.2800.4800.01100.0189
c0.1700.2300.00670.0091
ccc0.1000.0039
D4.9004.8005.0000.19290.18900.1969
E6.0005.8006.2000.23620.22830.2441
E13.9003.8004.0000.15350.14960.1575
e1.270--0.0500--
h0.2500.5000.00980.0197
k0°8°0°8°
L0.4001.2700.01570.0500
L11.0400.0409
1. Values in inches are converted from mm and rounded to four decimal digits.
Doc ID 022540 Rev 137/42
Package mechanical dataM95080 M95080-W M95080-R
$
%
:7?-%E
!
!
EEE
,
E
B
$
,
%
,
,
EB
$
,
%
,
0IN
+
+
-"-#
Figure 19. UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package
outline
1. Drawing is not to scale.
2. The central pad (the area E2 by D2 in the above illustration) is internally pulled to V
connected to any other voltage or signal line on the PCB, for example during the soldering process.
Table 21.UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
. It must not be
SS
2 x 3 mm, data
millimetersinches
Symbol
TypMinMaxTypMinMax
(1)
A0.5500.4500.6000.02170.01770.0236
A10.0200.0000.0500.00080.00000.0020
b0.2500.2000.3000.00980.00790.0118
D2.0001.9002.1000.07870.07480.0827
D2 (rev MB)1.6001.5001.7000.06300.05910.0669
D2 (rev MC)1.2001.6000.04720.0630
E3.0002.9003.1000.11810.11420.1220
E2 (rev MB)0.2000.1000.3000.00790.00390.0118
E2 (rev MC)1.2001.6000.04720.0630
e0.5000.0197
K (rev MB)0.8000.0315
K (rev MC)0.3000.0118
L0.3000.5000.01180.0197
L10.1500.0059
L30.3000.0118
(2)
eee
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from
Table 22.TSSOP8 – 8-lead thin shrink small outline, package mechanical data
millimetersinches
Symbol
TypMinMaxTypMinMax
(1)
A1.2000.0472
A10.0500.1500.00200.0059
A21.0000.8001.0500.03940.03150.0413
b0.1900.3000.00750.0118
c0.0900.2000.00350.0079
CP0.1000.0039
D3.0002.9003.1000.11810.11420.1220
e0.650--0.0256--
E6.4006.2006.6000.25200.24410.2598
E14.4004.3004.5000.17320.16930.1772
L0.6000.4500.7500.02360.01770.0295
L11.0000.0394
α0°8°0°8°
N88
1. Values in inches are converted from mm and rounded to four decimal digits.
Doc ID 022540 Rev 139/42
Part numberingM95080 M95080-W M95080-R
11 Part numbering
Table 23.Ordering information scheme
Example:M95080W MN 6TP /S
Device type
M95 = SPI serial access EEPROM
Device function
080 = 8 Kbit (1024 x 8)
Operating voltage
blank = V
W = V
R = V
Package
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
MB or MC = UFDFPN8 (MLP8)
= 4.5 to 5.5 V
CC
= 2.5 to 5.5 V
CC
= 1.8 to 5.5 V
CC
Device grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
Option
blank = Standard packing
T = Tape and reel packing
Plating technology
G or P = RoHS compliant and halogen-free
(ECOPACK®)
Process
(1)
/G or /S = Manufacturing technology code
1. The process letters appear on the device package (marking) and on the shipment box. Please contact your
nearest ST Sales Office.
40/42Doc ID 022540 Rev 1
M95080 M95080-W M95080-RRevision history
12 Revision history
Table 24.Document revision history
DateRevisionChanges
22-Mar-20121Initial release.
Doc ID 022540 Rev 141/42
M95080 M95080-W M95080-R
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