ST M95040-125, M95020-125, M95010-125 User Manual

Automotive 4-Kbit, 2-Kbit and 1-Kbit SPI bus EEPROM

SO8 (MN)

150 mil width

TSSOP8 (DW)

169 mil width

Features

■ Compatible with the Serial Peripheral Interface

(SPI) bus

■ Memory array

– 1 Kbit, 2 Kbit or 4 Kbit of EEPROM – Page size: 16 bytes – Write protection by block: 1/4, 1/2 or whole

memory

■ 5 MHz clock frequency

■ Write cycle within 5 ms

■ Operating temperature range: -40 °C to

+125 °C

■ Single supply voltage:

– 4.5 V to 5.5 V for M950x0 – 2.5 V to 5.5 V for M950x0-W

■ More than 1 million Write cycles

■ More than 40-year data retention

■ Enhanced ESD protection

■ Packages

– RoHS-compliant and halogen-free

(ECOPACK2

)

M95040-125

M95020-125 M95010-125

January 2012 Doc ID 022545 Rev 1 1/36

www.st.com

Contents M95040-125, M95020-125, M95010-125

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.4 Chip Select (S

2.5 Hold (HOLD

2.6 Write Protect (W

2.7 V

ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.8 Supply voltage (V

2.9 Supply voltage (V

2.9.1 Operating supply voltage V

2.9.2 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.9.3 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.9.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.1 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.2 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.3 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.3 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.3.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.3.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2/36 Doc ID 022545 Rev 1

M95040-125, M95020-125, M95010-125 Contents

6.3.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.4 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.5 Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.6 Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7 Power-up and delivery states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.2 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

9 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

11 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Doc ID 022545 Rev 1 3/36

List of tables M95040-125, M95020-125, M95010-125

List of tables

Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2. Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 3. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 4. Status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 5. Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 6. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 7. Operating conditions (M950x0, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 8. Operating conditions (M950x0-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 9. AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 10. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 11. DC characteristics (M950x0, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 12. DC characteristics (M950x0-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 13. AC characteristics (M950x0, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 14. AC characteristics (M950x0-W, device grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 15. SO8N — 8-lead plastic small outline, 150 mils body width, package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 16. TSSOP8 — 8-lead thin shrink small outline, package mechanical data . . . . . . . . . . . . . . . 33

Table 17. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 18. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4/36 Doc ID 022545 Rev 1

M95040-125, M95020-125, M95010-125 List of figures

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 5. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 7. Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 8. Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 9. Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 10. Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 11. Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 12. Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 13. Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 14. AC test measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 15. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 16. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 17. Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 18. SO8N — 8-lead plastic small outline 150 mils body width, package outline. . . . . . . . . . . . 32

Figure 19. TSSOP8 — 8-lead thin shrink small outline, package outline. . . . . . . . . . . . . . . . . . . . . . . 33

Doc ID 022545 Rev 1 5/36

Description M95040-125, M95020-125, M95010-125

AI01789C

M95xxx

HOLD

HOLDQ

AI01790D

M95xxx

1 2 3 4

1 Description

The M950x0-125 devices are 1-Kbit, 2-Kbit and 4-Kbit Electrically Erasable PROgrammable

Memories (EEPROM) accessed through the SPI bus, synchronized with a clock running up

to 5 MHz.

The devices can operate with supply voltages ranging from 2.5 V to 5.5 V.

The devices are guaranteed over the -40°C/+125°C temperature range and are compliant

with the Automotive standard AEC-Q100 Grade 1.

Figure 1. Logic diagram

Figure 2. 8-pin package connections

1. See Section 10: Package mechanical data for package dimensions, and how to identify pin 1.

6/36 Doc ID 022545 Rev 1

M95040-125, M95020-125, M95010-125 Description

Table 1. Signal names

Signal name Function

C Serial Clock

D Serial Data input

Q Serial Data output

S Chip Select

Write Protect

Hold

HOLD

Supply voltage

Ground

Doc ID 022545 Rev 1 7/36

Signal description M95040-125, M95020-125, M95010-125

2 Signal description

During all operations, VCC must be held stable and within the specified valid range:

(min) to VCC(max).

All of the input and output signals can be held high or low (according to voltages of V

or VOL, as specified in Section 9: DC and AC parameters). These signals are described

next.

2.1 Serial Data output (Q)

This output signal is used to transfer data serially out of the device. Data is shifted out on the

falling edge of Serial Clock (C).

2.2 Serial Data input (D)

This input signal is used to transfer data serially into the device. It receives instructions,

addresses, and the data to be written. Values are latched on the rising edge of Serial Clock

(C).

, VOH,

2.3 Serial Clock (C)

This input signal provides the timing of the serial interface. Instructions, addresses, or data

present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on

Serial Data Output (Q) changes after the falling edge of Serial Clock (C).

2.4 Chip Select (S)

When this input signal is high, the device is deselected and Serial Data Output (Q) is at high

impedance. Unless an internal Write cycle is in progress, the device will be in the Standby

Power mode. Driving Chip Select (S

mode.

After Power-up, a falling edge on Chip Select (S

instruction.

2.5 Hold (HOLD)

The Hold (HOLD) signal is used to pause any serial communications with the device without

deselecting the device.

During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data

Input (D) and Serial Clock (C) are Don’t Care.

To start the Hold condition, the device must be selected, with Chip Select (S

) low selects the device, placing it in the Active Power

) is required prior to the start of any

) driven low.

8/36 Doc ID 022545 Rev 1

M95040-125, M95020-125, M95010-125 Signal description

2.6 Write Protect (W)

This input signal is used to control whether the memory is write protected. When Write

Protect (W

enabled. Write Protect (W

) is held low, writes to the memory are disabled, but other operations remain

) must either be driven high or low, but must not be left floating.

2.7 VSS ground

VSS is the reference for the VCC supply voltage.

2.8 Supply voltage (VCC)

2.9 Supply voltage (V

)

2.9.1 Operating supply voltage V

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage

within the specified [V

(min), VCC(max)] range must be applied (see operating condition

tables in Section 9: DC and AC parameters). This voltage must remain stable and valid until

the end of the transmission of the instruction and, for a Write instruction, until the completion

of the internal write cycle (t

recommended to decouple the V

nF to 100 nF) close to the V

). In order to secure a stable DC supply voltage, it is

CC/VSS

2.9.2 Device reset

In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)

circuit is included. At power-up, the device does not respond to any instruction until V

reaches the internal reset threshold voltage (this threshold is defined in operating condition

tables in Section 9: DC and AC parameters) as V

When V

● in Standby Power mode

● deselected (note that, to be executed, an instruction must be preceded by a falling

● Status register value:

passes over the POR threshold, the device is reset and is in the following state:

edge on Chip Select (S

))

– the Write Enable Latch (WEL) is reset to 0 – Write In Progress (WIP) is reset to 0 – The SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits)

line with a suitable capacitor (usually of the order of 10

package pins.

RES

When V

passes over the POR threshold, the device is reset and enters the Standby

Power mode. The device must not be accessed until V

voltage within the specified [V

(min), VCC(max)] range defined in operating condition

tables in Section 9: DC and AC parameters.

Doc ID 022545 Rev 1 9/36

reaches a valid and stable VCC

Signal description M95040-125, M95020-125, M95010-125

2.9.3 Power-up conditions

When the power supply is turned on, VCC rises continuously from VSS to VCC. During this

time, the Chip Select (S

therefore recommended to connect the S

Figure 3).

) line is not allowed to float but should follow the VCC voltage. It is

line to VCC via a suitable pull-up resistor (see

In addition, the Chip Select (S

sensitive as well as level sensitive: after power-up, the device does not become selected

until a falling edge has first been detected on Chip Select (S

) must have been high, prior to going low to start the first operation.

The V

voltage has to rise continuously from 0 V up to the minimum VCC operating voltage

defined in operating condition tables in Section 9: DC and AC parameters and the rise time

must not vary faster than 1 V/µs.

2.9.4 Power-down

During power-down (continuous decrease in the VCC supply voltage below the minimum

operating voltage defined in operating condition tables in Section 9: DC and AC

parameters), the device must be:

● deselected (Chip Select S should be allowed to follow the voltage applied on V

● in Standby Power mode (there should not be any internal write cycle in progress).

) input offers a built-in safety feature, as the S input is edge

). This ensures that Chip Select

)

10/36 Doc ID 022545 Rev 1

M95040-125, M95020-125, M95010-125 Connecting to the SPI bus

AI12304b

Bus master

SPI memory

device

SDO

SDI

SCK

CQD

SPI memory

device

CQD

SPI mmory

device

CQD

CS3 CS2 CS1

SPI Interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

HOLD

RRR

3 Connecting to the SPI bus

These devices are fully compatible with the SPI protocol.

All instructions, addresses and input data bytes are shifted in to the device, most significant

bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)

after Chip Select (S

All output data bytes are shifted out of the device, most significant bit first. The Serial Data

Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction

(such as the Read from Memory Array and Read Status Register instructions) have been

clocked into the device.

Figure 3 shows an example of three memory devices connected to an MCU, on an SPI bus.

Only one memory device is selected at a time, so only one memory device drives the Serial

Data output (Q) line at a time, the other memory devices are high impedance.

The pull-up resistor R (represented in Figure 3) ensures that a device is not selected if the

bus master leaves the S

In applications where the bus master might enter a state where all SPI bus inputs/outputs

would be in high impedance at the same time (for example, if the bus master is reset during

the transmission of an Instruction), the clock line (C) must be connected to an external pull-

down resistor so that, if all inputs/outputs become high impedance, the C line is pulled low

(while the S

line is pulled high): this ensures that S and C do not become high at the same

time, and so, that the t

) goes low.

line in the high impedance state.

requirement is met. The typical value of R is 100 kΩ.

SHCH

Figure 3. Bus master and memory devices on the SPI bus

1. The Write Protect (W) and Hold (HOLD) signals should be driven high or low as appropriate.

Doc ID 022545 Rev 1 11/36

+ 25 hidden pages