ST M87C257 User Manual

M87C257

ADDRESS LATCHED

256K (32K x 8) UV EPROM and OTP EPROM

June 1996 1/13

AI00928B

A0-A14

ASV

Q0-Q7

M87C257

Figure 1. Logic Diag ra m

INTEGRA TE D ADDRE SS LATCH

FA ST ACCESS TIME: 45ns

LOW POWER “CMOS” CONSUMPTION:

– Active Current 30mA

– Standby Current 100µA

PROGRAMMING VOLTAGE: 12.75V

ELECTRONI C S IG NATURE for AUTOM ATED

PROGRAMMING

PROGRAM MING T IM ES of ARO UND 3sec.

(PRESTO II ALGORITHM)

DESCRIP TION

The M87C257 is a high speed 262,144 bit UV

erasable and electrically programmable EPROM.

The M87C257 incorporates latches for all address

inputs to minimize chip count, reduce cost, and

simplify the design of multiplexed bus systems.

The Window Ceramic Frit-Seal Dual-in-Line pack-

age has a transparent lid which allows the user to

expose the chip to ultraviolet light to erase the bit

pattern. A new pattern can then be written to the

device by following the programming procedure.

For applications where the content is pr ogrammed

only one time and erasure is not required, the

M87C257 is offered in Plas tic Leaded Chip Carrier ,

package.

A0 - A14 Address Inputs

Q0 - Q7 Data Outputs

E Chip Enable

G Output Enable

ASV

Address Strobe / Program Supply

Supply Voltage

Ground

T able 1. Signal Names

PLCC32 (C)

FDIP28W (F)

A13

A10

A14

A11

Q5Q1

Q3V

A12

ASV

AI00929

M87C257

Figure 2A. DIP Pin Connecti on s

Warning: NC = Not Connected, DU = Dont’t Use.

AI00930

A13

A10

A14

ASV

A11

M87C257

A12

Figure 2B. LCC Pin Conn ecti ons

DEVICE OPER ATION

The modes of operation of the M87C257 are listed

in the Operating Modes. A single power supply is

required in the read mode. All inputs are T TL levels

except for V

and 12V on A9 for Elect ronic S igna-

ture.

Read Mode

The M87C257 has two control functions, both of

which must be logically active in order to obtain

data at the outputs. Chip Enable (

E) is the power

control and should be used for device selection.

Output Enable (

G) is the output control and should

Symbol Parameter Value Unit

Ambient Operating Temperature –40 to 125 °C

BIAS

Temperature Under Bias –50 to 125 °C

STG

Storage Temperature –65 to 150 °C

(2)

Input or Output Voltages (except A9) –2 to 7 V

Supply Voltage –2 to 7 V

(2)

A9 Voltage –2 to 13.5 V

Program Supply Voltage –2 to 14 V

Notes: 1. Except for the rating "Operating Temperature Range", stresses above those lis ted in the Table "Absolute Maximum Ratings"

may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other

conditions above those indicated in the Operating sections of this specificat ion is not implied. Exposure to Abs olute Maxi mum

Rating conditions for extended periods may affect device reliability . Refer also to the SGS-THOMS O N SURE Program and other

relevant quality documents.

2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20 ns. Maximum DC

voltage on Output is V

+0.5V with possible ove rshoot to V

+2V for a period less than 20ns.

Tab l e 2. Absolu te Maxi mu m Ratin gs

(1)

2/13

M87C257

Mode E GA9ASV

Q0 - Q7

Read (Latched Address) V

Data Out

Read (Applied Address) V

Data Out

Output Disable V

X X Hi-Z

Program V

Pulse V

Data In

Verify V

Data Out

Program Inhibit V

Hi-Z

Standby V

X X X Hi-Z

Electronic Signature V

Codes

Note: X = V

or V

, V

= 12V ± 0.5V

T ab le 3. Operating Modes

Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data

Manufacturer’s Code V

00100000 20h

Device Code V

10000000 80h

T ab le 4. Electron ic Sig natu r e

be used to gate data to the output pins, inde-

pendent of device selection. Assuming that the

addresses are stable (

AS = V

) or latched (AS =

), the address access time (t

AVQV

) is equal to the

delay from

E to output (t

ELQV

). Data is available at

the output after delay of t

GLQV

from the falling edge

G, assuming that E has been low and the ad-

dresses have been stable for at least t

AVQV

-t

GLQV

The M87C257 reduces the hardware interface in

multiplexed address-data bus systems. The proc-

essor multiplexed bus (AD0-AD7) may be tied to

the M87C257’s address and data pins. No sepa-

rate address latch is needed because the

M87C257 latches all address inputs when

AS is

low.

Standby Mode

The M87C257 has a standby mode which reduces

the active current from 30mA to 100µA (Address

Stable). The M87C257 is placed in the standby

mode by applying a CMOS high signal to the

input. When in the standby mode, the outputs are

in a high impedance state, independent of the

input.

Two Line Output Control

Because EPROMs are usually used in larger mem-

ory arrays, this product features a 2 line control

function which accommodates the use of multiple

memory connection. The two line control function

allows:

a. the lowest possible memory power dissipation,

b. complete assuranc e that output bus cont entio n

will not occur.

For the most efficient use of thes e two control lines,

E should be decoded and used as the primary

device selecting function, while

G should be made

a common connection to all devices in the array

and connected to the

READ line from the system

control bus. This ensures that all dese lected mem-

ory devices are in their low power standby mode

and that the output pins are only active when data

is desired from a particular memory device.

3/13

M87C257

AI01822

High Speed

1.5V

2.4V

Standard

0.4V

2.0V

0.8V

Figure 3. AC Test ing Input Outp ut W avefo rm

AI01823

1.3V

OUT

= 30pF or 100pF

= 30pF for High Speed

= 100pF for Standard

includes JIG capacitance

3.3kΩ

1N914

DEVICE

UNDER

TEST

Figure 4. AC T est ing Load Circu it

High Speed Standard

Input Rise and Fall Times ≤ 10ns ≤ 20ns

Input Pulse Voltages 0 to 3V 0.4V to 2.4V

Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V

T ab le 5. AC Measurement Con ditions

Symbol Parameter Test Condition Min Max Unit

Input Capacitance V

= 0V 6 pF

OUT

Output Capacitance V

OUT

= 0V 12 pF

Note: 1. Sampled only , not 100% tested.

T ab le 6. Capacitance

(1)

= 25 °C, f = 1 MHz )

System Consi der atio n s

The power switching characteristics of Advance

CMOS EPROMs require careful decoupling of the

devices. The supply current, I

, has three seg-

ments that are of interest to the system designer:

the standby current level, the active current level,

and transient current peaks that are produced by

the falling and rising edges of

E. The magnitude of

this transient current peaks is dependent on the

capacitive and inductive loading of the device at the

output. The associated transient vo ltage peaks can

be suppressed by complying with the two line

output control and by properly select ed decoupling

capacitors. It is recommended that a 0.1µF ceramic

capacitor be used on every device between V

and V

. This should be a high frequency capacitor

of low inherent inductance and should be placed

as close to the device as possible. In addition, a

4.7µF bulk electrolytic capacitor should be used

between V

and V

for every eight devices. The

bulk capacitor should be located near the power

supply connection point. The purpose of the bulk

capacitor is to overcome the voltage drop caused

by the inductive effects of PCB trac es.

4/13

M87C257

Symbol Parameter Test Condition Min Max Unit

Input Leakage Current 0V ≤ V

≤ V

±10 µA

Output Leakage Current 0V ≤ V

OUT

≤ V

±10 µA

Supply Current

E = V

, G = V

OUT

= 0mA, f = 5MHz

30 mA

CC1

Supply Current

(Standby) TTL

E = V

, ASV

= V

, Address Switching 10 mA

E = V

, ASV

= V

, Address Stable 1 mA

CC2

Supply Current (Standby)

CMOS

E ≥ V

– 0.2V, ASV

≥ V

– 0.2V,

Address Switching

6mA

E ≥ V

– 0.2V, ASV

= V

Address Stable

100 µA

Program Current V

= V

100 µA

Input Low Voltage –0.3 0.8 V

(2)

Input High Voltage 2 V

+ 1 V

Output Low Voltage I

= 2.1mA 0.4 V

Output High Voltage I

= –1mA V

– 0.8V V

Notes: 1. V

must be applied simultaneously with or before V

and removed simultaneously or after V

2. Maximum DC voltage on Output is V

+0.5V .

T ab le 7. Read Mode DC Characteristic s

(1)

= 0 to 70°C, –40 to 85°C, –40 to 105°C or –40 to 125°C; V

= 5V ± 5% or 5V ± 10%; V

= V

)

Symbol Alt Parameter

Test

Condition

M87C257

Unit

-45

(3)

-60 -70 -80

Min Max Min Max Min Max Min Max

AVQV

ACC

Address Valid to

Output Valid

E = V

, G = V

45 60 70 80 ns

AVASL

Address Valid to

Address Strobe Low

7777ns

ASHASL

Address Strobe High

to Address Strobe Low

35 35 35 35 ns

ASLAX

Address Strobe Low to

Address Transition

20 20 20 20 ns

ASLGL

LOE

Address Strobe Low to

Output Enable Low

20 20 20 20 ns

ELQV

Chip Enable Low to

Output Valid

G = V

45 60 70 80 ns

GLQV

Output Enable Low to

Output Valid

E = V

25 30 35 40 ns

EHQZ

(2)

Chip Enable High to

Output Hi-Z

G = V

025030030040ns

GHQZ

(2)

Output Enable High to

Output Hi-Z

E = V

025030030040ns

AXQX

Address Transition to

Output Transition

E = V

G = V

0000ns

Notes: 1. V

must be applied simultaneously with or before V

and removed simultaneously or after V

2. Sampled only, n ot 100% tested.

3. In case of 45ns speed see High Speed AC measurement conditions.

T ab le 8A. Read Mode AC Charact eristi cs

(1)

= 0 to 70°C, –40 to 85°C, –40 to 105°C or –40 to 125°C; V

= 5V ± 5% or 5V ± 10%; V

= V

)

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M87C257

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