256K (32K x 8) UV EPROM and OTP EPROM
INTEGRA TE D ADDRE SS LATCH
FA ST ACCESS TIME: 45ns
LOW POWER “CMOS” CONSUMPTION:
– Active Current 30mA
– Standby Current 100µA
PROGRAMMING VOLTAGE: 12.75V
ELECTRONI C S IG NATURE for AUTOM ATED
PROGRAMMING
PROGRAM MING T IM ES of ARO UND 3sec.
(PRESTO II ALGORITHM)
DESCRIP TION
The M87C257 is a high speed 262,144 bit UV
erasable and electrically programmable EPROM.
The M87C257 incorporates latches for all address
inputs to minimize chip count, reduce cost, and
simplify the design of multiplexed bus systems.
The Window Ceramic Frit-Seal Dual-in-Line package has a transparent lid which allows the user to
expose the chip to ultraviolet light to erase the bit
pattern. A new pattern can then be written to the
device by following the programming procedure.
For applications where the content is pr ogrammed
only one time and erasure is not required, the
M87C257 is offered in Plas tic Leaded Chip Carrier ,
package.
ADDRESS LATCHED
28
1
FDIP28W (F)
Figure 1. Logic Diag ra m
V
CC
15
A0-A14
E
M87C257
M87C257
PLCC32 (C)
8
Q0-Q7
G
T able 1. Signal Names
A0 - A14 Address Inputs
Q0 - Q7 Data Outputs
E Chip Enable
G Output Enable
ASV
PP
V
CC
V
SS
June 1996 1/13
Address Strobe / Program Supply
Supply Voltage
Ground
ASV
PP
V
SS
AI00928B
M87C257
Figure 2A. DIP Pin Connecti on s
ASV
PP
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q2
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
M87C257
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AI00929
V
CC
A14
A13
A8
A9
A11
G
A10
E
Q7
Q6
Q5Q1
Q4
Q3V
Figure 2B. LCC Pin Conn ecti ons
PP
CC
A13
DU
32
DU
V
Q3
A14
Q4
25
Q5
A8
A9
A11
NC
G
A10
E
Q7
Q6
AI00930
ASV
A7
A12
1
A6
A5
A4
A3
A2
9
M87C257
A1
A0
NC
Q0
17
Q1
Q2
SS
V
Warning: NC = Not Connected, DU = Dont’t Use.
Tab l e 2. Absolu te Maxi mu m Ratin gs
Symbol Parameter Value Unit
T
A
T
BIAS
T
STG
(2)
V
IO
V
CC
(2)
V
A9
V
PP
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those lis ted in the Table "Absolute Maximum Ratings"
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20 ns. Maximum DC
Ambient Operating Temperature –40 to 125 °C
Temperature Under Bias –50 to 125 °C
Storage Temperature –65 to 150 °C
Input or Output Voltages (except A9) –2 to 7 V
Supply Voltage –2 to 7 V
A9 Voltage –2 to 13.5 V
Program Supply Voltage –2 to 14 V
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specificat ion is not implied. Exposure to Abs olute Maxi mum
Rating conditions for extended periods may affect device reliability . Refer also to the SGS-THOMS O N SURE Program and other
relevant quality documents.
voltage on Output is V
+0.5V with possible ove rshoot to VCC +2V for a period less than 20ns.
CC
DEVICE OPER ATION
The modes of operation of the M87C257 are listed
in the Operating Modes. A single power supply is
required in the read mode. All inputs are T TL levels
except for V
and 12V on A9 for Elect ronic S igna-
PP
ture.
(1)
Read Mode
The M87C257 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (
E) is the power
control and should be used for device selection.
Output Enable (
G) is the output control and should
2/13
T ab le 3. Operating Modes
M87C257
Mode E GA9ASV
Read (Latched Address) V
Read (Applied Address) V
Output Disable V
Program V
Verify V
Program Inhibit V
Standby V
Electronic Signature V
Note: X = VIH or VIL, VID = 12V ± 0.5V
IL
IL
IL
Pulse V
IL
IH
IH
IH
IL
V
IL
V
IL
V
IH
IH
V
IL
V
IH
X X X Hi-Z
V
IL
XVILData Out
XVIHData Out
X X Hi-Z
XVPPData In
XVPPData Out
XVPPHi-Z
V
ID
PP
V
IL
T ab le 4. Electron ic Sig natu r e
Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data
Manufacturer’s Code V
Device Code V
IL
IH
be used to gate data to the output pins, independent of device selection. Assuming that the
addresses are stable (
), the address access time (t
V
IL
delay from
E to output (t
the output after delay of t
G, assuming that E has been low and the ad-
of
AS = VIH) or latched (AS =
ELQV
GLQV
dresses have been stable for at least t
The M87C257 reduces the hardware interface in
multiplexed address-data bus systems. The processor multiplexed bus (AD0-AD7) may be tied to
the M87C257’s address and data pins. No separate address latch is needed because the
M87C257 latches all address inputs when
low.
Standby Mode
The M87C257 has a standby mode which reduces
the active current from 30mA to 100µA (Address
Stable). The M87C257 is placed in the standby
mode by applying a CMOS high signal to the
00100000 20h
10000000 80h
Two Line Output Control
Because EPROMs are usually used in larger mem-
) is equal to the
AVQV
). Data is available at
from the falling edge
AVQV-tGLQV
ory arrays, this product features a 2 line control
function which accommodates the use of multiple
memory connection. The two line control function
allows:
.
a. the lowest possible memory power dissipation,
b. complete assuranc e that output bus cont entio n
will not occur.
For the most efficient use of thes e two control lines,
E should be decoded and used as the primary
AS is
device selecting function, while
G should be made
a common connection to all devices in the array
and connected to the
READ line from the system
control bus. This ensures that all dese lected memory devices are in their low power standby mode
and that the output pins are only active when data
is desired from a particular memory device.
E
input. When in the standby mode, the outputs are
in a high impedance state, independent of the
G
input.
Q0 - Q7
Codes
3/13
M87C257
T ab le 5. AC Measurement Con ditions
High Speed Standard
Input Rise and Fall Times ≤ 10ns ≤ 20ns
Input Pulse Voltages 0 to 3V 0.4V to 2.4V
Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V
Figure 3. AC Test ing Input Outp ut W avefo rm
High Speed
3V
1.5V
0V
Standard
2.4V
0.4V
T ab le 6. Capacitance
Symbol Parameter Test Condition Min Max Unit
C
IN
C
OUT
Note: 1. Sampled only , not 100% tested.
(1)
(TA = 25 °C, f = 1 MHz )
Input Capacitance VIN = 0V 6 pF
Output Capacitance V
2.0V
0.8V
AI01822
Figure 4. AC T est ing Load Circu it
1.3V
1N914
3.3kΩ
DEVICE
UNDER
TEST
CL = 30pF or 100pF
CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance
= 0V 12 pF
OUT
OUT
AI01823
System Consi der atio n s
The power switching characteristics of Advance
CMOS EPROMs require careful decoupling of the
devices. The supply current, I
, has three seg-
CC
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of
E. The magnitude of
this transient current peaks is dependent on the
capacitive and inductive loading of the device at the
output. The associated transient vo ltage peaks can
be suppressed by complying with the two line
4/13
output control and by properly select ed decoupling
capacitors. It is recommended that a 0.1µF ceramic
capacitor be used on every device between V
CC
and VSS. This should be a high frequency capacitor
of low inherent inductance and should be placed
as close to the device as possible. In addition, a
4.7µF bulk electrolytic capacitor should be used
between V
and VSS for every eight devices. The
CC
bulk capacitor should be located near the power
supply connection point. The purpose of the bulk
capacitor is to overcome the voltage drop caused
by the inductive effects of PCB trac es.
M87C257
T ab le 7. Read Mode DC Characteristic s
(1)
(TA = 0 to 70°C, –40 to 85°C, –40 to 105°C or –40 to 125°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
Symbol Parameter Test Condition Min Max Unit
Input Leakage Current 0V ≤ VIN ≤ V
LI
Output Leakage Current 0V ≤ V
Supply Current
Supply Current
(Standby) TTL
E = VIH, ASVPP = VIH, Address Switching 10 mA
E = VIH, ASVPP = VIL, Address Stable 1 mA
OUT
E = VIL, G = VIL,
I
= 0mA, f = 5MHz
OUT
≤ V
CC
CC
I
I
I
CC1
I
LO
CC
E ≥ VCC – 0.2V, ASVPP ≥ VCC – 0.2V,
I
CC2
Supply Current (Standby)
CMOS
Address Switching
E ≥ VCC – 0.2V, ASVPP = VSS,
Address Stable
I
PP
V
V
IH
V
V
Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
Program Current VPP = V
Input Low Voltage –0.3 0.8 V
IL
(2)
Input High Voltage 2 VCC + 1 V
Output Low Voltage IOL = 2.1mA 0.4 V
OL
Output High Voltage IOH = –1mA VCC – 0.8V V
OH
2. Maximum DC voltage on Output is V
+0.5V .
CC
CC
±10 µA
±10 µA
30 mA
6mA
100 µA
100 µA
T ab le 8A. Read Mode AC Charact eristi cs
(1)
(TA = 0 to 70°C, –40 to 85°C, –40 to 105°C or –40 to 125°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
M87C257
-60 -70 -80
Symbol Alt Parameter
Test
Condition
-45
(3)
Min Max Min Max Min Max Min Max
Address Valid to
t
AVQV
t
AVASL
t
ASHASLtLL
t
ASLAX
t
ASLGLtLOE
t
ELQV
t
GLQV
t
EHQZ
t
GHQZ
t
AXQX
Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
t
ACC
Output Valid
Address Valid to
t
AL
Address Strobe Low
Address Strobe High
to Address Strobe Low
Address Strobe Low to
t
LA
Address Transition
Address Strobe Low to
Output Enable Low
Chip Enable Low to
t
CE
Output Valid
Output Enable Low to
t
OE
Output Valid
(2)
(2)
2. Sampled only, n ot 100% tested.
3. In case of 45ns speed see High Speed AC measurement conditions.
Chip Enable High to
t
DF
Output Hi-Z
Output Enable High to
t
DF
Output Hi-Z
Address Transition to
t
OH
Output Transition
E = VIL, G = V
G = V
IL
E = V
IL
G = V
IL
E = V
IL
E = VIL,
G = V
IL
IL
45 60 70 80 ns
7777ns
35 35 35 35 ns
20 20 20 20 ns
20 20 20 20 ns
45 60 70 80 ns
25 30 35 40 ns
025030030040ns
025030030040ns
0000ns
Unit
5/13
M87C257
T ab le 8B. Read Mode AC Charact eristi cs
(1)
(TA = 0 to 70°C, –40 to 85°C, –40 to 105°C or –40 to 125°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
Symbol Alt Parameter
Test
Condition
-90 -10 -12 -15/-20
Min Max Min Max Min Max Min Max
t
AVQV
t
AVASL
t
ASHASLtLL
t
ASLAX
t
ASLGLtLOE
t
ELQV
t
GLQV
(2)
t
EHQZ
(2)
t
GHQZ
t
AXQX
Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Sampled only, n ot 100% tested.
Address Valid to
t
ACC
Output Valid
Address Valid to
t
AL
Address Strobe Low
Address Strobe High
to Address Strobe Low
Address Strobe Low to
t
LA
Address Transition
Address Strobe Low
to Output Enable Low
Chip Enable Low to
t
CE
Output Valid
Output Enable Low to
t
OE
Output Valid
Chip Enable High to
t
DF
Output Hi-Z
Output Enable High to
t
DF
Output Hi-Z
Address Transition to
t
OH
Output Transition
E = VIL, G = V
G = V
IL
E = V
IL
G = V
IL
E = V
IL
E = VIL, G = V
IL
90 100 120 150 ns
7777ns
35 35 35 35 ns
20 20 20 20 ns
20 20 20 20 ns
90 100 120 150 ns
40 40 50 60 ns
040030040040ns
040030040040ns
0000ns
IL
M87C257
Unit
Figure 5. Read Mode AC Wavefo r ms
A0-A14
ASV
PP
E
G
Q0-Q7
VALID
tAVASL
tASHASL
tAVQV
tASLGL
tGLQV
tELQV
tASLAX
tAXQX
tEHQZ
tGHQZ
Hi-Z
DATA OUT
AI00931
6/13
M87C257
T ab le 9. Programming Mode DC Charact erist ics
(1)
(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Symbol Parameter Test Condition Min Max Unit
I
LI
I
CC
I
PP
V
V
V
OL
V
OH
V
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
T ab le 10. Programmi ng Mode AC Ch aracterist ics
Input Leakage Current VIL ≤ VIN ≤ V
IH
Supply Current 50 mA
Program Current E = V
Input Low Voltage –0.3 0.8 V
IL
Input High Voltage 2 VCC + 0.5 V
IH
IL
Output Low Voltage IOL = 2.1mA 0.4 V
Output High Voltage TTL IOH = –1mA VCC -0.8V V
A9 Voltage 11.5 12.5 V
ID
(1)
±10 µA
50 mA
(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Symbol Alt Parameter Test Condition Min Max Unit
t
AVEL
t
QVEL
t
VPHEL
t
VCHEL
t
ELEH
t
EHQX
t
QXGL
t
GLQV
t
GHQZ
t
GHAX
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V
t
t
t
VPS
t
VCS
t
t
t
OES
t
t
DFP
t
Address Valid to Chip Enable Low 2 µs
AS
Input Valid to Chip Enable Low 2 µs
DS
VPP High to Chip Enable Low 2 µs
VCC High to Chip Enable Low 2 µs
Chip Enable Program Pulse Width 95 105 µs
PW
Chip Enable High to Input Transition 2 µs
DH
Input Transition to Output Enable Low 2 µs
Output Enable Low to Output Valid 100 ns
OE
Output Enable High to Output Hi-Z 0 130 ns
Output Enable High to Address Transition 0 ns
AH
PP
Programming
When delivered (and after each erasure for UV
EPROM), all bits of the M87C257 are in the "1"
state. Data is introduced by selectively programming "0"s into the desired bit locations. Although
only "0"s will be programmed, both "1"s and "0"s
can be present in the data word. The only way to
change a "0" to a "1" is by die exposition to ultraviolet light (UV EPROM). The M87C257 is in the
programming mode when V
is at V
and E is pulsed to VIL. The data to be
IH
input is at 12.75V , G
PP
programmed is applied to 8 bits in parallel to the
data output pins. The levels required for the address and data inputs are TTL. V
is specified to
CC
be 6.25 V ± 0.25 V.
7/13
M87C257
Figure 6. Programming and Verify Modes AC Waveforms
A0-A14
tAVEL
Q0-Q7
ASV
V
CC
E
G
PP
DATA IN DATA OUT
tQVEL
tVPHEL
tVCHEL
tELEH
Figure 7. Progr a m min g Flow ch ar t
VCC = 6.25V, VPP = 12.75V
n = 0
E = 100µs Pulse
NO
NO
VERIFY
YES
Last
NO
Addr
YES
CHECK ALL BYTES
1st: VCC = 6V
2nd: VCC = 4.2V
++ Addr
YES
++n
= 25
FAIL
VALID
tEHQX
tGLQV
tQXGL
PROGRAM VERIFY
PRESTO II Program ming Algorit hm
PRESTO II Programming Algorithm allows to program the whole array with a guaranteed margin, in
a typical time of 3.5 seconds. Programming with
PRESTO II involves the application of a sequence
of 100µs program pulses to each byte until a correct
verify occurs (see Figure 7). During programming
and verify operation, a MARGIN MODE circuit is
automatically activated in order to guarantee that
each cell is programmed with enough margin. No
overprogram pulse is applied since the verify in
MARGIN MODE provides necessary margin to
each programmed cell.
Program Inhibit
Programming of multiple M87C257s in parallel wit h
different d ata is also easily accomplished. Except
E, all like inputs including G of the parallel
for
M87C257 may be comm on. A TTL low level pulse
applied to a M87C257’s
will program that M87C257. A high level
inhibits the other M87C257s from being programmed.
Program Verify
AI00760B
A verify (read) should be performed on the programmed bits to deter mine that they were c orrectly
programmed. The verify is accomplished with
, E at VIH, VPP at 12.75V and VCC at 6.25V.
V
IL
tGHQZ
tGHAX
AI00557
E input, with VPP at 12.75V ,
E input
G at
8/13
M87C257
Electronic Signature
The Electronic Signature (ES) mode allows the
reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically matc h the devic e to be programm ed
with its corres ponding programming algorithm. The
ES mode is functional in the 25°C ± 5°C ambient
temperature ran ge that is required wh en programming the M87C257.
To activate the ES mode, the programming equipment must force 1 1.5V to 12.5V on addres s line A9
of the M87C257, with V
= VPP = 5V . T wo identifier
CC
bytes may then be sequenced from the device
outputs by toggling address line A0 from V
All other address lines must be held at V
Electronic Si gnature mode. B yte 0 (A0= V
sents the manufacturer code and byte 1 (A0=V
the device identifier c ode. When A9 = V
to VIH.
IL
during
IL
) repre-
IL
, AS need
ID
IH
not be toggled to latch eac h identif ier addr ess. For
the SGS-THOMSON M87C257, these two identifier bytes are given in Table 4 and can be read-out
on outputs Q0 to Q7.
ERASURE OPERATION (applies for U V EPROM)
The erasure characterist ics of the M87C257 is such
that erasure begins when the cells are exposed to
light with wavelengths shorter than approximately
4000 Å. It should be noted that sunlight and some
type of fluorescent lamps have wave lengths in th e
3000-4000 Å range. Research shows that constant
exposure to room level fluorescent lighting could
erase a typical M87C257 in about 3 years, while it
would take approximately 1 week to cause erasure
when exposed to direct sunlight. If the M87C257 is
to be exposed to these types of lighting conditions
for extended periods of time, it is suggested that
opaque labels be put over the M87C257 window to
prevent unintentional erasure. The recommended
erasure procedure for the M87C257 is exposure to
short wave ultraviolet light which has wavelength
2537Å. The integrated dose (i.e. UV intensity x
)
exposure time) for erasure should be a minimum
of 15 W-sec/cm
age is approximately 15 to 20 minutes using an
ultraviolet lamp with 12000 µW/cm
2
. The erasure time with this dos-
2
power rating.
The M87C257 should be placed within 2.5 cm (1
inch) of the lamp tubes during the erasure. Some
lamps have a filter on their tubes which should be
removed before erasure.
9/13
M87C257
ORDERI NG INFO RM ATION SCHEME
Example: M87C257 -70 X C 1 X
Speed
(1)
-45
-60 60 ns
-70 70 ns
-80 80 ns
-90 90 ns
-10 100 ns
-12 120 ns
-15 150 ns
-20 200 ns
Note: 1. High Speed, see AC Characteristics section for furth er info rmation.
45 ns
VCC Tolerance
X ± 5%
blank ± 10%
Package
F FDIP28W
C PLCC32
Temperature Range
1 0 to 70 °C
6 –40 to 85 °C
7 –40 to 105 °C
3 –40 to 125 °C
Option
X Additional
Burn-in
TR Tape & Reel
Packing
For a list of available options (Speed, VCC T olerance, Package, etc ...) refer to the current Memory Shor tform
catalogue.
For further information on any aspect of this device, please contact the SGS-THOMSON Sales Office
nearest to you.
10/13
FDIP28W - 28 pin Ceramic Frit-seal DIP, with window
M87C257
Symb
Typ Min Max Typ M in Max
A 5.71 0.225
A1 0.50 1.78 0.020 0.070
A2 3.90 5.08 0.154 0.200
B 0.40 0.55 0.016 0.022
B1 1.17 1.42 0.046 0.056
C 0.22 0.31 0.009 0.012
D 38.10 1.500
E 15.40 15.80 0.606 0.622
E1 13.05 13.36 0.514 0.526
e1 2.54 – – 0.100 – –
e3 33.02 – – 1.300 – –
eA 16.17 18.32 0.637 0.721
L 3.18 4.10 0.125 0.161
S 1.52 2.49 0.060 0.098
∅ 7.11 – – 0.280 – –
α 4° 15° 4° 15°
N28 28
FDIP28W
mm inches
Drawing is not to scale
B1 B e1
e3
D
S
N
∅
1
A2
A1AL
Cα
eA
E1 E
FDIPW-a
11/13
M87C257
PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular
Symb
Typ Min Max Typ Min M ax
A 2.54 3.56 0.100 0.140
A1 1.52 2.41 0.060 0.095
B 0.33 0.53 0.013 0.021
B1 0.66 0.81 0.026 0.032
D 12.32 12.57 0.485 0.495
D1 11.35 11.56 0.447 0.455
D2 9.91 10.92 0.390 0.430
E 14.86 15.11 0.585 0.595
E1 13.89 14.10 0.547 0.555
E2 12.45 13.46 0.490 0.530
e 1.27 – – 0.050 – –
N32 32
Nd 7 7
Ne 9 9
CP 0.10 0.004
PLCC32
mm inches
Drawing is not to scale
12/13
Ne
PLCC
D
D1
1 N
Nd
E1 E
D2/E2
A1
B1
e
B
A
CP
M87C257
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not auth orized for use as critical components in life support devices or s ystems wit hout ex press
written approval of SGS-THOMSON Microelectronics.
© 1996 SGS-THOMSON Microelectronics - All Rights Reserved
Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malays ia - Malta - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
SGS-THOMSON Microelectronics GROUP OF COMP ANIES
13/13
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