ST M74HCT74 User Manual
M74HCT74
DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR
■HIGH SPEED :
fMAX = 48MHz (TYP.) at VCC = 4.5V
■LOW POWER DISSIPATION: ICC =2μA(MAX.) at TA=25°C
■COMPATIBLE WITH TTL OUTPUTS : VIH = 2V (MIN.) VIL = 0.8V (MAX)
■BALANCED PROPAGATION DELAYS: tPLH tPHL
■SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN)
■PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 74
DESCRIPTION
The M74HCT74 is an high speed CMOS DUAL D TYPE FLIP FLOP WITH CLEAR fabricated with silicon gate C2MOS technology.
A signal on the D INPUT (nD) is transferred on the Q OUTPUT during the positive going transition of the clock pulse. CLEAR (CLR) and PRESET (PR) are independent of the clock and accomplished by a low on the appropriate input.
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DIP |
SOP |
TSSOP |
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ORDER CODES |
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PACKAGE |
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TUBE |
T & R |
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DIP |
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M74HCT74B1R |
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SOP |
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M74HCT74M1R |
M74HCT74RM13TR |
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TSSOP |
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M74HCT74TTR |
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The M74HCT74 is designed to directly interface HSC2MOS systems with TTL and NMOS components.
All inputs are equipped with protection circuits against static discharge and transient excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
August 2001 |
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M74HCT74
INPUT AND OUTPUT EQUIVALENT CIRCUIT |
PIN DESCRIPTION |
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PIN No |
SYMBOL |
NAME AND FUNCTION |
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1,13 |
1CLR, 2CLR |
Asynchronous Reset - |
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Direct Input |
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2, 12 |
1D, 2D |
Data Inputs |
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Clock Input |
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3, 11 |
1CK, 2CK |
(LOW-to-HIGH, |
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Edge-Triggered) |
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4, 10 |
1PR, 2PR |
Asynchronous Set - Direct |
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Input |
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5, 9 |
1Q, 2Q |
True Flip-Flop Outputs |
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6, 8 |
1Q, 2Q |
Complement Flip-Flop |
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Outputs |
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7 |
GND |
Ground (0V) |
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14 |
Vcc |
Positive Supply Voltage |
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TRUTH TABLE |
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INPUTS |
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OUTPUTS |
FUNCTION |
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CLR |
PR |
D |
CK |
Q |
Q |
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L |
H |
X |
X |
L |
H |
CLEAR |
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H |
L |
X |
X |
H |
L |
PRESET |
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L |
L |
X |
X |
H |
H |
---- |
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H |
H |
L |
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L |
H |
---- |
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H |
H |
H |
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H |
L |
---- |
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H |
H |
X |
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Qn |
Qn |
NO CHANGE |
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X : Don’t Care |
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LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
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M74HCT74 |
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ABSOLUTE MAXIMUM RATINGS |
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Symbol |
Parameter |
Value |
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Unit |
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VCC |
Supply Voltage |
-0.5 to +7 |
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V |
VI |
DC Input Voltage |
-0.5 to VCC + 0.5 |
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VO |
DC Output Voltage |
-0.5 to VCC + 0.5 |
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V |
IIK |
DC Input Diode Current |
± 20 |
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mA |
IOK |
DC Output Diode Current |
± 20 |
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mA |
IO |
DC Output Current |
± 25 |
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mA |
ICC or IGND |
DC VCC or Ground Current |
± 50 |
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mA |
PD |
Power Dissipation |
500(*) |
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mW |
Tstg |
Storage Temperature |
-65 to +150 |
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°C |
TL |
Lead Temperature (10 sec) |
300 |
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°C |
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
RECOMMENDED OPERATING CONDITIONS
Symbol |
Parameter |
Value |
Unit |
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VCC |
Supply Voltage |
4.5 to 5.5 |
V |
VI |
Input Voltage |
0 to VCC |
V |
VO |
Output Voltage |
0 to VCC |
V |
Top |
Operating Temperature |
-55 to 125 |
°C |
tr, tf |
Input Rise and Fall Time (VCC = 4.5 to 5.5V) |
0 to 500 |
ns |
DC SPECIFICATIONS
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Test Condition |
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Value |
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Symbol |
Parameter |
VCC |
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TA = 25°C |
-40 to 85°C |
-55 to 125°C |
Unit |
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(V) |
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Min. |
Typ. |
Max. |
Min. |
Max. |
Min. |
Max. |
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VIH |
High Level Input |
4.5 |
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2.0 |
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2.0 |
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2.0 |
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V |
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Voltage |
to |
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5.5 |
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VIL |
Low Level Input |
4.5 |
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0.8 |
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0.8 |
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0.8 |
V |
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Voltage |
to |
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5.5 |
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VOH |
High Level Output |
4.5 |
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IO=-20 μA |
4.4 |
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4.5 |
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4.4 |
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4.4 |
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V |
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Voltage |
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IO=-4.0 mA |
4.18 |
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4.31 |
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4.13 |
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4.10 |
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VOL |
Low Level Output |
4.5 |
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IO=20 μA |
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0.0 |
0.1 |
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0.1 |
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0.1 |
V |
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Voltage |
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IO=4.0 mA |
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0.17 |
0.26 |
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0.33 |
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0.40 |
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II |
Input Leakage |
5.5 |
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VI = VCC or GND |
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± 0.1 |
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± 1 |
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± 1 |
μA |
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Current |
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ICC |
Quiescent Supply |
5.5 |
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VI = VCC or GND |
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2 |
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20 |
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40 |
μA |
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Current |
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ICC |
Additional Worst |
5.5 |
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Per Input pin |
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2.0 |
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2.9 |
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3.0 |
mA |
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Case Supply |
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VI = 0.5V or |
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Current |
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VI = 2.4V |
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Other Inputs at |
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VCC or GND |
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IO = 0 |
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3/10 |
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