ST M74HCT652 User Manual

M74HCT652

OCTAL BUS TRANSCEIVER/REGISTER WITH 3 STATE OUTPUTS

■HIGH SPEED:

fMAX = 55 MHz (TYP.) at VCC = 4.5V

■LOW POWER DISSIPATION: ICC = 4μA(MAX.) at TA=25°C

■COMPATIBLE WITH TTL OUTPUTS : VIH = 2V (MIN.) VIL = 0.8V (MAX)

■SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 6mA (MIN)

■BALANCED PROPAGATION DELAYS: tPLH tPHL

■PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 652

DESCRIPTION

The 74HCT652 is an advanced high-speed CMOS OCTAL BUS TRANSCEIVER AND REGISTER (3-STATE) fabricated with silicon gate C2MOS technology.

This device consists of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal storage registers. Enable GAB and GBA are provided to control the transceiver functions. Select AB(SAB) and select BA(SBA) control pins are provided to select whether real-time or stored data is transferred. A low input level selects real-time data, and a high selects stored data.

Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transition at the appropriate clock pins (CLOCK AB or CLOCK

DIP	SOP	TSSOP

ORDER CODES
PACKAGE	TUBE	T & R

DIP	M74HCT652B1R
SOP	M74HCT652M1R	M74HCT652RM13TR

TSSOP		M74HCT652TTR

BA) regardless of the select or enable control pins. When select AB and select BA are in the real time transfer mode, it is also possible to store data without using the internal D type flip-flops by simultaneously enabling GAB and GBA. In this configuration each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines will remain at its last state.

All inputs are equipped with protection circuits against static discharge and transient excess voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

April 2003

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M74HCT652

INPUT AND OUTPUT EQUIVALENT CIRCUIT	PIN DESCRIPTION
	PIN No	SYMBOL	NAME AND FUNCTION
	1	CAB	A to B Clock Input (LOW
			to HIGH, Edge-Triggered)
	2	SAB	Select A to B Source Input
	3	GAB	Direction Control Input
	4, 5, 6, 7, 8,	A1 to A8	A Data Inputs/Outputs
	9, 10, 11
	20, 19, 18,	B1 to B8	B Data Inputs/Outputs
	17, 16, 15,
	14, 13
	21	GBA	Output Enable Input
			(Active LOW)
	22	SBA	Select B to A Source Input
	23	CBA	B to A Clock Input (LOW
			to HIGH, Edge Triggered)
	12	GND	Ground (0V)
	24	VCC	Positive Supply Voltage

TRUTH TABLE

GAB

GBA

CAB

CBA

SAB

SBA

FUNCTION

INPUTS

Both the A bus and the B bus are inputs

The Output functions of the A and B bus are disabled

Both the A and B bus are used for inputs to the internal

INPUTS

flip-flops. Data at the bus will be stored on low to high

transition of the clock inputs.

OUTPUTS

INPUTS

The A bus are outputs and the B bus are inputs

The data at the B bus are displayed at the A bus

The data at the B bus are displayed at the A bus. The

data of the B bus are stored to internal flip-flop on low

to high transition of the clock pulse

The data stored to the internal flip-flop are displayed at

the A bus.

The data at the B bus are stored to the internal flip-flop

on low to high transition of the clock pulse. The states

of the internal flip-flops output directly to the A bus.

INPUTS

OUTPUTS

The A bus are inputs and the B bus are outputs.

The data at the A bus are displayed at the B bus

The data at the A bus are displayed at the B bus. The

data of the A bus are stored to the internal flip-flop on

low to high transition of the clock pulse.

The data stored to the internal flip-flops are displayed

at the B bus

The data at the A bus are stored to the internal flip-flop

on low to high transition of the clock pulse. The states

of the internal flip-flops output directly to the B bus.

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M74HCT652

GAB GBA CAB CBA SAB SBA

FUNCTION

OUTPUTS OUTPUTS

The data stored to the internal flip-flops are displayed

at the A and B bus respectively.

The output at the A bus are displayed at the B bus, the

output at the B bus are displayed at the A bus respec-

tively

X : Don’t Care

Z : High Impedance

Qn : The data stored to the internal flip-flops by most recent low to high transition of the clock inputs

* : The data at the A and B bus will be stored to the internal flip-flops on every low to high transition of the clock inputs.

LOGIC DIAGRAM

TIMING CHART

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M74HCT652

ABSOLUTE MAXIMUM RATINGS

Symbol	Parameter	Value	Unit

VCC	Supply Voltage	-0.5 to +7	V
VI	DC Input Voltage	-0.5 to VCC + 0.5	V
VO	DC Output Voltage	-0.5 to VCC + 0.5	V
IIK	DC Input Diode Current	± 20	mA
IOK	DC Output Diode Current	± 20	mA
IO	DC Output Current	± 35	mA
ICC or IGND	DC VCC or Ground Current	± 70	mA
PD	Power Dissipation	500(*)	mW
Tstg	Storage Temperature	-65 to +150	°C
TL	Lead Temperature (10 sec)	300	°C

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied

(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter	Value	Unit

VCC	Supply Voltage	4.5 to 5.5	V
VI	Input Voltage	0 to VCC	V
VO	Output Voltage	0 to VCC	V
Top	Operating Temperature	-55 to 125	°C
tr, tf	Input Rise and Fall Time (VCC = 4.5 to 5.5V)	0 to 500	ns

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M74HCT652

DC SPECIFICATIONS

Test Condition

Value

Symbol

Parameter

VCC

TA = 25°C

-40 to 85°C

-55 to 125°C

Unit

(V)

Min.

Typ.

Max.

Min.

Max.

Min.

Max.

VIH

High Level Input

4.5

2.0

Voltage

5.5

VIL

Low Level Input

4.5

Voltage

0.8

5.5

VOH

High Level Output

4.5

IO=-20 μA

4.4

4.5

4.4

Voltage

IO=-6.0 mA

4.18

4.31

4.13

4.10

VOL

Low Level Output

4.5

IO=20 μA

0.0

0.1

Voltage

IO=6.0 mA

0.17

0.26

0.33

0.40

Input Leakage

5.5

VI = VCC or GND

± 0.1

± 1

μA

Current

IOZ

High Impedance

5.5

VI = VIH or VIL

± 0.5

± 5

± 10

μA

Output Leakage

VO = VCC or GND

Current

ICC

Quiescent Supply

5.5

VI = VCC or GND

μA

Current

ICC

Additional Worst

5.5

Per Input pin

2.0

2.9

3.0

Case Supply

VI = 0.5V or

Current

VI = 2.4V

Other Inputs at

VCC or GND

IO = 0

(*) Applicable Only to GAB, GBA, CAB, CBA, SAB, SBA Input

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