ST M74HCT640 User Manual

M74HCT640

OCTAL BUS TRANSCEIVER WITH 3 STATE OUTPUTS (INVERTED)

HIGH SPEED:

tPD = 13ns (TYP.) at VCC = 4.5V

LOW POWER DISSIPATION: ICC = 4μA(MAX.) at TA=25°C

COMPATIBLE WITH TTL OUTPUTS : VIH = 2V (MIN.) VIL = 0.8V (MAX)

SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 6mA (MIN)

BALANCED PROPAGATION DELAYS: tPLH tPHL

PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 640

DESCRIPTION

The M74HCT640 is an advanced high-speed CMOS OCTAL BUS TRANSCEIVER (3-STATE) fabricated with silicon gate C2MOS technology.

This IC is intended for two-way asynchronous communication between data buses, and the direction of data transmission is determined by DIR input. The enable input G can be used to disable the device so that the buses are effectively isolated.

DIP

SOP

TSSOP

 

 

ORDER CODES

 

PACKAGE

 

TUBE

T & R

 

 

 

 

DIP

 

M74HCT640B1R

 

 

 

 

 

SOP

 

M74HCT640M1R

M74HCT640RM13TR

 

 

 

 

TSSOP

 

 

M74HCT640TTR

 

 

 

 

All inputs are equipped with protection circuits against static discharge and transient excess voltage.

All floating bus terminals during High Z State must be held HIGH or LOW.

PIN CONNECTION AND IEC LOGIC SYMBOLS

August 2001

1/11

ST M74HCT640 User Manual

M74HCT640

INPUT AND OUTPUT EQUIVALENT CIRCUIT

PIN DESCRIPTION

 

 

PIN No

SYMBOL

NAME AND FUNCTION

 

1

DIR

Directional Control

 

2, 3, 4, 5, 6,

A1 to A8

Data Inputs/Outputs

 

7, 8, 9

 

 

 

18, 17, 16,

B1 to B8

Data Inputs/Outputs

 

15, 14, 13,

 

 

 

12, 11

 

 

 

19

G

Output Enable Input

 

10

GND

Ground (0V)

 

20

VCC

Positive Supply Voltage

TRUTH TABLE

 

 

INPUTS

 

 

FUNCTION

OUTPUT

 

 

 

 

 

 

 

 

 

G

 

DIR

A BUS

 

B BUS

 

 

 

 

 

 

 

 

 

 

 

 

L

 

L

OUTPUT

 

INPUT

A =

B

 

 

 

 

 

 

 

 

 

 

L

 

H

INPUT

 

OUTPUT

B =

A

 

 

 

 

 

 

 

 

 

 

H

 

X

Z

 

Z

Z

 

 

 

 

 

 

 

 

 

 

 

X : Don’t Care

Z : High Impedance

LOGIC DIAGRAM

This logic diagram has not be used to estimate propagation delays

2/11

M74HCT640

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Value

Unit

 

 

 

 

VCC

Supply Voltage

-0.5 to +7

V

VI

DC Input Voltage

-0.5 to VCC + 0.5

V

VO

DC Output Voltage

-0.5 to VCC + 0.5

V

IIK

DC Input Diode Current

± 20

mA

IOK

DC Output Diode Current

± 20

mA

IO

DC Output Current

± 35

mA

ICC or IGND

DC VCC or Ground Current

± 70

mA

PD

Power Dissipation

500(*)

mW

Tstg

Storage Temperature

-65 to +150

°C

TL

Lead Temperature (10 sec)

300

°C

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied

(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Value

Unit

 

 

 

 

VCC

Supply Voltage

4.5 to 5.5

V

VI

Input Voltage

0 to VCC

V

VO

Output Voltage

0 to VCC

V

Top

Operating Temperature

-55 to 125

°C

tr, tf

Input Rise and Fall Time (VCC = 4.5 to 5.5V)

0 to 500

ns

3/11

M74HCT640

DC SPECIFICATIONS

 

 

 

Test Condition

 

 

 

 

Value

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

Parameter

VCC

 

 

 

TA = 25°C

-40 to 85°C

-55 to 125°C

Unit

 

 

(V)

 

 

Min.

Typ.

Max.

Min.

Max.

Min.

Max.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VIH

High Level Input

4.5

 

 

2.0

 

 

 

2.0

 

2.0

 

V

 

Voltage

to

 

 

 

 

 

 

 

 

 

5.5

 

 

 

 

 

 

 

 

 

 

 

VIL

Low Level Input

4.5

 

 

 

 

 

0.8

 

0.8

 

0.8

V

 

Voltage

to

 

 

 

 

 

 

 

 

 

5.5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VOH

High Level Output

4.5

 

IO=-20 μA

4.4

 

4.5

 

4.4

 

4.4

 

V

 

Voltage

 

 

 

 

 

 

 

 

 

 

 

 

IO=-6.0 mA

4.18

 

4.31

 

4.13

 

4.10

 

 

 

 

 

 

 

 

 

 

VOL

Low Level Output

4.5

 

IO=20 μA

 

 

0.0

0.1

 

0.1

 

0.1

V

 

Voltage

 

 

 

 

 

 

 

 

 

 

 

 

IO=6.0 mA

 

 

0.17

0.26

 

0.33

 

0.40

 

 

 

 

 

 

 

 

 

II

Input Leakage

5.5

 

VI = VCC or GND

 

 

 

± 0.1

 

± 1

 

± 1

μA

 

Current

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IOZ

High Impedance

5.5

 

VI = VIH or VIL

 

 

 

± 0.5

 

± 5

 

± 10

μA

 

Output Leakage

 

VO = VCC or GND

 

 

 

 

 

 

Current

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ICC

Quiescent Supply

5.5

 

VI = VCC or GND

 

 

 

4

 

40

 

80

μA

 

Current

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ICC

Additional Worst

5.5

 

Per Input pin

 

 

 

2.0

 

2.9

 

3.0

mA

 

Case Supply

 

 

VI = 0.5V or

 

 

 

 

 

 

 

 

 

 

Current

 

 

VI = 2.4V

 

 

 

 

 

 

 

 

 

 

 

 

 

Other Inputs at

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC or GND

 

 

 

 

 

 

 

 

 

 

 

 

 

IO = 0

 

 

 

 

 

 

 

 

 

4/11

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