ST M74HCT573 User Manual

M74HCT573

OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING

■HIGH SPEED:

tPD = 21ns (TYP.) at VCC = 4.5V

■LOW POWER DISSIPATION: ICC = 4μA(MAX.) at TA=25°C

■COMPATIBLE WITH TTL OUTPUTS : VIH = 2V (MIN.) VIL = 0.8V (MAX)

■BALANCED PROPAGATION DELAYS: tPLH tPHL

■SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 6mA (MIN)

■PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573

DESCRIPTION

The M74HCT573 is an high speed CMOS OCTAL LATCH WITH 3-STATE OUTPUTS fabricated with silicon gate C2MOS technology.

This 8-BIT D-Type latches is controlled by a latch enable input (LE) and output enable input (OE). While the LE input is held at a high level, the Q outputs will follow the data input precisely. When the LE is taken low, the Q outputs will be latched precisely at the logic level of D input data.

While the OE input is at low level, the eight outputs will be in a normal logic state (high or low logic level) and while OE is at high level the outputs will be in a high impedance state.

DIP		SOP	TSSOP
ORDER CODES
PACKAGE		TUBE	T & R
DIP		M74HCT573B1R
SOP		M74HCT573M1R	M74HCT573RM13TR
TSSOP			M74HCT573TTR

The 3-State output configuration and the wide choice of outline make bus organized system simple.

The M74HCT573 is designed to directly interface HSC2MOS systems with TTL and NMOS components.

All inputs are equipped with protection circuits against static discharge and transient excess voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

July 2001

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M74HCT573

INPUT AND OUTPUT EQUIVALENT CIRCUIT	PIN DESCRIPTION
	PIN No	SYMBOL	NAME AND FUNCTION
	1	OE	3 State Output Enable
			Input (Active LOW)
	2, 3, 4, 5, 6,	D0 to D7	Data Inputs
	7, 8, 9
	12, 13, 14,	Q0 to Q7	3 State Latch Outputs
	15, 16, 17,
	18, 19
	11	LE	Latch Enable Input
	10	GND	Ground (0V)
	20	VCC	Positive Supply Voltage

TRUTH TABLE

			INPUTS		OUTPUTS
	OE		LE	D	Q
	H		X	X	Z
	L		L	X	NO CHANGE (*)
	L		H	L	L
	L		H	H	H
X: Don’t Care
Z: High Impedance

(*): Q Outputs are latched at the time when the LE input is taken low logic level.

LOGIC DIAGRAM

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M74HCT573

ABSOLUTE MAXIMUM RATINGS

Symbol	Parameter	Value	Unit
VCC	Supply Voltage	-0.5 to +7	V
VI	DC Input Voltage	-0.5 to VCC + 0.5	V
VO	DC Output Voltage	-0.5 to VCC + 0.5	V
IIK	DC Input Diode Current	± 20	mA
IOK	DC Output Diode Current	± 20	mA
IO	DC Output Current	± 35	mA
ICC or IGND	DC VCC or Ground Current	± 70	mA
PD	Power Dissipation	500(*)	mW
Tstg	Storage Temperature	-65 to +150	°C
TL	Lead Temperature (10 sec)	300	°C

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied

(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter	Value	Unit
VCC	Supply Voltage	4.5 to 5.5	V
VI	Input Voltage	0 to VCC	V
VO	Output Voltage	0 to VCC	V
Top	Operating Temperature	-55 to 125	°C
tr, tf	Input Rise and Fall Time (VCC = 4.5 to 5.5V)	0 to 500	ns

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M74HCT573

DC SPECIFICATIONS

Test Condition

Value

Symbol

Parameter

VCC

TA = 25°C

-40 to 85°C

-55 to 125°C

Unit

(V)

Min.

Typ.

Max.

Min.

Max.

Min.

Max.

VIH

High Level Input

4.5

2.0

2.0

2.0

V

Voltage

to

5.5

VIL

Low Level Input

4.5

0.8

0.8

0.8

V

Voltage

to

5.5

VOH

High Level Output

4.5

IO=-20 μA

4.4

4.5

4.4

4.4

V

Voltage

IO=-6.0 mA

4.18

4.31

4.13

4.10

VOL

Low Level Output

4.5

IO=20 μA

0.0

0.1

0.1

0.1

V

Voltage

IO=6.0 mA

0.17

0.26

0.33

0.40

II

Input Leakage

5.5

VI = VCC or GND

± 0.1

± 1

± 1

μA

Current

IOZ

High Impedance

5.5

VI = VIH or VIL

± 0.5

± 5

± 10

μA

Output Leakage

VO = VCC or GND

Current

ICC

Quiescent Supply

5.5

VI = VCC or GND

4

40

80

μA

Current

ICC

Additional Worst

5.5

Per Input pin

2.0

2.9

3.0

mA

Case Supply

VI = 0.5V or

Current

VI = 2.4V

Other Inputs at

VCC or GND

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)

			Test Condition							Value
Symbol	Parameter	VCC		CL		TA = 25°C				-40 to 85°C		-55 to 125°C		Unit
		(V)		(pF)		Min.	Typ.	Max.		Min.	Max.	Min.	Max.
tTLH tTHL	Output Transition	4.5		50			7		12		15		18	ns
	Time
tPLH tPHL	Propagation Delay	4.5		50			21		33		41		50	ns
	Time (LE - Q,Q)	4.5		150			25		39		49		59
tPLH tPHL	Propagation Delay	4.5		50			19		30		38		45	ns
	Time (D - Q,Q)	4.5		150			23		36		45		54
tPZL tPZH	Output Enable	4.5		50	RL = 1 KΩ		19		30		38		45	ns
	Time	4.5		150			23		36		45		54
tPLZ tPHZ	Output Disable	4.5		50	RL = 1 KΩ		18		25		31		38	ns
	Time
tW(L)	Minimum Pulse	4.5		50			7		15		19		22	ns
tW(H)	Width (LE)
ts	Minimum Set-Up	4.5		50			4		10		13		15	ns
	Time
th	Minimum Hold	4.5		50					5		5		5	ns
	Time

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