M74HCT373
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING
■HIGH SPEED:
tPD = 19ns (TYP.) at VCC = 4.5V
■LOW POWER DISSIPATION: ICC = 4μA(MAX.) at TA=25°C
■COMPATIBLE WITH TTL OUTPUTS : VIH = 2V (MIN.) VIL = 0.8V (MAX)
■SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 6mA (MIN)
■BALANCED PROPAGATION DELAYS: tPLH tPHL
■PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373
DESCRIPTION
The M74HCT373 is an high speed CMOS OCTAL LATCH WITH 3-STATE OUTPUTS fabricated with sub-micron silicon gate C2MOS technology. This 8-BIT D-Type latches is controlled by a latch enable input (LE) and output enable input (OE).
While the LE input is held at a high level, the Q outputs will follow the data input. When the LE is taken low, the Q outputs will be latched at the logic level of D input data.
While the OE input is at low level, the eight outputs will be in a normal logic state (high or low logic
DIP |
SOP |
TSSOP |
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ORDER CODES |
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PACKAGE |
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TUBE |
T & R |
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DIP |
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M74HCT373B1R |
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SOP |
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M74HCT373M1R |
M74HCT373RM13TR |
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TSSOP |
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M74HCT373TTR |
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level) and when OE is in high level the outputs will be in a high impedance state.
The 3-State output configuration and the wide choice of outline make bus organized system simple.
All inputs are equipped with protection circuits against static discharge and transient excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
August 2001 |
1/11 |
M74HCT373
INPUT AND OUTPUT EQUIVALENT CIRCUIT |
PIN DESCRIPTION |
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PIN No |
SYMBOL |
NAME AND FUNCTION |
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1 |
OE |
3 State Output Enable |
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Input (Active LOW) |
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2, 5, 6, 9, 12, |
Q0 to Q7 |
3 State Outputs |
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15, 16, 19 |
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3, 4, 7, 8, 13, |
D0 to D7 |
Data Inputs |
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14, 17, 18 |
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11 |
LE |
Latch Enable Input |
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10 |
GND |
Ground (0V) |
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20 |
VCC |
Positive Supply Voltage |
TRUTH TABLE
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INPUTS |
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OUTPUTS |
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OE |
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LE |
D |
Q |
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H |
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X |
X |
Z |
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L |
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L |
X |
NO CHANGE (*) |
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L |
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H |
L |
L |
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L |
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H |
H |
H |
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X: Don’t Care
Z: High Impedance
(*): Q Outputs are latched at the time when the LE input is taken low logic level.
LOGIC DIAGRAM
2/11
M74HCT373
ABSOLUTE MAXIMUM RATINGS
Symbol |
Parameter |
Value |
Unit |
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VCC |
Supply Voltage |
-0.5 to +7 |
V |
VI |
DC Input Voltage |
-0.5 to VCC + 0.5 |
V |
VO |
DC Output Voltage |
-0.5 to VCC + 0.5 |
V |
IIK |
DC Input Diode Current |
± 20 |
mA |
IOK |
DC Output Diode Current |
± 20 |
mA |
IO |
DC Output Current |
± 35 |
mA |
ICC or IGND |
DC VCC or Ground Current |
± 70 |
mA |
PD |
Power Dissipation |
500(*) |
mW |
Tstg |
Storage Temperature |
-65 to +150 |
°C |
TL |
Lead Temperature (10 sec) |
300 |
°C |
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
RECOMMENDED OPERATING CONDITIONS
Symbol |
Parameter |
Value |
Unit |
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VCC |
Supply Voltage |
4.5 to 5.5 |
V |
VI |
Input Voltage |
0 to VCC |
V |
VO |
Output Voltage |
0 to VCC |
V |
Top |
Operating Temperature |
-55 to 125 |
°C |
tr, tf |
Input Rise and Fall Time (VCC = 4.5 to 5.5V) |
0 to 500 |
ns |
3/11
M74HCT373
DC SPECIFICATIONS
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Test Condition |
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Value |
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Symbol |
Parameter |
VCC |
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TA = 25°C |
-40 to 85°C |
-55 to 125°C |
Unit |
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(V) |
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Min. |
Typ. |
Max. |
Min. |
Max. |
Min. |
Max. |
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VIH |
High Level Input |
4.5 |
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2.0 |
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2.0 |
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2.0 |
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V |
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Voltage |
to |
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5.5 |
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VIL |
Low Level Input |
4.5 |
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0.8 |
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0.8 |
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0.8 |
V |
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Voltage |
to |
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5.5 |
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VOH |
High Level Output |
4.5 |
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IO=-20 μA |
4.4 |
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4.5 |
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4.4 |
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4.4 |
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V |
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Voltage |
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IO=-6.0 mA |
4.18 |
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4.31 |
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4.13 |
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4.10 |
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VOL |
Low Level Output |
4.5 |
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IO=20 μA |
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0.0 |
0.1 |
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0.1 |
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0.1 |
V |
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Voltage |
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IO=6.0 mA |
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0.17 |
0.26 |
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0.33 |
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0.40 |
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II |
Input Leakage |
5.5 |
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VI = VCC or GND |
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± 0.1 |
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± 1 |
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± 1 |
μA |
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Current |
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IOZ |
High Impedance |
5.5 |
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VI = VIH or VIL |
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± 0.5 |
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± 5 |
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± 10 |
μA |
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Output Leakage |
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VO = VCC or GND |
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Current |
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ICC |
Quiescent Supply |
5.5 |
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VI = VCC or GND |
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4 |
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40 |
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80 |
μA |
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Current |
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ICC |
Additional Worst |
5.5 |
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Per Input pin |
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2.0 |
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2.9 |
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3.0 |
mA |
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Case Supply |
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VI = 0.5V or |
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Current |
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VI = 2.4V |
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Other Inputs at |
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VCC or GND |
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IO = 0 |
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4/11