The M74HCT04 is a high speed CMOS hex
inverter fabricated with silicon gate C
technology.
The internal circuit is composed of 3 stages
including a buffer output, which enables high
noise immunity and stable output.
The M74HCT04 is designed to directly interface
2
HSC
MOS systems with TTL and NMOS
components.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
2
MOS
May 2008 Rev 21/11
www.st.com
11
Pin connection and IEC logic symbolsM74HCT04
1 Pin connection and IEC logic symbols
Figure 1.Pin connections and IEC logic symbols
14
1A
1
V
CC
1Y
2A
2Y
3A
GND
3Y
2
3
4
5
6
7
13
6A
6Y
12
11
5A
5Y
10
9
4A
4Y
8
Table 2.Pin description
Pin numberSymbolName and function
1, 3, 5, 9, 11, 131A to 6AData inputs
2, 4, 6, 8, 10, 121Y to 6YData outputs
7GNDGround (0 V)
14V
CC
Positive supply voltage
Figure 2.Input and output equivalent circuit
V
CC
Input
GND
Table 3.Truth table
AY
LH
HL
2/11
GND
V
CC
Output
M74HCT04Maximum rating
2 Maximum rating
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only, and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may aff ect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 4.Absolute maximum ratings
SymbolParameterValueUnit
V
I
CC
I
T
1. 500mW at 65 ° C; derate to 300 mW by 10 mW/ ° C from 65 ° C to 85 ° C
Supply voltage-0.5 to +7V
CC
DC input voltage-0.5 to VCC + 0.5V
V
I
DC output voltage-0.5 to VCC + 0.5V
V
O
I
DC input diode current± 20mA
IK
DC output diode current± 20mA
I
OK
I
DC output current± 25mA
O
or
DC VCC or Ground current± 50mA
GND
P
Power dissipation500
D
Storage temperature-65 to +150°C
stg
Lead temperature (10 sec)300°C
T
L
(1)
mW
Table 5.Recommemded operating conditions
SymbolParameterValueUnit
V
V
T
t
Supply voltage4.5 to 5.5V
CC
Input voltage0 to V
V
I
Output voltage0 to V
O
Operating temperature-55 to 125°C
op
, tfInput rise and fall time (VCC = 4.5 to 5.5 V)0 to 500ns
r
CC
CC
V
V
3/11
Maximum ratingM74HCT04
Table 6.DC specifications
Test conditionValue
SymbolParameter
V
CC
= 25 °C-40 to 85°C
T
A
(V)
MinTypMaxMinMaxMinMax
V
V
V
I
High level input
IH
voltage
Low level input
V
IL
voltage
High level output
OH
voltage
Low level output
OL
voltage
Input leakage
I
I
current
Quiescent supply
CC
current
4.5
to
5.5
4.5
to
5.5
4.5
4.5
5.5V
5.5V
2.02.02.0V
0.80.80.8V
I
=-20 μA4.44.54.44.4
O
= -4.0 mA4.184.314.134.10
I
O
I
= 20 μA0.00.10.10.1
O
= 4.0 mA0.170.260.330.40
I
O
= VCC or GND± 0.1± 1± 1μA
I
= VCC or GND11020μA
I
Per input pin
= 0.5 V or
V
Additional worst
Δ I
CC
case supply
5.5
current
Table 7.AC electric al characteristics (CL = 50 pF, input tr = tf = 6 ns)
I
= 2.4 V
V
I
Other inputs at
VCC or GND
= 0
I
O
2.02.93.0mA
-55 to
125°C
Unit
V
V
Test conditionValue
SymbolParameter
V
CC
(V)
t
TLH tTHL
t
PLH tPHL
Output transition
time
Propagation delay
time
4.58151923ns
4.511182327ns
4/11
= 25°C-40 to 85°C
T
A
-55 to
125°C
Min.Typ. Max. Min.Max. Min. Max.
Unit
M74HCT04Maximum rating
Table 8.Capacitive characteristics
Test conditionValue
SymbolParameter
V
CC
TA = 25°C-40 to 85°C
-55 to
125°C
(V)
MinTypMaxMinMaxMinMax
C
C
1. CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current
consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation.
I
Input capacitance5101010pF
IN
Power dissipation
PD
capacitance
= CPD x VCC x fIN + ICC/6 (per gate)
CC(opr)
(1)
20pF
Unit
5/11
Test circuitM74HCT04
3 Test circuit
Figure 3.Test circuit
1. CL = 50pF or equivalent (includes jig and probe capacitance)
= Z
2. R
T
of pulse generator (typically 50Ω)
OUT
Figure 4.Wavefor m: pr opa gation dela y times (f = 1 MHz; 50 % duty cycle)
6/11
M74HCT04Package mechanical data
4 Package mechanical data
In order to meet environmental requ irements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related t o soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.