ST M74HC597 User Manual
M74HC597
8 BIT LATCH/SHIFT REGISTER
■ HIGH SPEED :
f
= 50 MHz (TYP.) at VCC = 6V
MAX
■ LOW POWER DISSIPATION:
I
=4µA(MAX.) at TA=25°C
CC
■ HIGH NOISE IMMUNITY:
V
= V
NIH
■ SYMMETRICAL OUTPUT IMPEDANCE:
|I
| = IOL = 4mA (MIN)
OH
■ BALANCED PROPAGATION DELAYS:
t
≅ t
PLH
■ WIDE OPERATING VOLTAGE RANGE:
V
(OPR) = 2V to 6V
CC
■ PIN AND FUNCTION COMPATIBLE WITH
= 28 % VCC (MIN.)
NIL
PHL
74 SERIES 597
DESCRIPTION
The M74HC597 is an high speed CMOS 8 BIT
PIPO SHIFT REGISTER fabricated with silicon
gate C
2
MOS technology.
This devices comes in a 16-pin package and
consist of an 8-bit storage latch feeding a paralle l
in, serial out 8-bit shift register. Both the storage
TSSOPDIP SOP
ORDER CODES
PACKAGE TUBE T & R
DIP M74HC597B1R
SOP M74HC597M1R M74HC597RM13TR
TSSOP M74HC597TTR
register and shift register have positive edge
triggered clocks. The shift register also has direct
load (from storage) and clear inputs.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/14July 2001
M74HC597
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No SYMBOL NAME AND FUNCTION
9 QH’ Serial Data Outputs
10 SCLR
11 SCK
12 RCK
13 SLOAD
10 SI Serial Data Input
15, 1, 2, 3, 4,
5, 6, 7
8 GND Ground (0V)
16 Vcc Positive Supply Voltage
TRUTH TABLE
A to H Parallel Data Inputs
Asynchronous Reset
Input (Active LOW)
Shift Clock Input (LOW to
HIGH Edge-triggered)
Storage Clock Input (LOW
to HIGH Edge-triggered)
Parallel Data Input (Active
Low)
INPUTS
SI SCK SCLR
X X L H X S.R. IS CLEARED TO "L"
X X H L X INPUT REGISTER DATA IS STORED INTO S.R.
LHHX
HHHX
X H H X STATE OF S.R. IS NOT CHANGED
XXXX
XXXX STORAGE REGISTER STATE IS NOT CHANGED
X : Don’t Care
SLOAD RCK
FIRST STAGE OF S.R. BECOMES "L" OTHER STAGES
STORE THE DATA OF PREVIOUS STAGE, RESPECTIVELY
FIRST STAGE OF S.R. BECOMES "H" OTHER STAGES
STORE THE DATA OF PREVIOUS STAGE, RESPECTIVELY
INPUT DATA ON A
OUTPUT
~ H LINE IS STORED INTO INPUT REG-
ISTER
2/14
LOGIC DIAGRAM
M74HC597
This log i c diagram has not be used to est i m at e propagation delays
3/14
M74HC597
TIMING CHART
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
V
V
I
I
OK
I
I
or I
CC
P
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65
Supply Voltage
CC
DC Input Voltage -0.5 to VCC + 0.5
I
DC Output Voltage -0.5 to VCC + 0.5
O
DC Input Diode Current
IK
DC Output Diode Current
DC Output Current
O
DC VCC or Ground Current
GND
Power Dissipation
D
Storage Temperature
stg
Lead Temperature (10 sec)
L
°C; derate to 300mW by 10mW/°C from 65°C to 85°C
-0.5 to +7 V
V
V
± 20 mA
± 20 mA
± 25 mA
± 50 mA
500(*) mW
-65 to +150 °C
300 °C
4/14
M74HC597
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Value Unit
V
V
V
T
t
r
DC SPECIFICATIONS
Symbol Parameter
V
IH
V
IL
V
OH
V
OL
I
I
I
CC
Supply Voltage
CC
Input Voltage 0 to V
I
Output Voltage 0 to V
O
Operating Temperature
op
Input Rise and Fall Time VCC = 2.0V
, t
f
V
V
CC
CC
= 4.5V
= 6.0V
Test Condition Value
= 25°C
T
A
Min. Typ. Max. Min. Max. Min. Max.
High Level Input
V
CC
(V)
2.0 1.5 1.5 1.5
Voltage
6.0 4.2 4.2 4.2
Low Level Input
2.0 0.5 0.5 0.5
Voltage
6.0 1.8 1.8 1.8
High Level Output
Voltage
Low Level Output
Voltage
Input Leakage
Current
Quiescent Supply
Current
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
IO=-20 µA
I
=-20 µA
O
I
=-20 µA
O
I
=-4.0 mA
O
I
=-5.2 mA
O
IO=20 µA
I
=20 µA
O
I
=20 µA
O
I
=4.0 mA
O
I
=5.2 mA
O
= VCC or GND
V
I
= VCC or GND
V
I
1.9 2.0 1.9 1.9
4.4 4.5 4.4 4.4
5.9 6.0 5.9 5.9
4.18 4.31 4.13 4.10
5.68 5.8 5.63 5.60
0.0 0.1 0.1 0.1
0.0 0.1 0.1 0.1
0.0 0.1 0.1 0.1
0.17 0.26 0.33 0.40
0.18 0.26 0.33 0.40
± 0.1 ± 1 ± 1 µA
44080µA
2 to 6 V
CC
CC
-55 to 125 °C
0 to 1000 ns
0 to 500 ns
0 to 400 ns
-40 to 85°C -55 to 125°C
V
V
Unit
V4.5 3.15 3.15 3.15
V4.5 1.35 1.35 1.35
V
V
5/14
Loading...