The M74HC595 is an high speed CMOS 8-BIT
SHIFTREGISTERS/OUTPUTLATCHES
(3-STATE) fabricated with silicon gate C
2
MOS
technology.
This device contains an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit D -t y pe storage
register. The storage register has 8 3-STATE
outputs. Separate clocks a re provided for both t he
shift register and the storage register.
PIN CONNECTION AND IEC LOGIC SYMBOLS
The shift register has a direct-overriding clear,
serial input, and serial output (st andard) pins for
cascading. Both the shift register and storage
register use positive-edge t riggered clocks. If both
clocks are c onnec ted together, the shift r egister
state wi ll always be one clock pulse ahead of the
storage register.
All inputs a re equipped with protection circuits
against static discharge and transient excess
voltage.
1/16March 2004
M74HC595
INPUT AND OUTPUT EQUIVALENT CIRCUITPIN DESCRIPTION
PIN N°SYMBOLNAME AND FUNCTION
1, 2, 3, 4, 5,
6, 7, 15
9QH’Serial Data Outputs
10SCLR
11SCKShift Register Clock Input
13G
14SISerial Data Input
12RCKStorage Register Clock
8GNDGround (0V)
16V
TRUTH TABLE
QA to QHData Outputs
CC
Shift Register Clear Input
Output Enable Input
Input
Positive Supply Voltage
INPUTS
SISCKSCLR
XXXXHQA THRU QH OUTPUTS DISABLE
XXXXLQATHRUQHOUTPUTSENABLE
XXLXXSHIFT REGISTER IS CLEARED
LHXX
HHXX
XHXXSTATE OF S.R. IS NOT CHANGED
XXXX
XXXXSTORAGE REGISTER STATE IS NOT CHANGED
X: Don’t Care
RCKG
FIRST STAGE OF S.R. BECOMES "L" OTHER
STAGES STORE THE DATA OF PREVIOUS
FIRST STAGE OF S.R. BECOMES "H" OTHER
STAGES STORE THE DATA OF PREVIOUS
S.R. DATA IS STORED INTO STORAGE
OUTPUTS
STAGE, RESPECTIVELY
STAGE, RESPECTIVELY
REGISTER
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
2/16
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
M74HC595
TIMING CHART
3/16
M74HC595
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
V
V
I
I
OK
I
I
or I
CC
P
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) Power dissipation at 65°C. Derating from 65
RECOMMENDED OPERATING CONDITIONS
SymbolParameterValueUnit
V
V
V
T
t
r,tf
Supply Voltage
CC
DC Input Voltage-0.5 to VCC+0.5
I
DC Output Voltage-0.5 to VCC+0.5
O
DC Input Diode Current
IK
DC Output Diode Current
DC Output Current
O
DC VCCor Ground Current
GND
-0.5 to +7V
± 20mA
± 20mA
± 35mA
± 70mA
Power DissipationDIP750(*)mW
D
SOP500(*)mW
TSSOP450(*)mW
Storage Temperature
stg
Lead Temperature (10 sec)
L
-65 to +150°C
300°C
°Cto125°C: DIP Package -10mW/°C; SO Package -7mW/°C; TSSOP Package -6.1mW/°C.
Supply Voltage
CC
Input Voltage0 to V
I
Output Voltage0 to V
O
Operating Temperature
op
Input Rise and Fall TimeVCC=2.0V
V
=4.5V
CC
=6.0V
V
CC
2to6V
CC
CC
-55 to 125°C
0 to 1000ns
0 to 500ns
0 to 400ns
V
V
V
V
4/16
DC SPECIFICATIONS
SymbolParameter
V
V
V
V
V
High Level Input
IH
Voltage
V
Low Level Input
IL
Voltage
High Level Output
OH
Voltage
(for QH’ outputs)
High Level Output
OH
Voltage
(for QA to QH
outputs)
Low Level Output
OL
Voltage
(for QH’ outputs)
Low Level Output
OL
Voltage
(for QA to QH
outputs)
Input Leakage
I
I
Current
I
High Impedance
OZ
Output Leakage
Current
Quiescent Supply
I
CC
Current
M74HC595
Test ConditionValue
T
= 25°C
V
CC
(V)
A
Min.Typ. Max.Min.Max. Min. Max.
2.01.51.51.5
6.04.24.24.2
2.00.50.50.5
6.01.81.81.8
=-20 µA
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
V
6.0
6.0
6.0
I=VCC
V
VO=VCCor GND
V
I=VCC
I
O
=-20 µA
I
O
=-20 µA
I
O
=-4.0 mA
I
O
I
=-7.8 mA
O
=-20 µA
I
O
I
=-20 µA
O
=-20 µA
I
O
I
=-6.0 mA
O
=-7.8 mA
I
O
=20 µA
I
O
=20 µA
I
O
I
=20 µA
O
I
=4.0 mA
O
=7.8 mA
I
O
=20 µA
I
O
I
=20 µA
O
I
=20 µA
O
=6.0 mA
I
O
=7.8 mA
I
O
I=VIH
or GND
or V
or GND
1.92.01.91.9
4.44.54.44.4
5.96.05.95.9
4.184.314.134.10
5.685.85.635.60
1.92.01.91.9
4.44.54.44.4
5.96.05.95.9
4.184.314.134.10
5.685.85.635.60
0.00.10.10.1
0.00.10.10.1
0.00.10.10.1
0.170.260.330.40
0.180.260.330.40
0.00.10.10.1
0.00.10.10.1
0.00.10.10.1
0.170.260.330.40
0.180.260.330.40
IL
-40 to 85°C -55 to 125°C
± 0.1± 1± 1µA
± 0.5± 5± 10µA
44080µA
Unit
V4.53.153.153.15
V4.51.351.351.35
V
V
V
V
5/16
M74HC595
AC ELECTRICAL CHARACTERISTICS (CL= 50 pF, Input tr=tf=6ns)
Test ConditionValue
T
SymbolParameter
t
TLHtTHL
Output Transition
Time
(Qn)
t
TLHtTHL
Output Transition
Time
(QH’)
t
PLHtPHL
Propagation Delay
Time
(SCK - QH’)
t
PLHtPHL
t
PLHtPHL
Propagation Delay
Time
- QH’)
(SCLR
Propagation Delay
Time
(RCK - Qn)
t
PZLtPZH
High Impedance
Output Enable
Time
t
PLZtPHZ
High Impedance
Output Disable
Time
f
t
MAX
W(H)
Maximum Clock
Frequency
Minimum Pulse
Width
(SCK, RCK)
t
W(L)
t
s
Minimum Pulse
Width
)
(SCLR
Minimum Set-up
Time
(SI - CCK)
t
Minimum Set-up
s
Time
(SCK - RCK)
C
V
CC
(V)
L
(pF)
2.0
50
6.06101315
2.0
50
6.07131620
2.0
50
6.013212632
2.0
50
6.015303745
2.0
50
6.017263238
2.0
150
6.022324148
2.0
50
L
=1KΩ
R
6.013232935
2.0
R
150
=1KΩ
L
6.017303745
2.0
R
50
=1KΩ
L
6.014263238
2.0
50
6.035592824
2.0
150
6.031452520
2.0
50
6.06131619
2.0
50
6.06131619
2.0
50
6.0491113
2.0
50
6.06131619
= 25°C
A
Min.Typ. Max.Min.Max. Min. Max.
25607590
307595115
45125155190
60175220265
60150190225
75190240285
45135170205
60175220265
30150190225
6.0174.84
5.2144.23.4
177595110
207595110
25506575
357595110
-40 to 85°C -55 to 125°C
Unit
ns4.57121518
ns4.58151923
ns4.515253138
ns4.518354453
ns4.520303845
ns4.525384857
ns4.515273441
ns4.520354453
ns4.515303845
MHz4.530502420
MHz4.526402117
ns4.56151922
ns4.56151922
ns4.55101315
ns4.58151922
6/16
M74HC595
Test ConditionValue
= 25°C
SymbolParameter
t
Minimum Set-up
s
Time
- RCK)
(SCRL
Minimum Hold
t
h
Time
C
V
CC
(V)
L
(pF)
2.0
50
6.07172125
2.0
50
T
A
Min.Typ. Max.Min.Max. Min. Max.
40100125145
6.0000
t
REM
Minimum Clear
Removal Time
2.0
15506575
50
6.0391113
CAPACITIVE CHARACTERISTICS
Test ConditionValue
= 25°C
SymbolParameter
V
CC
(V)
C
C
Input Capacitance
IN
Power Dissipation
PD
Capacitance (note
1)
1) CPDis defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
T
A
Min.Typ. Max.Min.Max. Min. Max.
5101010pF
184pF
-40 to 85°C -55 to 125°C
Unit
ns4.510202529
000
ns4.5000
ns4.53101315
-40 to 85°C -55 to 125°C
CC(opr)=CPDxVCCxfIN+ICC
Unit
TEST CIRCUIT
TESTSWITCH
t
PLH,tPHL
t
PZL,tPLZ
t
PZH,tPHZ
CL= 50pF/150pF or equivalent (includes jig and probe capacitance)
=1KΩ or equivalent
R
1
R
T=ZOUT
of pulse generator (typically 50Ω)
Open
V
CC
GND
7/16
M74HC595
WAVEFORM 1: SCK TO QH’ PROPAGATION DELAY TIME S, SCK MINIMUM PULSE WIDTH
(f=1MHz; 50% duty cycle)
WAVEFORM 2: RCK TO Qn PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle)
WAVEFORM 3: SI TO SCK SETUP AND HO LD TIMES (f=1MHz; 50% duty cycle)
8/16
WAVEFORM 4: SCK TO RCK SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
M74HC595
WAVEFORM 5: SCLR
MINIMUM PULSE W IDTH, MINIMUM REMOVAL TIME
(f=1MHz; 50% duty cycle)
9/16
M74HC595
WAVEFORM 6: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% du ty cycle)
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