The M74HC533 is an high speed CMOS OCTAL
LATCH WITH 3-STATE OUTPUTS fabricated
with silicon gate C
2
MOS technology.
This 8-BIT D-Type la tches is controlled by a latch
enable input (LE) and output enable input (OE
).
While the LE in put is held at a high level, the Q
outputs will follow the data input. When the LE is
taken, the Q outputs will be latched at the logic
level of D input data.
TSSOPDIPSOP
ORDER CODES
PACKAGETUBET & R
DIPM74HC533B1R
SOPM74HC533M1RM74HC533RM13TR
TSSOPM74HC533TTR
While the OE
input is at low level, the eight outputs
will be in a norm al logic state (high or low logic
level) and while high le vel the outpu ts will be in a
high impedance state.
The 3-State output configuration and the wide
choice of outline make bus organized system
simple.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/11August 2001
M74HC533
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN NoSYMBOLNAME AND FUNCTION
1OE
2, 5, 6, 9, 12,
15, 16, 19
3, 4, 7, 8, 13,
14, 17, 18
11LELatch Enable Input
10GNDGround (0V)
20V
TRUTH TABLE
INPUTSOUTPUTS
to Q73 State Outputs
Q0
D0 to D7Data Inputs
CC
3 State Output Enable
Input (Active LOW)
Positive Supply Voltage
OE
LEDQ
HXXZ
LLXNO CHANGE (*)
LHLH
LHHL
X: Don’t Care
Z: High Impedance
(*): Q
Outputs ar e l atched at the time when the LE i nput is taken lo w l ogic level.
LOGIC DIAGRAM
2/11
M74HC533
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
V
V
I
I
OK
I
I
or I
CC
P
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
Flop) and the C
when n pcs of F lip Flop operate, can be gained by the fol l owing equati on: C
PD
-40 to 85°C -55 to 125°C
= CPD x VCC x fIN + ICC/8 (per Flip
CC(opr)
PD(TOTAL)
= 22 + 16 x n (pF)
Unit
5/11
M74HC533
TEST CIRCUIT
TESTSWITCH
t
, t
PLH
PHL
, t
t
PZL
PLZ
t
, t
PZH
PHZ
CL = 50pF/150pF or equivalent (includes jig and probe capacitance)
R
= 1KΩ or equivalent
1
R
= Z
of pulse generator (t ypically 50Ω)
T
OUT
Open
V
CC
GND
WAVEFORM 1: LE TO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, Dn TO LE SETUP
AND HOLD TIMES (f=1MHz; 50% duty cycle)
6/11
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycl e )
M74HC533
WAVEFORM 3: PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle)
7/11
M74HC533
Plastic DIP-20 (0.25) MECHANICAL DATA
mm.inch
DIM.
MIN.TYPMAX.MIN.TYP.MAX.
a10.2540.010
B1.391.650.0550.065
b0.450.018
b10.250.010
D25.41.000
E8.50.335
e2.540.100
e322.860.900
F7.10.280
I3.930.155
L3.30.130
Z1.340.053
8/11
P001J
SO-20 MECHANICAL DATA
M74HC533
DIM.
MIN.TYPMAX.MIN.TYP.MAX.
A2.650.104
a10.10.20.0040.008
a22.450.096
b0.350.490.0140.019
b10.230.320.0090.012
C0.50.020
c145° (typ.)
D12.6013.000.4960.512
E10.0010.650.3930.419
e1.270.050
e311.430.450
F7.407.600.2910.300
L0.501.270.0200.050
M0.750.029
S8° (max.)
mm.inch
PO13L
9/11
M74HC533
TSSOP20 MECHANICAL DATA
mm.inch
DIM.
MIN.TYPMAX.MIN.TYP.MAX.
A1.20.047
A10.050.150.0020.0040.006
A20.811.050.0310.0390.041
b0.190.300.0070.012
c0.090.200.0040.0089
D6.46.56.60.2520.2560.260
E6.26.46.60.2440.2520.260
E14.34.44.480.1690.1730.176
e0.65 BSC0.0256 BSC
K0°8°0°8°
L0.450.600.750.0180.0240.030
A2
A
A1
b
e
K
c
L
E
D
E1
PIN 1 IDENTIFICATION
10/11
1
0087225C
M74HC533
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