ST M74HC533 User Manual

M74HC533
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUT INVERTING
HIGH SPEED:
t
= 12ns (TYP.) at VCC = 6V
PD
LOW POWER DISSIPATION:
I
= 4µA(MAX.) at TA=25°C
CC
HIGH NOISE IMMUNITY:
= V
V
NIH
SYMMETRICAL OUTPUT IMPEDANCE:
|I
| = IOL = 6mA (MIN)
OH
BALANCED PROPAGATION DELAYS:
t
t
PLH
WIDE OPERATING VOLTAGE RANGE:
V
(OPR) = 2V to 6V
CC
PIN AND FUNCTION COMPATIBLE WITH
= 28 % VCC (MIN.)
NIL
PHL
74 SERIES 533
DESCRIPTION
The M74HC533 is an high speed CMOS OCTAL LATCH WITH 3-STATE OUTPUTS fabricated with silicon gate C
2
MOS technology.
This 8-BIT D-Type la tches is controlled by a latch enable input (LE) and output enable input (OE
).
While the LE in put is held at a high level, the Q outputs will follow the data input. When the LE is taken, the Q outputs will be latched at the logic level of D input data.
TSSOPDIP SOP
ORDER CODES
PACKAGE TUBE T & R
DIP M74HC533B1R
SOP M74HC533M1R M74HC533RM13TR
TSSOP M74HC533TTR
While the OE
input is at low level, the eight outputs will be in a norm al logic state (high or low logic level) and while high le vel the outpu ts will be in a high impedance state. The 3-State output configuration and the wide choice of outline make bus organized system simple. All inputs are equipped with protection circuits against static discharge and transient excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/11August 2001
M74HC533
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No SYMBOL NAME AND FUNCTION
1OE
2, 5, 6, 9, 12,
15, 16, 19
3, 4, 7, 8, 13,
14, 17, 18
11 LE Latch Enable Input 10 GND Ground (0V) 20 V
TRUTH TABLE
INPUTS OUTPUTS
to Q7 3 State Outputs
Q0
D0 to D7 Data Inputs
CC
3 State Output Enable Input (Active LOW)
Positive Supply Voltage
OE
LE D Q
HXXZ
L L X NO CHANGE (*) LHLH LHHL
X: Don’t Care Z: High Impedance (*): Q
Outputs ar e l atched at the time when the LE i nput is taken lo w l ogic level.
LOGIC DIAGRAM
2/11
M74HC533
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
V
V
I
I
OK
I
I
or I
CC
P
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied (*) 500mW at 65
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Value Unit
V
V
V
T
t
r
Supply Voltage
CC
DC Input Voltage -0.5 to VCC + 0.5
I
DC Output Voltage -0.5 to VCC + 0.5
O
DC Input Diode Current
IK
DC Output Diode Current DC Output Current
O
DC VCC or Ground Current
GND
Power Dissipation
D
Storage Temperature
stg
Lead Temperature (10 sec)
L
°C; derate to 300mW by 10mW/°C from 65°C to 85°C
Supply Voltage
CC
Input Voltage 0 to V
I
Output Voltage 0 to V
O
Operating Temperature
op
Input Rise and Fall Time VCC = 2.0V
, t
f
V V
CC CC
= 4.5V = 6.0V
-0.5 to +7 V
± 20 mA ± 20 mA ± 35 mA ± 70 mA
500(*) mW
-65 to +150 °C
300 °C
2 to 6 V
CC CC
-55 to 125 °C 0 to 1000 ns
0 to 500 ns 0 to 400 ns
V V
V V
3/11
M74HC533
DC SPECIFICATIONS
Symbol Parameter
V
V
V
V
I
I
High Level Input
IH
Voltage
Low Level Input
IL
Voltage
High Level Output
OH
Voltage
Low Level Output
OL
Voltage
I
Input Leakage
I
Current High Impedance
OZ
Output Leakage Current
Quiescent Supply
CC
Current
Test Condition Value
V
(V)
CC
= 25°C
A
Min. Typ. Max. Min. Max. Min. Max.
-40 to 85°C -55 to 125°C
T
2.0 1.5 1.5 1.5
6.0 4.2 4.2 4.2
2.0 0.5 0.5 0.5
6.0 1.8 1.8 1.8
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
6.0
IO=-20 µA I
=-20 µA
O
I
=-20 µA
O
I
=-6.0 mA
O
I
=-7.8 mA
O
IO=20 µA I
=20 µA
O
I
=20 µA
O
I
=6.0 mA
O
I
=7.8 mA
O
= VCC or GND
V
I
= VIH or V
V
I
IL
VO = VCC or GND
= VCC or GND
V
I
1.9 2.0 1.9 1.9
4.4 4.5 4.4 4.4
5.9 6.0 5.9 5.9
4.18 4.31 4.13 4.10
5.68 5.8 5.63 5.60
0.0 0.1 0.1 0.1
0.0 0.1 0.1 0.1
0.0 0.1 0.1 0.1
0.17 0.26 0.33 0.40
0.18 0.26 0.33 0.40
± 0.1 ± 1 ± 1 µA
± 0.5 ± 5 ± 10 µA
44080µA
Unit
V4.5 3.15 3.15 3.15
V4.5 1.35 1.35 1.35
V
V
4/11
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)
Test Condition Value
T
Symbol Parameter
t
TLH tTHL
t
PLH tPHL
t
PZL tPZH
Output Transition Time
Propagation Delay Time
(LE, D - Q
)
High Impedance Output Enable Time
t
PLZ tPHZ
High Impedance Output Disable Time
t
W(H)
Minimum Pulse Width (LE)
Minimum Set-up
t
s
Time
Minimum Hold
t
h
Time
C
V
CC
(V)
L
(pF)
2.0 50
6.0 6101315
2.0 50
6.0 12 21 26 32
2.0
150
6.0 16 30 37 45
2.0
R
50
= 1 K
L
6.0 11 21 26 32
2.0
150
L
= 1 K
R
6.0 15 30 37 45
2.0
R
50
= 1 K
L
6.0 13 21 26 32
2.0 50
6.0 6131619
2.0 50
6.0 3 9 11 13
2.0 50
6.0 5 5 5
= 25°C
A
Min. Typ. Max. Min. Max. Min. Max.
25 60 75 90
42 125 155 190
57 175 220 265
39 125 155 190
54 175 220 265
30 125 155 190
15 75 95 110
16 50 65 75
555
M74HC533
-40 to 85°C -55 to 125°C
Unit
ns4.5 7121518
ns4.5 14 25 31 38
ns4.5 19 35 44 53
ns4.5 13 25 31 38
ns4.5 18 35 44 53
ns4.5 14 25 31 38
ns4.5 6151922
ns4.5 4101315
ns4.5 5 5 5
CAPACITIVE CHARACTERISTICS
Test Condition Value
T
Symbol Parameter
C
C
C
Input Capacitance
IN
Output
OUT
Capacitance Power Dissipation
PD
Capacitance (note
V
CC
(V)
= 25°C
A
Min. Typ. Max. Min. Max. Min. Max.
5101010pF
10 pF
38 pF
1)
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I Flop) and the C
when n pcs of F lip Flop operate, can be gained by the fol l owing equati on: C
PD
-40 to 85°C -55 to 125°C
= CPD x VCC x fIN + ICC/8 (per Flip
CC(opr)
PD(TOTAL)
= 22 + 16 x n (pF)
Unit
5/11
M74HC533
TEST CIRCUIT
TEST SWITCH
t
, t
PLH
PHL
, t
t
PZL
PLZ
t
, t
PZH
PHZ
CL = 50pF/150pF or equivalent (includes jig and probe capacitance) R
= 1K or equivalent
1
R
= Z
of pulse generator (t ypically 50)
T
OUT
Open
V
CC
GND
WAVEFORM 1: LE TO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, Dn TO LE SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
6/11
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycl e )
M74HC533
WAVEFORM 3: PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle)
7/11
M74HC533
Plastic DIP-20 (0.25) MECHANICAL DATA
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
a1 0.254 0.010
B 1.39 1.65 0.055 0.065 b 0.45 0.018
b1 0.25 0.010
D 25.4 1.000 E 8.5 0.335
e 2.54 0.100
e3 22.86 0.900
F 7.1 0.280
I 3.93 0.155
L 3.3 0.130
Z 1.34 0.053
8/11
P001J
SO-20 MECHANICAL DATA
M74HC533
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 2.65 0.104 a1 0.1 0.2 0.004 0.008 a2 2.45 0.096
b 0.35 0.49 0.014 0.019
b1 0.23 0.32 0.009 0.012
C 0.5 0.020 c1 45° (typ.)
D 12.60 13.00 0.496 0.512
E 10.00 10.65 0.393 0.419
e 1.27 0.050
e3 11.43 0.450
F 7.40 7.60 0.291 0.300
L 0.50 1.27 0.020 0.050
M 0.75 0.029
S8° (max.)
mm. inch
PO13L
9/11
M74HC533
TSSOP20 MECHANICAL DATA
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 1.2 0.047
A1 0.05 0.15 0.002 0.004 0.006
A2 0.8 1 1.05 0.031 0.039 0.041
b 0.19 0.30 0.007 0.012
c 0.09 0.20 0.004 0.0089
D 6.4 6.5 6.6 0.252 0.256 0.260
E 6.2 6.4 6.6 0.244 0.252 0.260
E1 4.3 4.4 4.48 0.169 0.173 0.176
e 0.65 BSC 0.0256 BSC
K0° 8°0° 8°
L 0.45 0.60 0.75 0.018 0.024 0.030
A2
A
A1
b
e
K
c
L
E
D
E1
PIN 1 IDENTIFICATION
10/11
1
0087225C
M74HC533
Information furnished is bel ieved to be accurate and reliable. However, STMicroe lectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No li cense is granted by i mp lication or otherwise under a ny patent or patent rig h ts of S TMic roelec tronics. Specifications mentioned in this publication ar e subject to change without notice. This publication supersedes and replaces all information previously supplied. S TMicroelectronics products are not authorized for use as critica l components in life suppo rt devices or systems without express written approval of STMicroelectronics.
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11/11
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