ST M74HC4543 User Manual
M74HC4543
BCD TO 7 SEGMENT LATCH/DECODER/LCD DRIVER
■HIGH SPEED:
tPD = 14ns (TYP.) at VCC = 6V
■LOW POWER DISSIPATION: ICC = 4μA(MAX.) at TA=25°C
■HIGH NOISE IMMUNITY: VNIH = VNIL = 28 % VCC (MIN.)
■SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN)
■BALANCED PROPAGATION DELAYS: tPLH tPHL
■WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V
■PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 4543
DIP |
SOP |
TSSOP |
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ORDER CODES |
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PACKAGE |
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TUBE |
T & R |
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DIP |
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M74HC4543B1R |
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SOP |
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M74HC4543M1R |
M74HC4543RM13TR |
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TSSOP |
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M74HC4543TTR |
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DESCRIPTION
The M74HC4543 is an high speed CMOS BCD-TO-7 SEGMENT DECODER WITH LCD DRIVER fabricated with silicon gate C2MOS technology.
This device consists of BCD-TO-7 segment decoder with a BCD input latch and a 7-segment driver for a liquid crystal display (LCD). When any illegal BCD input signal is applied or input BI is held high, the display is blanked. When driving
LCDs, a common square wave signal should be applied not only to the PH input of this device but also to the electrically common backplane of the display. For other types of readouts, such as light-emitting diode (LED), some additional drivers, such as a transistor array is required. All inputs are equipped with protection circuits against static discharge and transient excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
July 2001 |
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M74HC4543
INPUT AND OUTPUT EQUIVALENT CIRCUIT |
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PIN DESCRIPTION |
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PIN No |
SYMBOL |
NAME AND FUNCTION |
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1 |
LD |
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Latch Disable Input |
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(Active HIGH) |
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5, 3, 2, 4 |
A to D |
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Address (Data) Inputs |
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6 |
PH |
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Phase Input (Active |
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HIGH) |
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7 |
BI |
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Blanking Input (Active |
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HIGH) |
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9, 10, 11, 12, |
a to g |
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Segment Outputs |
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13, 15, 14 |
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8 |
GND |
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Ground (0V) |
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16 |
VCC |
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Positive Supply Voltage |
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TRUTH TABLE |
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INPUT |
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OUTPUT |
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DISPLAY MODE |
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LD |
BI |
PH |
D |
C |
B |
A |
a |
b |
c |
d |
e |
f |
g |
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X |
H |
L |
X |
X |
X |
X |
L |
L |
L |
L |
L |
L |
L |
BLANK |
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H |
L |
L |
L |
L |
L |
L |
H |
H |
H |
H |
H |
H |
L |
0 |
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H |
L |
L |
L |
L |
L |
H |
L |
H |
H |
L |
L |
L |
L |
1 |
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H |
L |
L |
L |
L |
H |
L |
H |
H |
L |
H |
H |
L |
H |
2 |
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H |
L |
L |
L |
L |
H |
H |
H |
H |
H |
H |
L |
L |
H |
3 |
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H |
L |
L |
L |
H |
L |
L |
L |
H |
H |
L |
L |
H |
H |
4 |
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H |
L |
L |
L |
H |
L |
H |
H |
L |
H |
H |
L |
H |
H |
5 |
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H |
L |
L |
L |
H |
H |
L |
H |
L |
H |
H |
H |
H |
H |
6 |
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H |
L |
L |
L |
H |
H |
H |
H |
H |
H |
L |
L |
L |
L |
7 |
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H |
L |
L |
H |
L |
L |
L |
H |
H |
H |
H |
H |
H |
H |
8 |
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H |
L |
L |
H |
L |
L |
H |
H |
H |
H |
H |
L |
H |
H |
9 |
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H |
L |
L |
H |
L |
H |
X |
L |
L |
L |
L |
L |
L |
L |
BLANK |
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H |
L |
L |
H |
H |
X |
X |
L |
L |
L |
L |
L |
L |
L |
BLANK |
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L |
L |
L |
X |
X |
X |
X |
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##### |
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##### |
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− |
− |
H |
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− |
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INVERSE OF ABOVE OUTPUT LEVEL |
DISPLAY AS |
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ABOVE |
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X : Don’t Care |
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− : Same as above combinations |
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### : Depends upon the BCD code previously applied when LD =’H’ |
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M74HC4543
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
DISPLAY MODE
ABSOLUTE MAXIMUM RATINGS
Symbol |
Parameter |
Value |
Unit |
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VCC |
Supply Voltage |
-0.5 to +7 |
V |
VI |
DC Input Voltage |
-0.5 to VCC + 0.5 |
V |
VO |
DC Output Voltage |
-0.5 to VCC + 0.5 |
V |
IIK |
DC Input Diode Current |
± 20 |
mA |
IOK |
DC Output Diode Current |
± 20 |
mA |
IO |
DC Output Current |
± 25 |
mA |
ICC or IGND |
DC VCC or Ground Current |
± 50 |
mA |
PD |
Power Dissipation |
500(*) |
mW |
Tstg |
Storage Temperature |
-65 to +150 |
°C |
TL |
Lead Temperature (10 sec) |
300 |
°C |
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
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