The M74HC4094 is an high speed CMOS 8 BIT
SIPO SHIFT LATCH REGISTER fabricated with
silicon gate C
This device consists of an 8 bit shift register and
an 8 bit latch with 3 state output buffer. Data is
shifted serially trough the shift register on the
positive going transition of the clock input signal.
Theoutputofthelaststage(Qs)canbeusedto
cascade several devices.
Data on the Qs out put is transferred to a second
output (Qs’) on the following negative transition of
=28%VCC(MIN.)
PHL
2
MOS technology.
M74HC4094
TSSOPDIPSOP
ORDER CODES
PACKAGETUBET & R
DIPM74HC4094B1R
SOPM74HC4094M1R M74HC4094RM13TR
TSSOPM74HC4094TTR
the clock input sig nal. The data of each stage of
the s hift register is provided with a latch, which
latches data on the negativ e going transition of the
STROBE input signal. When the STROBE input is
held high, data propagates through the latch to a
3-state output buffer.
This buffer is enabled when OUT PUT ENA BLE
input is taken high.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNE CTION AND IEC LOGIC SYMBOLS
1/12January 2003
M74HC4094
INPUT AND OUTPUT EQUIVALENT CIRCUITPIN DESCRIPTION
This logic diagram has not be used to estimate propagation delays
2/12
TIMING CHART
M74HC4094
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
CC
V
V
I
IK
I
OK
I
or I
I
CC
P
T
stg
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mWat 65
Supply Voltage
DC Input Voltage-0.5 to VCC+ 0.5
I
DC Output Voltage-0.5 to VCC+ 0.5
O
DC Input Diode Current
DC Output Diode Current
DC Output Current
O
DC VCCor Ground Current
GND
Power Dissipation
D
Storage Temperature
Lead Temperature (10 sec)
L
°C; derate to 300mW by 10mW/°Cfrom65°Cto85°C
-0.5 to +7V
V
V
± 20mA
± 20mA
± 25mA
± 50mA
500(*)mW
-65 to +150°C
300°C
3/12
M74HC4094
RECOMMENDED OPERATING CONDITIONS
SymbolParameterValueUnit
V
CC
V
V
T
t
r,tf
DC SPECIFICATIONS
SymbolParameter
V
IH
V
IL
V
OH
V
OL
I
I
I
OZ
I
CC
Supply Voltage
Input Voltage0 to V
I
Output Voltage0 to V
O
Operating Temperature
op
Input Rise and Fall TimeVCC= 2.0V
= 4.5V
V
CC
= 6.0V
V
CC
Test ConditionValue
= 25°C
T
A
Min.Typ. Max.Min. Max. Min.Max.
High Level Input
V
CC
(V)
2.01.51.51.5
Voltage
6.04.24.24.2
Low Level Input
2.00.50.50.5
Voltage
6.01.81.81.8
High Level Output
Voltage
Low Level Output
Voltage
Input Leakage
Current
High Impedance
Output Leakage
Current
Quiescent Supply
Current
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
6.0
IO=-20 µA
I
=-20 µA
O
=-20 µA
I
O
=-4.0 mA
I
O
=-5.2 mA
I
O
IO=20 µA
I
=20 µA
O
=20 µA
I
O
=4.0 mA
I
O
=5.2 mA
I
O
I=VIH
or GND
or V
IL
V
I=VCC
V
VO=VCCor GND
V
I=VCC
or GND
1.92.01.91.9
4.44.54.44.4
5.96.05.95.9
4.184.314.134.10
5.685.85.635.60
0.00.10.10.1
0.00.10.10.1
0.00.10.10.1
0.170.260.330.40
0.180.260.330.40
± 0.1± 1± 1µA
± 0.5± 5± 10µA
44080µA
2to6V
CC
CC
-55 to 125°C
0 to 1000ns
0 to 500ns
0 to 400ns
-40 to 85°C -55 to 125°C
V
V
Unit
V4.53.153.153.15
V4.51.351.351.35
V
V
4/12
AC ELECTRICAL C HARACTERISTICS (CL= 50 pF, Input tr=tf=6ns)
Test ConditionValue
= 25°C
SymbolParameter
t
TLHtTHL
t
PLHtPHL
Output Transition
Time
Propagation Delay
Time
(CLOCK - Qn)
t
PLHtPHL
Propagation Delay
Time
(CLOCK - QS, Q’S)
t
PLHtPHL
Propagation Delay
Time
(STROBE - Qn)
t
PZLtPZH
High Impedance
Output Enable
Time
t
PHZtPLZ
High Impedance
Output Disable
Time
f
t
W(H)
t
t
MAX
W(L)
W(L)
t
s
Maximum Clock
Frequency
Minimum Pulse
Width
Minimum Pulse
Width
Minimum Set-up
Time
(SERIAL INPUT)
t
Minimum Set-up
s
Time
(STROBE)
Minimum Hold
t
h
Time
(SI, ST)
V
CC
(V)
2.0307595115
6.07131620
2.092200250300
6.020344351
2.065150190225
6.015263238
2.075160200240
6.016273441
2.058150190225
6.013263238
2.035150190225
6.013263238
2.06164.84
6.035802824
2.0177595110
6.06131619
2.0287595110
6.06131619
2.0307595110
6.05131619
2.045100125145
6.08172125
2.0000
6.0000
T
A
Min.Typ. Max.Min. Max. Min.Max.
M74HC4094
-40 to 85°C -55 to 125°C
Unit
ns4.58151923
ns4.526405060
ns4.519303845
ns4.520324048
ns4.516303845
ns4.516303845
MHz4.530662420
ns4.57151922
ns4.56151922
ns4.57151922
ns4.510202529
ns4.5000
5/12
M74HC4094
CAPACITIVE CHARACTERISTICS
Test ConditionValue
SymbolParameter
C
C
Input Capacitance
IN
Power Dissipation
PD
Capacitance (note1)5.0140pF
V
CC
(V)
5.05101010pF
= 25°C
T
A
-40 to 85°C -55 to 125°C
Min.Typ. Max.Min. Max. Min.Max.
Unit
1) CPDis defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
FLOP)
CC(opr)=CPDxVCCxfIN+ICC
/2(perFLIP/
TEST CIRCUIT
TESTSWITCH
t
PLH,tPHL
t
PZL,tPLZ
t
PZH,tPHZ
CL= 50pF/150pF or equivalent (includes jig and probe capacitance)
=1KΩor equivalent
R
1
R
T=ZOUT
of pulse generator (typically 50Ω)
Open
V
CC
GND
6/12
M74HC4094
WAVEFORM 1: PROPAGATION DELAY TI MES, MINIMUM PULSE WIDTH (CLOCK), SE TUP AND
HOLD TIMES (CLOCK) (f=1MHz; 50% duty cycle)
WAVEFORM 2 :PROPAGATION DELAY TIMES, MINIMUM PULSE WIDTH (STROBE), SETUP AND
HOLD TIMES (STROBE)(f=1MHz; 50% duty cycle)
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mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
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