ST M74HC4094 User Manual

8 BIT SIPO SHIFT LATCH REGISTER (3-STATE)
HIGH SPEED :
f
=80MHz(TYP.)atVCC=6V
MAX
LOW POWER DISSIPATION:
I
=4µA(MAX.) at TA=25°C
CC
HIGH NOISE IMMUNITY:
V
NIH=VNIL
SYMMETRICAL OUTPUT IMPEDANCE:
|I
|=IOL=4mA(MIN)
OH
BALANCED PROPAGATION DELAYS:
t
t
PLH
WIDE OPERATING VOLTAGE RANGE:
V
(OPR) = 2 V to 6V
CC
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 4094
DESCRIPTION
The M74HC4094 is an high speed CMOS 8 BIT SIPO SHIFT LATCH REGISTER fabricated with silicon gate C This device consists of an 8 bit shift register and an 8 bit latch with 3 state output buffer. Data is shifted serially trough the shift register on the positive going transition of the clock input signal. Theoutputofthelaststage(Qs)canbeusedto cascade several devices. Data on the Qs out put is transferred to a second output (Qs’) on the following negative transition of
=28%VCC(MIN.)
PHL
2
MOS technology.
M74HC4094
TSSOPDIP SOP
ORDER CODES
PACKAGE TUBE T & R
DIP M74HC4094B1R
SOP M74HC4094M1R M74HC4094RM13TR
TSSOP M74HC4094TTR
the clock input sig nal. The data of each stage of the s hift register is provided with a latch, which latches data on the negativ e going transition of the STROBE input signal. When the STROBE input is held high, data propagates through the latch to a 3-state output buffer. This buffer is enabled when OUT PUT ENA BLE input is taken high. All inputs are equipped with protection circuits against static discharge and transient excess voltage.
PIN CONNE CTION AND IEC LOGIC SYMBOLS
1/12January 2003
M74HC4094
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No SYMBOL NAME AND FUNCTION
1 STROBE Strobe Input 2 SERIAL IN Serial Input 3 CLOCK Clock Input
4, 5, 6, 7, 14,
13, 12, 11
9, 10 QS Q’S Serial Outputs
15 OE Output Enable Input
8 GND Ground (0V)
16 Vcc Positive Supply Voltage
TRUTH TABLE
Q1 to Q7 Parallel Outputs
CK OE ST SI
H H L L Qn-1 Q7 NC HHHHQn-1 Q7 NC HLXNCNCQ7NC
LXXZZNCQ8
H H H NC NC NC Q8
LXXZZQ7NC
X : Don’t Care Z : High Impedance NC: NoChange
LOGIC DIAGRAM
PARALLEL OUTPUTS SERIAL OUTPUTS
Q1 Qn Qs Qs’
This logic diagram has not be used to estimate propagation delays
2/12
TIMING CHART
M74HC4094
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
V
V
I
IK
I
OK
I
or I
I
CC
P
T
stg
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied (*) 500mWat 65
Supply Voltage DC Input Voltage -0.5 to VCC+ 0.5
I
DC Output Voltage -0.5 to VCC+ 0.5
O
DC Input Diode Current DC Output Diode Current DC Output Current
O
DC VCCor Ground Current
GND
Power Dissipation
D
Storage Temperature Lead Temperature (10 sec)
L
°C; derate to 300mW by 10mW/°Cfrom65°Cto85°C
-0.5 to +7 V V V
± 20 mA ± 20 mA ± 25 mA ± 50 mA
500(*) mW
-65 to +150 °C 300 °C
3/12
M74HC4094
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Value Unit
V
CC
V V T
t
r,tf
DC SPECIFICATIONS
Symbol Parameter
V
IH
V
IL
V
OH
V
OL
I
I
I
OZ
I
CC
Supply Voltage Input Voltage 0 to V
I
Output Voltage 0 to V
O
Operating Temperature
op
Input Rise and Fall Time VCC= 2.0V
= 4.5V
V
CC
= 6.0V
V
CC
Test Condition Value
= 25°C
T
A
Min. Typ. Max. Min. Max. Min. Max.
High Level Input
V
CC
(V)
2.0 1.5 1.5 1.5
Voltage
6.0 4.2 4.2 4.2
Low Level Input
2.0 0.5 0.5 0.5
Voltage
6.0 1.8 1.8 1.8
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
High Impedance Output Leakage Current
Quiescent Supply Current
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
6.0
IO=-20 µA I
=-20 µA
O
=-20 µA
I
O
=-4.0 mA
I
O
=-5.2 mA
I
O
IO=20 µA I
=20 µA
O
=20 µA
I
O
=4.0 mA
I
O
=5.2 mA
I
O
I=VIH
or GND
or V
IL
V
I=VCC
V
VO=VCCor GND
V
I=VCC
or GND
1.9 2.0 1.9 1.9
4.4 4.5 4.4 4.4
5.9 6.0 5.9 5.9
4.18 4.31 4.13 4.10
5.68 5.8 5.63 5.60
0.0 0.1 0.1 0.1
0.0 0.1 0.1 0.1
0.0 0.1 0.1 0.1
0.17 0.26 0.33 0.40
0.18 0.26 0.33 0.40
± 0.1 ± 1 ± 1 µA
± 0.5 ± 5 ± 10 µA
44080µA
2to6 V
CC CC
-55 to 125 °C 0 to 1000 ns
0 to 500 ns 0 to 400 ns
-40 to 85°C -55 to 125°C
V V
Unit
V4.5 3.15 3.15 3.15
V4.5 1.35 1.35 1.35
V
V
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AC ELECTRICAL C HARACTERISTICS (CL= 50 pF, Input tr=tf=6ns)
Test Condition Value
= 25°C
Symbol Parameter
t
TLHtTHL
t
PLHtPHL
Output Transition Time
Propagation Delay Time (CLOCK - Qn)
t
PLHtPHL
Propagation Delay Time (CLOCK - QS, Q’S)
t
PLHtPHL
Propagation Delay Time (STROBE - Qn)
t
PZLtPZH
High Impedance Output Enable Time
t
PHZtPLZ
High Impedance Output Disable Time
f
t
W(H)
t
t
MAX
W(L)
W(L)
t
s
Maximum Clock Frequency
Minimum Pulse Width
Minimum Pulse Width
Minimum Set-up Time (SERIAL INPUT)
t
Minimum Set-up
s
Time (STROBE)
Minimum Hold
t
h
Time (SI, ST)
V
CC
(V)
2.0 30 75 95 115
6.0 7 13 16 20
2.0 92 200 250 300
6.0 20 34 43 51
2.0 65 150 190 225
6.0 15 26 32 38
2.0 75 160 200 240
6.0 16 27 34 41
2.0 58 150 190 225
6.0 13 26 32 38
2.0 35 150 190 225
6.0 13 26 32 38
2.0 6 16 4.8 4
6.0 35 80 28 24
2.0 17 75 95 110
6.0 6 13 16 19
2.0 28 75 95 110
6.0 6 13 16 19
2.0 30 75 95 110
6.0 5 13 16 19
2.0 45 100 125 145
6.0 8 17 21 25
2.0 0 0 0
6.0 0 0 0
T
A
Min. Typ. Max. Min. Max. Min. Max.
M74HC4094
-40 to 85°C -55 to 125°C
Unit
ns4.5 8 15 19 23
ns4.5 26 40 50 60
ns4.5 19 30 38 45
ns4.5 20 32 40 48
ns4.5 16 30 38 45
ns4.5 16 30 38 45
MHz4.5 30 66 24 20
ns4.5 7 15 19 22
ns4.5 6 15 19 22
ns4.5 7 15 19 22
ns4.5 10 20 25 29
ns4.5 0 0 0
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M74HC4094
CAPACITIVE CHARACTERISTICS
Test Condition Value
Symbol Parameter
C
C
Input Capacitance
IN
Power Dissipation
PD
Capacitance (note1)5.0 140 pF
V
CC
(V)
5.0 5 10 10 10 pF
= 25°C
T
A
-40 to 85°C -55 to 125°C
Min. Typ. Max. Min. Max. Min. Max.
Unit
1) CPDis defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I FLOP)
CC(opr)=CPDxVCCxfIN+ICC
/2(perFLIP/
TEST CIRCUIT
TEST SWITCH
t
PLH,tPHL
t
PZL,tPLZ
t
PZH,tPHZ
CL= 50pF/150pF or equivalent (includes jig and probe capacitance)
=1KΩor equivalent
R
1
R
T=ZOUT
of pulse generator (typically 50)
Open
V
CC
GND
6/12
M74HC4094
WAVEFORM 1: PROPAGATION DELAY TI MES, MINIMUM PULSE WIDTH (CLOCK), SE TUP AND HOLD TIMES (CLOCK) (f=1MHz; 50% duty cycle)
WAVEFORM 2 :PROPAGATION DELAY TIMES, MINIMUM PULSE WIDTH (STROBE), SETUP AND HOLD TIMES (STROBE)(f=1MHz; 50% duty cycle)
7/12
M74HC4094
WAVEFORM 3 : OUTPUT ENABLE AND DISABLE TIMES(f=1MHz; 50% duty cycle)
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M74HC4094
Plastic DIP-16 (0.25) MECHANICAL DATA
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
a1 0.51 0.020
B 0.77 1.65 0.030 0.065
b 0.5 0.020
b1 0.25 0.010
D 20 0.787 E 8.5 0.335
e 2.54 0.100
e3 17.78 0.700
F 7.1 0.280
I 5.1 0.201
L 3.3 0.130
Z 1.27 0.050
P001C
9/12
M74HC4094
SO-16 MECHANICAL DATA
DIM.
A 1.75 0.068 a1 0.1 0.2 0.004 0.008 a2 1.65 0.064
b 0.35 0.46 0.013 0.018
b1 0.19 0.25 0.007 0.010
C 0.5 0.019 c1 45˚ (typ.)
D 9.8 10 0.385 0.393
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 8.89 0.350
F 3.8 4.0 0.149 0. 157
G 4.6 5.3 0.181 0. 208
L 0.5 1.27 0.019 0.050 M 0.62 0.024 S8 ˚ (max.)
MIN. TYP MAX. MIN. TYP. MAX.
mm. inch
10/12
PO13H
M74HC4094
TSSOP16 MECHANICAL DATA
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 1.2 0.047
A1 0.05 0.15 0.002 0.004 0.006
A2 0.8 1 1.05 0.031 0.039 0.041
b 0.19 0.30 0.007 0.012
c 0.09 0.20 0.004 0.0079
D 4.9 5 5.1 0.193 0.197 0.201
E 6.2 6.4 6.6 0.244 0.252 0.260
E1 4.3 4.4 4.48 0.169 0.173 0.176
e 0.65 BSC 0.0256 BSC
K0˚ 8˚0˚ 8˚
L 0.45 0.60 0.75 0.018 0.024 0.030
A2
A
A1
b
e
c
K
L
E
D
E1
PIN 1 IDENTIFICATION
1
0080338D
11/12
M74HC4094
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use o f suc h inf ormat ion n or f or an y infr ingeme nt of paten ts or oth er ri gh ts of third part ies whic h may resul t f rom its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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