ST M74HC390 User Manual

Features

■ HIgh Speed:

f

= 79MHz (Typ.) at VCC = 6V

MAX

■ Low power dissipation:

I

= 4µA (Max.) at TA = 25°C

CC

■ High noise immunity:

V

= V

NIH

■ Balanced propagation delays:

t

≅ t

PLH

■ Wide operating voltage range:

V

(Opr) = 2V to 6V

CC

■ Pin and function compatible with 74 series 390

= 28 % VCC (Min.)

NIL

PHL

Description

The M74HC390 is an high speed CMOS dual
decade counter fabricated with silicon gate
C2MOS technology.

This dual decade counter contains two
independent ripple carry counters. Each counter
is composed of a divide by two and divide by five
counter. The divide by two and divide by five
counters can be cascaded to form dual decade,
dual biquinary, or various combination up to a
single divide by 100 counter.

M74HC390

Dual decade counter

DIP-16 SO-16

Each 4-bit counter is increased on the high to low
transition (negative edge) of the clock input, and
each has an independent clear input. When clear
is set low all four bits of each counter are set to
low. This enables count truncation and allows the
implementation of divide by N counter
configuration.

All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.

Order codes

Part number Package Packaging

M74HC390B1R DIP-14 Tube

M74HC390RM13TR SO-14 Tape and reel

July 2006 Rev 2 1/17

www.st.com

17

Contents M74HC390

Contents

1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

4 Block and logic diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

5 Timing chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

6 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

6.1 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

8 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

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M74HC390 Pin settings

1 Pin settings

1.1 Pin connection

Figure 1. Pin connection (top through view)

1.2 Pin description

Table 1. Pin description

Pin N° Symbol Name and function

1, 15

2, 14

3, 5, 6, 7 1QA to 1QD Flip flop outputs

4, 12

13, 11, 10, 9 2QA to 2QD Flip flop outputs

8 GND Ground (0V)

16 Vcc Positive supply voltage

1 CLOCK A
2 CLOCK B

1 CLEAR
2 CLEAR

1 CLOCK A
2 CLOCK B

Clock input divide by 2 section (HIGH to LOW Edge-Triggered)

Asynchronous master reset inputs

Clock input divide by 5 section (HIGH to LOW Edge-Triggered)

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Device summary M74HC390

2 Device summary

Figure 2. IInput and output equivalent circuit

Figure 3. Logic diagram

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M74HC390 Truth table

3 Truth table

Table 2. Truth table

Outputs

COUNT

QD QC QB QA QA QD QC QB

0 LLLLLLLL

1 LLLHLLLH

2 LLHLLLHL

3 LLHHLLHH

4LHLLLHLL

5LHLHHHLL

6LHHLHLLH

7 LHHHHLHL

8 HLLLHLHH

9HLLHHHLL

BCD COUNT

(1)

BI-QUINARY

(2)

1. Output QA is connected to input CLOCK B for BCD count.

2. Output QD is connected to input CLOCK A for bi-quinary count.

Table 3. Truth table

Inputs Outputs

CLOCK A CLOCK B CLEAR QA QB QC QD

X X H LLLL

X L BINARY COUNT UP

X L QUINARY COUNT UP

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Block and logic diagrams M74HC390

4 Block and logic diagrams

Figure 4. Block diagram

Figure 5. Logic diagram

Note: This logic diagram has not be used to estimate propagation delays

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