ST M74HC299 User Manual

M74HC299

8 BIT PIPO SHIFT REGISTER

WITH ASYNCHRONOUS CLEAR

■ HIGH SPEED :

f

= 80MHz (TYP.) at VCC = 6V

MAX

■ LOW POWER DISSIPATION:

I

=4µA(MAX.) at TA=25°C

CC

■ HIGH NOISE IMMUNITY:

V

= V

NIH

■ SYMMETRICAL OUTPUT IMPEDANCE:

|I

| = IOL = 6mA (MIN) FOR Q A’ TO QH’

OH

|I

| = IOL = 4mA (MIN) FOR QA TO QH

OH

■ BALANCED PROPAGATION DELAYS:

t

≅ t

PLH

■ WIDE OPERATING VOLTAGE RANGE:

V

(OPR) = 2V to 6V

CC

■ PIN AND FUNCTION COMPATIBLE WITH

= 28 % VCC (MIN.)

NIL

PHL

74 SERIES 299

DESCRIPTION

The M74HC299 is an high speed CMOS 8 BIT
PIPO SHIFT REGISTER (3-STATE) fabricated
with silicon gate C

2

MOS technology.
This device has four modes (HOLD, SHIFT LEFT,
SHIFT RIGHT and LOAD DA TA). Each mode is
chosen by two function select inputs (S0, S1).
When one or both enable inputs, (G1

, G2) are

TSSOPDIP SOP

ORDER CODES

PACKAGE TUBE T & R

DIP M74HC299B1R

SOP M74HC299M1R M74HC299RM13TR

TSSOP M74HC299TTR

high, the eight input/output terminals are in the
high impedance state; however sequential
operation or clearing of the register is not affected.
Clear function on the M74HC299 is asynchronous
to CLOCK.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

1/13July 2001

M74HC299

IINPUT AND OUTPUT EQUIVALENT CIRCUIT

PIN DESCRIPTION

PIN No SYMBOL NAME AND FUNCTION

1, 19 S0, S1 Mode Select Inputs

2, 3 G1

7, 13, 6, 14, 5, 15, 4, 16 A/QA to H/QH Parallel Data Inputs or 3-State Parallel Outputs (Bus Driver)

8, 17 QA’ to QH’ Serial Outputs (Standard Output)

9 CLEAR
11 SR Serial Data Shift Right Input
12 CLOCK Clock Input (LOW to HIGH, Edge-triggered)
18 SL Serial Data Shift Left Input
10 GND Ground (0V)
20 V

, G2 3-State Output Enable Inputs (Active LOW)

Asynchronous Master Reset Input (Active LOW)

CC

Positive Supply Voltage

TRUTH TABLE

INPUTS INPUTS/OUTPUTS OUTPUTS

MODE

CLEAR

FUNCTION

SELECTED

S1 S0 G1

ZLHHXXXXXZZLL

CLEAR

L L X L L X X XLLLL
L X L L L X X XLLLL

HOLD H L L L L X X X QA0 QH0 QA0 QH0
SHIFT

RIGHT

SHIFT

LEFT

H L H L L X H H QGn H QGn
H L H L L X L L QGn L QGn
H H L L L H X QBnHQBnH
H H L L L L X QBnLQBnL

LOADH H H X X X Xahah

* When one or both output controls are high, the eight input/output terminals are in the high impedance state: however sequential operation
or clearing of the register is not affected.
Z : High Impedance
Qn0 : The level of An befor e the indicated steady state input conditions were established.
Qnn : The level of Qn before the most recent active transition indicated by OR
a, h : The lev el of the steady s tate inputs A, H, respecti vely.

X : Don’t Care

2/13

OUTPUT

CONTROL

CLOCK

SERIAL

A/QA H/QH QA’ QH’

*G2*SLSR

LOGIC DIAGRAM

M74HC299

3/13

M74HC299

TIMING CHART

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V

V

V

I

I

OK

I
I

I

or I

CC

P

T

T

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not t implied
(*) 500mW at 65

Supply Voltage

CC

DC Input Voltage -0.5 to VCC + 0.5

I

DC Output Voltage -0.5 to VCC + 0.5

O

DC Input Diode Current

IK

DC Output Diode Current
DC Output Source Sink Current Per Output Pin (QA-QH)

O

DC Output Source Sink Current Per Output Pin (QA’-QH’)

O

DC VCC or Ground Current

GND

Power Dissipation

D

Storage Temperature

stg

Lead Temperature (10 sec)

L

°C; derate to 300mW by 10mW/°C from 65°C to 85°C

-0.5 to +7 V
V
V

± 20 mA
± 20 mA
± 35 mA

± 235 mA

± 70 mA

500(*) mW

-65 to +150 °C
300 °C

4/13