The M74HC259 is an high speed CMOS 8 BIT
ADDRESSABLE LATCH fabricated with silicon
gate C
2
MOS technology.
The M74HC259 has single data input (D) 8 latch
outputs (Q0-Q7), 3 a ddress inputs (A, B, and C),
common enable input (E), and a comm on CLE AR
input. To operate t his de vi ce as an addressable
latch, data is held on the D input, and the address
of the latch into which the data is to be entered is
held on the A, B, and C inputs. When ENABLE
is
taken low the data flows through to the addresses
output. The data is stored on the positive-going
edge of the ENABLE
latches will remain unaffected. With ENABLE
pulse. All unaddressed
in
the high state the device is deselected and all
TSSOPDIPSOP
ORDER CODES
PACKAGETUBET & R
DIPM74HC259B1R
SOPM74HC259M1RM74HC259RM13TR
TSSOPM74HC259TTR
latches remain in their previous state, unaffect ed
by changes on the data or address inputs. To
eliminate the possibility of entering erroneous data
into the latches, th e EN A BLE
should be held high
(inactive) while the address lines are changing. If
ENABLE
is held high and CLEAR is taken l ow all
eight latches are cleared to the low state. If
ENABLE
is low all latches except the addres sed
latch will be cleared. The addressed latch will
instead follow the D input, effectively
implementing a 3-to-8 line decoder.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/13July 2001
M74HC259
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN NoSYMBOLNAME AND FUNCTION
1, 2, 3A, B, CAddress Inputs
4, 5, 6, 7, 9,
10, 11, 12
13DData Input
14ENABLE
15CLEAR
8GNDGround (0V)
16VccPositive Supply Voltage
TRUTH TABLE
Q0 to Q7Latch Outputs
Latch Enable Input (Active
Low)
Conditional Reset Input
(Low)
INPUTS
CLEAR
HLDQi0ADDRESSABLE LATCH
HHQi0Qi0MEMORY
LLDL8 LINE DEMULTIPLEXER
LHLLCLEAR ALL BITS TO ’L’
D : The level at the data input
Qi0 : The level before the indicated steady state input conditions where established, (i = 0, 1, ......., 7).
ENABLE
CBA
LLLQ0
LLHQ1
LHLQ2
LHHQ3
HLLQ4
HLHQ5
HHLQ6
HHHQ7
OUTPUTS OF
ADDRESSED LATCH
SELECT INPUTS
EACH OTHER OUTPUTFUNCTION
LATCH ADDRESSED
2/13
LOGIC DIAGRAM
M74HC259
This log i c diagram has not be used to est i m at e propagation delays
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
V
V
I
I
OK
I
I
or I
CC
P
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65
WAVEFORM 5 : SETUP AND HOLD TIME (f=1MHz; 50% duty cycle)
8/13
WAVEFOR M 6 : I N P U T WA VEFORMS (f=1MHz; 50% duty cycle)
M74HC259
9/13
M74HC259
Plastic DIP-16 (0.25) MECHANICAL DATA
mm.inch
DIM.
MIN.TYPMAX.MIN.TYP.MAX.
a10.510.020
B0.771.650.0300.065
b0.50.020
b10.250.010
D200.787
E8.50.335
e2.540.100
e317.780.700
F7.10.280
I5.10.201
L3.30.130
Z1.270.050
10/13
P001C
SO-16 MECHANICAL DATA
M74HC259
DIM.
A1.750.068
a10.10.20.0030.007
a21.650.064
b0.350.460.0130.018
b10.190.250.0070.010
C0.50.019
c145° (typ.)
D9.8100.3850.393
E5.86.20.2280.244
e1.270.050
e38.890.350
F3.84.00.1490.157
G4.65.30.1810.208
L0.51.270.0190.050
M0.620.024
S8° (max.)
MIN.TYPMAX.MIN.TYP.M AX.
mm.inch
PO13H
11/13
M74HC259
TSSOP16 MECHANICAL DATA
mm.inch
DIM.
MIN.TYPMAX.MIN.TYP.M AX.
A1.20.047
A10.050.150.0020.0040.006
A20.811.050.0310.0390.041
b0.190.300.0070.012
c0.090.200.0040.0089
D4.955.10.1930.1970.201
E6.26.46.60.2440.2520.260
E14.34.44.480.1690.1730.176
e0.65 BSC0.0256 BSC
K0°8°0°8°
L0.450.600.750.0180.0240.030
A2
A
A1
b
e
c
K
L
E
D
E1
PIN 1 IDENTIFICATION
12/13
1
0080338D
M74HC259
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