M74HC175
QUAD D-TYPE FLIP FLOP WITH CLEAR
■HIGH SPEED :
tPD = 16 ns (TYP.) at VCC = 6V
■LOW POWER DISSIPATION: ICC =4μA(MAX.) at TA=25°C
■HIGH NOISE IMMUNITY: VNIH = VNIL = 28 % VCC (MIN.)
■SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN)
■BALANCED PROPAGATION DELAYS: tPLH tPHL
■WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V
■PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 175
DESCRIPTION
The M74HC175 is an high speed CMOS HEX D-TYPE FLIP FLOP WITH CLEAR fabricated with silicon gate C2MOS technology.
These four flip-flops are controlled by a clock input (CLOCK) and a clear input (CLEAR). The information data applied to the D inputs (1D to 4D) are transferred to the outputs (1Q to 4Q and 1Q to
DIP |
SOP |
TSSOP |
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ORDER CODES |
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PACKAGE |
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TUBE |
T & R |
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DIP |
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M74HC175B1R |
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SOP |
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M74HC175M1R |
M74HC175RM13TR |
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TSSOP |
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M74HC175TTR |
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4Q) on the positive-going edge of the clock pulse. The reset function is accomplished when the CLEAR input is low and all Q outputs are low regardless of other input conditions.
All inputs are equipped with protection circuits against static discharge and transient excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
July 2001 |
1/11 |
M74HC175
INPUT AND OUTPUT EQUIVALENT CIRCUIT |
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PIN DESCRIPTION |
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PIN No |
SYMBOL |
NAME AND FUNCTION |
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1 |
CLEAR |
Asynchronous Master |
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Reset (Active Low) |
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2, 7, 10, 15 |
1Q to 4Q |
Flip-Flop Outputs |
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3, 6, 11, 14 |
1Q to 4Q |
Complementary Flip-Flop |
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Outputs |
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4, 5, 12, 13 |
1D to 4D |
Data Inputs |
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9 |
CLOCK |
Clock Input (LOW to |
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HIGH, edge triggered) |
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8 |
GND |
Ground (0V) |
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16 |
Vcc |
Positive Supply Voltage |
TRUTH TABLE |
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INPUTS |
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OUTPUTS |
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FUNCTION |
CLEAR |
D |
CLOCK |
Q |
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Q |
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L |
X |
X |
L |
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H |
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H |
L |
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L |
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H |
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H |
H |
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H |
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L |
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H |
X |
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Qn |
Qn |
NO CHANGE |
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X : Don’t Care |
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LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
2/11
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M74HC175 |
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ABSOLUTE MAXIMUM RATINGS |
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Symbol |
Parameter |
Value |
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Unit |
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VCC |
Supply Voltage |
-0.5 to +7 |
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V |
VI |
DC Input Voltage |
-0.5 to VCC + 0.5 |
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V |
VO |
DC Output Voltage |
-0.5 to VCC + 0.5 |
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V |
IIK |
DC Input Diode Current |
± 20 |
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mA |
IOK |
DC Output Diode Current |
± 20 |
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mA |
IO |
DC Output Current |
± 25 |
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mA |
ICC or IGND |
DC VCC or Ground Current |
± 50 |
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mA |
PD |
Power Dissipation |
500(*) |
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mW |
Tstg |
Storage Temperature |
-65 to +150 |
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°C |
TL |
Lead Temperature (10 sec) |
300 |
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°C |
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
RECOMMENDED OPERATING CONDITIONS
Symbol |
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Parameter |
Value |
Unit |
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VCC |
Supply Voltage |
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2 to 6 |
V |
VI |
Input Voltage |
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0 to VCC |
V |
VO |
Output Voltage |
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0 to VCC |
V |
Top |
Operating Temperature |
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-55 to 125 |
°C |
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Input Rise and Fall Time |
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VCC = 2.0V |
0 to 1000 |
ns |
tr, tf |
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VCC = 4.5V |
0 to 500 |
ns |
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VCC = 6.0V |
0 to 400 |
ns |
3/11
M74HC175
DC SPECIFICATIONS
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Test Condition |
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Value |
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Symbol |
Parameter |
VCC |
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TA = 25°C |
-40 to 85°C |
-55 to 125°C |
Unit |
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(V) |
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Min. |
Typ. |
Max. |
Min. |
Max. |
Min. |
Max. |
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VIH |
High Level Input |
2.0 |
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1.5 |
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1.5 |
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1.5 |
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Voltage |
4.5 |
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3.15 |
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3.15 |
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3.15 |
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V |
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6.0 |
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4.2 |
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4.2 |
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4.2 |
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VIL |
Low Level Input |
2.0 |
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0.5 |
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0.5 |
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0.5 |
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Voltage |
4.5 |
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1.35 |
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1.35 |
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1.35 |
V |
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6.0 |
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1.8 |
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1.8 |
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1.8 |
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VOH |
High Level Output |
2.0 |
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IO=-20 μA |
1.9 |
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2.0 |
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1.9 |
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1.9 |
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Voltage |
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4.5 |
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IO=-20 μA |
4.4 |
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4.5 |
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4.4 |
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4.4 |
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6.0 |
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IO=-20 μA |
5.9 |
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6.0 |
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5.9 |
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5.9 |
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V |
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4.5 |
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IO=-4.0 mA |
4.18 |
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4.31 |
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4.13 |
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4.10 |
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6.0 |
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IO=-5.2 mA |
5.68 |
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5.8 |
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5.63 |
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5.60 |
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VOL |
Low Level Output |
2.0 |
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IO=20 μA |
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0.0 |
0.1 |
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0.1 |
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0.1 |
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Voltage |
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4.5 |
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IO=20 μA |
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0.0 |
0.1 |
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0.1 |
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0.1 |
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6.0 |
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IO=20 μA |
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0.0 |
0.1 |
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0.1 |
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0.1 |
V |
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4.5 |
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IO=4.0 mA |
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0.17 |
0.26 |
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0.33 |
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0.40 |
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6.0 |
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IO=5.2 mA |
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0.18 |
0.26 |
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0.33 |
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0.40 |
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II |
Input Leakage |
6.0 |
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VI = VCC or GND |
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± 0.1 |
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± 1 |
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± 1 |
μA |
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Current |
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ICC |
Quiescent Supply |
6.0 |
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VI = VCC or GND |
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4 |
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40 |
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80 |
μA |
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Current |
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4/11