ST M74HC165 User Manual
Features
■ High speed:
–t
= 15 ns (typ.) at VCC = 6 V
PD
■ Low power dissipation:
–I
= 4 μA (max.) at TA = 25 °C
CC
■ High noise immunity:
V
= V
NIH
■ Symmetrical output impedance:
|I
| = IOL = 4 mA (min)
OH
■ Balanced propagation delays:
t
≅ t
PLH
■ Wide operating voltage range:
V
(opr) = 2 V to 6 V
CC
■ Pin and function compatible with
74 series 165
Table 1. Device summary
= 28 % VCC (Min.)
NIL
PHL
M74HC165
8-bit PISO shift register
SO-16
DIP-16
TSSOP16
Description
The M74HC165 is a high speed CMOS 8-bit
PISO (parallel-in-serial-out) shift register
fabricated with silicon gate C
This device contains eight clocked master slave
RS flip-flops connected as a shift register, with
auxiliary gating to provide overriding
asynchronous parallel entry. The parallel data
enter when the shift/load
change while shift/load
recommended set-up and hold times are
observed. For clocked operation, shift/load
be high. The two clock inputs perform identically:
one can be used as a clock inhibit by applying a
high signal, to allow this operation clocking is
accomplished through a 2-input nor gate . To avoid
double clocking, however, the inhibit signal should
only go high while the clock is high. Otherwise the
rising inhibit signal causes the same response as
rising clock edge. All inputs are equipped with
protection circuits against static discharge and
transient excess voltage.
2
MOS technology.
input is low and can
is low, provided that the
must
Order code Package Packaging
M74HC165B1R DIP-16 Tube
M74HC165RM13TR SO-16 Tape and reel
M74HC165TTR TSSOP16 Tape and reel
May 2008 Rev 5 1/21
www.st.com
21
Contents M74HC165
Contents
1 Logic symbols and I/O equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Logic states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.3 Timing chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2/21
M74HC165 Logic symbols and I/O equivalent circuit
1 Logic symbols and I/O equivalent circuit
Figure 1. IEC logic symbols
Figure 2. Input and output equivalent circuit
3/21
Pin settings M74HC165
2 Pin settings
2.1 Pin connection
Figure 3. Pin connection (top through view)
2.2 Pin description
Table 2. Pin description
Pin number Symbol Name and function
1SHIFT/LOADData inputs
2 CLOCK Clock input (low to high, edge triggered)
7QHComplementary output
9 QH Serial output
10 SI Serial input
11, 12, 13, 14, 3, 4, 5, 6 A to H Parallel data inputs
15 CLOCK INH Clock inhibit
8 GND Ground (0 V)
16 V
CC
Positive supply voltage
4/21
M74HC165 Logic states
3 Logic states
3.1 Truth table
Table 3. Truth table
Inputs Internal outputs Outputs
Shift
/Load
L X X X a..........h a b h
HL HXHQAnQGn
HL LXLQAnQGn
HLHXHQAnQGn
HLLXLQAnQGn
H X H X X No change
H H X X X No change
Clock INH Clock SI A..........H QA QB QH
Note: a........h : the level of steady input voltage at inputs a through respectively QAn - QGn : the
level of QA - QG, respectively. Before the most recent transition of the clock.
3.2 Logic diagram
Figure 4. Logic diagram
Note: This logic diagram has not to be use d to estimate propagation delays
5/21
Logic states M74HC165
3.3 Timing chart
Figure 5. Timing chart
6/21
M74HC165 Maximum rating
4 Maximum rating
Stressing the device above the rating listed in the “absolute maximum ratings” table may
cause permanent damage to the device. these are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. exposure to absolute maximum rating conditions for
extended periods may aff ect device reliability. refer also to the STMicroelectronics sure
program and other relevant quality documents.
Table 4. Absolute maximum ratings
Symbol Parameter Value Unit
V
V
I
ICC or
I
GND
P
T
1. (*) 500mW at 65 ° C; derate to 300 mW by 10 mW/° C from 65°C to 85° C
Supply voltage -0.5 to +7 V
CC
V
DC input voltage -0.5 to VCC + 0.5 V
I
DC output voltage -0.5 to VCC + 0.5 V
O
I
DC input diode current ± 20 mA
IK
DC output diode current ± 20 mA
OK
I
DC output current ± 25 mA
O
DC VCC or ground current ± 50 mA
Power dissipation 500
D
Storage temperature -65 to +150 °C
stg
T
Lead temperature (10 sec) 300 °C
L
(1)
mW
4.1 Recommended operating conditions
Table 5. Recommended operating conditions
Symsbol Parameter Value Unit
V
V
V
T
t
r
Supply voltage 2 to 6 V
CC
Input voltage 0 to V
I
Output voltage 0 to V
O
Operating temperature -55 to 125 °C
op
, t
Input rise and fall time
f
7/21
CC
CC
V
= 2.0 V 0 to 1000 ns
CC
= 4.5 V 0 to 500 ns
V
CC
V
= 6.0 V 0 to 400 ns
CC
V
V
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