M74HC163
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
■ HIGH SPEED :
f
= 62 MHz (TYP.) at VCC = 6V
MAX
■ LOW POWER DISSIPATION:
I
=4µA(MAX.) at TA=25°C
CC
■ HIGH NOISE IMMUNITY:
V
= V
NIH
■ SYMMETRICAL OUTPUT IMPEDANCE:
|I
| = IOL = 4mA (MIN)
OH
■ BALANCED PROPAGATION DELAYS:
t
≅ t
PLH
■ WIDE OPERATING VOLTAGE RANGE:
V
(OPR) = 2V to 6V
CC
■ PIN AND FUNCTION COMPATIBLE WITH
= 28 % VCC (MIN.)
NIL
PHL
74 SERIES 163
DESCRIPTION
The M74HC163 is an high speed CMOS
SYNCHRONOUS 4 BIT BINARY PRESETTABLE
COUNTER fabricated with silicon gate C
2
MOS
technology.
The CLOCK input is active on the rising edge.
Both LOAD
and CLEAR input s are active LOW.
Presetting is synchronous on the rising edge of
the clock, the function is synchronous to the
TSSOPDIP SOP
ORDER CODES
PACKAGE TUBE T & R
DIP M74HC163B1R
SOP M74HC163M1R M74HC163RM13TR
TSSOP M74HC163TTR
CLOCK. Two enable inputs (TE and PE) and
CARRY output are provided to enable easy
cascading of counters, which facilities easy
implementation of N-bit counters without using
external gates.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/12July 2001
M74HC163
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No SYMBOL NAME AND FUNCTION
1 CLEAR
2 CLOCK
3, 4, 5, 6 A, B, C, D Data Inputs
7 PE Count Enable Input
10 TE Count Enable Carry Input
9LOAD
14, 13, 12,
11
15 CARRY Terminal Count Output
8 GND Ground (0V)
16 Vcc Positive Supply Voltage
TRUTH TABLE
QA to QD Flip Flop Outputs
Asynchronous Master
Reset
Clock Input (LOW to
HIGH, Edge-trigge red)
Parallel Enable Input
INPUTS OUTPUTS
FUNCTION
CLEAR
LOAD PE TE CLOCK QA QB QC QD
L X X X L L L L RESET TO "0"
H L X X A B C D PRESET DATA
H H X L NO CHANGE NO COUNT
H H L X NO CHANGE NO COUNT
H H H H COUNT UP COUNT
H X X X NO CHANGE NO COUNT
X : Don’t Care
A, B, C, D : Logic level of data inputs
Carry : CARRY = TE·Q
A·QB·QC·QD
LOGIC DIAGRAM
This log i c diagram has not be used to est i m at e propagation delays
2/12
TIMING CHART
M74HC163
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
V
V
I
I
OK
I
I
or I
CC
P
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65
Supply Voltage
CC
DC Input Voltage -0.5 to VCC + 0.5
I
DC Output Voltage -0.5 to VCC + 0.5
O
DC Input Diode Current
IK
DC Output Diode Current
DC Output Current
O
DC VCC or Ground Current
GND
Power Dissipation
D
Storage Temperature
stg
Lead Temperature (10 sec)
L
°C; derate to 300mW by 10mW/°C from 65°C to 85°C
-0.5 to +7 V
V
V
± 20 mA
± 20 mA
± 25 mA
± 50 mA
500(*) mW
-65 to +150 °C
300 °C
3/12
M74HC163
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Value Unit
V
V
V
T
t
r
DC SPECIFICATIONS
Symbol Parameter
V
IH
V
IL
V
OH
V
OL
I
I
I
CC
Supply Voltage
CC
Input Voltage 0 to V
I
Output Voltage 0 to V
O
Operating Temperature
op
Input Rise and Fall Time VCC = 2.0V
, t
f
V
V
CC
CC
= 4.5V
= 6.0V
Test Condition Value
= 25°C
T
A
Min. Typ. Max. Min. Max. Min. Max.
High Level Input
V
CC
(V)
2.0 1.5 1.5 1.5
Voltage
6.0 4.2 4.2 4.2
Low Level Input
2.0 0.5 0.5 0.5
Voltage
6.0 1.8 1.8 1.8
High Level Output
Voltage
Low Level Output
Voltage
Input Leakage
Current
Quiescent Supply
Current
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
IO=-20 µA
I
=-20 µA
O
I
=-20 µA
O
I
=-4.0 mA
O
I
=-5.2 mA
O
IO=20 µA
I
=20 µA
O
I
=20 µA
O
I
=4.0 mA
O
I
=5.2 mA
O
= VCC or GND
V
I
= VCC or GND
V
I
1.9 2.0 1.9 1.9
4.4 4.5 4.4 4.4
5.9 6.0 5.9 5.9
4.18 4.31 4.13 4.10
5.68 5.8 5.63 5.60
0.0 0.1 0.1 0.1
0.0 0.1 0.1 0.1
0.0 0.1 0.1 0.1
0.17 0.26 0.33 0.40
0.18 0.26 0.33 0.40
± 0.1 ± 1 ± 1 µA
44080µA
2 to 6 V
CC
CC
-55 to 125 °C
0 to 1000 ns
0 to 500 ns
0 to 400 ns
-40 to 85°C -55 to 125°C
V
V
Unit
V4.5 3.15 3.15 3.15
V4.5 1.35 1.35 1.35
V
V
4/12
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)
Test Condition Value
T
Symbol Parameter
t
TLH tTHL
t
PLH tPHL
Output Transition
Time
Propagation Delay
Time
(CLOCK - Q)
t
PLH tPHL
Propagation Delay
Time
(CLOCK - CARRY)
t
PLH tPHL
Propagation Delay
Time
(TE - CARRY)
agation Delay
t
t
f
MAX
t
W(H)
t
W(L)
3URS
PHL
Time
(CLEAR
Propagation Delay
PHL
Time
(CLEAR
Maximum Clock
Frequency
Minimum Pulse
Width (CLOCK)
Minimum Set-up
t
s
Time
(LOAD
Minimum Set-up
t
s
Time
-Q)
- CARRY)
, PE, TE)
(A, B, C, D)
Minimum Set-up
t
s
Time
(CLEAR
Minimum Hold
t
h
Time
)
(A, B - CLOCK)
t
REM
Minimum Removal
Time
V
CC
(V)
2.0 25 75 95 110
6.0 6131619
2.0 48 125 155 190
6.0 14 21 26 32
2.0 57 150 190 225
6.0 16 26 32 38
2.0 39 100 125 150
6.0 11 17 21 26
2.0 72 200 250 300
6.0 20 34 43 51
2.0 39 100 125 150
6.0 11 17 21 26
2.0 6.2 18 5 4.2
6.0 37 62 30 25
2.0 18 75 95 110
6.0 6131619
2.0 40 100 125 150
6.0 8172126
2.0 20 75 95 110
6.0 3131619
2.0 20 75 95 110
6.0 3131619
2.0 0 0 0
6.0 0 0 0
2.0 18 50 65 75
6.0 3 9 11 13
= 25°C
A
Min. Typ. Max. Min. Max. Min. Max.
M74HC163
-40 to 85°C -55 to 125°C
Unit
ns4.5 7151922
ns4.5 16 25 31 38
ns4.5 19 30 38 45
ns4.5 13 20 25 30
ns4.5 24 40 50 60
ns4.5 13 20 25 30
MHz4.5 31 53 25 21
ns4.5 6151922
ns4.5 10 20 25 30
ns4.5 5151922
ns4.5 5151922
ns4.5 0 0 0
ns4.5 4101315
5/12
M74HC163
CAPACITIVE CHARACTERISTICS
Test Condition Value
T
Symbol Parameter
V
CC
(V)
C
C
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (R ef er to Test Circui t). Averag e operating current can be obtained by the following equation. I
Input Capacitance
IN
Power Dissipation
PD
Capacitance (note 1)5.0 50 pF
5.0 5101010pF
= 25°C
A
Min. Typ. Max. Min. Max. Min. Max.
TEST CIRCUIT
-40 to 85°C -55 to 125°C
= CPD x VCC x fIN + I
CC(opr)
CC
Unit
CL = 50pF or equivalent (includes jig and p robe capacit ance)
R
= Z
of pulse generator (typically 50Ω)
T
OUT
WAVEFORM 1: PROPAGATION DELAY TIMES, MINIMUM PULSE WIDTH (COUNT MODE)
(f=1MHz; 50% duty cycle)
6/12
WAVEFORM 2 : SETUP AND HOLD TIMES (CLEAR MODE) (f=1MHz; 50% duty cycle)
M74HC163
WAVEFORM 3 : SETUP AND HOLD TIMES (PRESET MODE) (f=1MHz; 50% duty cycle)
7/12
M74HC163
WAVEFORM 4 : SETUP AND HOLD TIMES (COUNTENABLE MODE) (f=1MHz; 50% duty cycle )
WAVEFORM 5 : PROPAGATION DELAY TIMES (CASCADE MODE) (f=1MHz; 50% duty cycle)
8/12
M74HC163
Plastic DIP-16 (0.25) MECHANICAL DATA
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
a1 0.51 0.020
B 0.77 1.65 0.030 0.065
b 0.5 0.020
b1 0.25 0.010
D 20 0.787
E 8.5 0.335
e 2.54 0.100
e3 17.78 0.700
F 7.1 0.280
I 5.1 0.201
L 3.3 0.130
Z 1.27 0.050
P001C
9/12
M74HC163
SO-16 MECHANICAL DATA
DIM.
A 1.75 0.068
a1 0.1 0.2 0.003 0.007
a2 1.65 0.064
b 0.35 0.46 0.013 0.018
b1 0.19 0.25 0.007 0.010
C 0.5 0.019
c1 45° (typ.)
D 9.8 10 0.385 0.393
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 8.89 0.350
F 3.8 4.0 0.149 0.157
G 4.6 5.3 0.181 0.208
L 0.5 1.27 0.019 0.050
M 0.62 0.024
S8° (max.)
MIN. TYP MAX. MIN. TYP. MAX.
mm. inch
10/12
PO13H
M74HC163
TSSOP16 MECHANICAL DATA
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 1.2 0.047
A1 0.05 0.15 0.002 0.004 0.006
A2 0.8 1 1.05 0.031 0.039 0.041
b 0.19 0.30 0.007 0.012
c 0.09 0.20 0.004 0.0089
D 4.9 5 5.1 0.193 0.197 0.201
E 6.2 6.4 6.6 0.244 0.252 0.260
E1 4.3 4.4 4.48 0.169 0.173 0.176
e 0.65 BSC 0.0256 BSC
K0° 8°0° 8°
L 0.45 0.60 0.75 0.018 0.024 0.030
A2
A
A1
b
e
c
K
L
E
D
E1
PIN 1 IDENTIFICATION
1
0080338D
11/12
M74HC163
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consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No li cense is granted by imp lication or otherwise under a ny patent or patent rig hts of STMicroelectronics. Spec ific at ions
mentioned in this publication ar e subject to change without notice. This publication supersedes and replaces all information
previously supplied. S TMicroelectronics products are not authorized for use as critica l components in life suppo rt devices or
systems without express written approval of STMicroelectronics.
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12/12
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