ST M54HC137, M74HC137 User Manual
M54HC137
M74HC137
3 TO 8 LINE DECODER/LATCH (INVERTING)
.HIGH SPEED
.tPD = 11 ns (TYP.) AT VCC = 5 V LOW POWER DISSIPATION
.ICC = 4 μA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY
.VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY
.10 LSTTL LOADS
SYMMETRICAL OUTPUT IMPEDANCE
. IOH = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS
.tPLH = tPHL
WIDE OPERATING VOLTAGE RANGE
.VCC (OPR) = 2 V TO 6 V
PIN AND FUNCTION COMPATIBLE WITH 54/74LS137
DESCRIPTION
The M54/74HC137 is a high speed CMOS 3 TO 8LINE DECODER/LATCH (INVERTING) fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. This device is a 3 to 8line decoder withlatches on thethree address inputs. When GLgoes fromlow tohigh, theaddress present at theselect inputs (A, B and C) is stored in the latches. As long as GL remains high no address changes will be recognized. Output enable pins G1 and G2, control the state of the outputs independently of the select or latch-enable inputs. All the outputs are high unless G1 is high and G2 is low. The HC137 is ideally suited for the implementation of glitch-free decoders in stored-address applications in bus oriented systems. All inputs are equipped withprotection circuits against staticdischarge and transient excess voltage.
INPUT AND OUTPUT EQUIVALENT CIRCUIT
B1R |
F1R |
(Plastic Package) |
(Ceramic Package) |
M1R |
C1R |
(Micro Package) |
(Chip Carrier) |
ORDER CODES : |
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M54HC137F1R |
M74HC137M1R |
M74HC137B1R |
M74HC137C1R |
PIN CONNECTIONS (top view)
NC =
No Internal
Connection
February 1993 |
1/11 |
M54/M74HC137
TRUTH TABLE
INPUTS |
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OUTPUTS |
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ENABLE |
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SELECT |
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GL |
G1 |
G2 |
C |
B |
A |
Y0 |
Y1 |
Y2 |
Y3 |
Y4 |
Y5 |
Y6 |
Y7 |
X |
X |
H |
X |
X |
X |
H |
H |
H |
H |
H |
H |
H |
H |
X |
L |
X |
X |
X |
X |
H |
H |
H |
H |
H |
H |
H |
H |
L |
H |
L |
L |
L |
L |
L |
H |
H |
H |
H |
H |
H |
H |
L |
H |
L |
L |
L |
H |
H |
L |
H |
H |
H |
H |
H |
H |
L |
H |
L |
L |
H |
L |
H |
H |
L |
H |
H |
H |
H |
H |
L |
H |
L |
L |
H |
H |
H |
H |
H |
L |
H |
H |
H |
H |
L |
H |
L |
H |
L |
L |
H |
H |
H |
H |
L |
H |
H |
H |
L |
H |
L |
H |
L |
H |
H |
H |
H |
H |
H |
L |
H |
H |
L |
H |
L |
H |
H |
L |
H |
H |
H |
H |
H |
H |
L |
H |
L |
H |
L |
H |
H |
H |
H |
H |
H |
H |
H |
H |
H |
L |
H |
H |
L |
X |
X |
X |
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Outputs corresponding to stored address L: all others H |
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LOGIC DIAGRAM
2/11
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M54/M74HC137 |
PIN DESCRIPTION |
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PIN No |
SYMBOL |
NAME AND FUNCTION |
1, 2, 3 |
A to C |
Data Inputs |
4 |
GL |
Latch Enable Input (Active LOW) |
5 |
G2 |
Data Enable Input (Active LOW) |
6 |
G1 |
Data Enable Input (Active HIGH) |
15, 14, 13, 12, 11, 10, 9, 7 |
Y0 to Y7 |
Multiplexer Outputs |
8 |
GND |
Ground (0V) |
16 |
VCC |
Positive Supply Voltage |
IEC LOGIC SYMBOLS
ABSOLUTE MAXIMUM RATINGS
Symbol |
Parameter |
Value |
Unit |
VCC |
Supply Voltage |
-0.5 to +7 |
V |
VI |
DC Input Voltage |
-0.5 to VCC + 0.5 |
V |
VO |
DC Output Voltage |
-0.5 to VCC + 0.5 |
V |
IIK |
DC Input Diode Current |
± 20 |
mA |
IOK |
DC Output Diode Current |
± 20 |
mA |
IO |
DC Output Source Sink Current Per Output Pin |
± 25 |
mA |
ICC or IGND |
DC VCC or Ground Current |
± 50 |
mA |
PD |
Power Dissipation |
500 (*) |
mW |
Tstg |
Storage Temperature |
-65 to +150 |
oC |
TL |
Lead Temperature (10 sec) |
300 |
oC |
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition isnotimplied.
(*) 500 mW: 65 oC derate to 300 mW by 10mW/oC: 65 oC to 85 oC
3/11
M54/M74HC137
RECOMMENDED OPERATING CONDITIONS
Symbol |
Parameter |
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Value |
Unit |
VCC |
Supply Voltage |
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2 to 6 |
V |
VI |
Input Voltage |
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0 to VCC |
V |
VO |
Output Voltage |
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0 to VCC |
V |
Top |
Operating Temperature: M54HC Series |
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-55 to +125 |
oC |
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M74HC Series |
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-40 to +85 |
oC |
tr, tf |
Input Rise and Fall Time |
VCC = 2 V |
0 to 1000 |
ns |
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VCC = 4.5 V |
0 to 500 |
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VCC = 6 V |
0 to 400 |
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DC SPECIFICATIONS
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Test Conditions |
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Value |
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Symbol |
Parameter |
VCC |
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TA = 25 oC |
-40 to 85 oC |
-55 to 125 oC |
Unit |
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54HC and 74HC |
74HC |
54HC |
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(V) |
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Min. Typ. Max. Min. Max. Min. Max. |
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VIH |
High Level Input |
2.0 |
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1.5 |
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1.5 |
1.5 |
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Voltage |
4.5 |
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3.15 |
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3.15 |
3.15 |
V |
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6.0 |
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4.2 |
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4.2 |
4.2 |
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VIL |
Low Level Input |
2.0 |
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0.5 |
0.5 |
0.5 |
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Voltage |
4.5 |
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1.35 |
1.35 |
1.35 |
V |
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6.0 |
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1.8 |
1.8 |
1.8 |
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VOH |
High Level |
2.0 |
VI = |
IO=-20 μA |
1.9 |
2.0 |
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1.9 |
1.9 |
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Output Voltage |
4.5 |
4.4 |
4.5 |
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4.4 |
4.4 |
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VIH |
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V |
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6.0 |
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5.9 |
6.0 |
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5.9 |
5.9 |
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or |
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4.5 |
VIL |
IO=-4.0 mA |
4.18 |
4.31 |
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4.13 |
4.10 |
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6.0 |
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IO=-5.2 mA |
5.68 |
5.8 |
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5.63 |
5.60 |
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VOL |
Low Level Output |
2.0 |
VI = |
IO= 20 μA |
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0.0 |
0.1 |
0.1 |
0.1 |
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Voltage |
4.5 |
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0.0 |
0.1 |
0.1 |
0.1 |
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VIH |
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V |
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6.0 |
or |
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0.0 |
0.1 |
0.1 |
0.1 |
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4.5 |
VIL |
IO= 4.0 mA |
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0.17 |
0.26 |
0.33 |
0.40 |
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6.0 |
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IO= 5.2 mA |
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0.18 |
0.26 |
0.33 |
0.40 |
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II |
Input Leakage |
6.0 |
VI = VCC or GND |
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±0.1 |
±1 |
±1 |
μA |
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Current |
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ICC |
Quiescent Supply |
6.0 |
VI = VCC or GND |
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2 |
20 |
40 |
μA |
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Current |
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4/11
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