ST M74HC107 User Manual

M74HC107

DUAL J-K FLIP FLOP WITH CLEAR

■HIGH SPEED :

fMAX = 80MHz (TYP.) at VCC = 6V

■LOW POWER DISSIPATION: ICC =2μA(MAX.) at TA=25°C

■HIGH NOISE IMMUNITY: VNIH = VNIL = 28 % VCC (MIN.)

■SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN)

■BALANCED PROPAGATION DELAYS: tPLH tPHL

■WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V

■PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 107

DESCRIPTION

		DIP		SOP	TSSOP
ORDER CODES
PACKAGE				TUBE	T & R
DIP				M74HC107B1R
SOP				M74HC107M1R	M74HC107RM13TR
TSSOP					M74HC107TTR

The M74HC107 is an high speed CMOS DUAL J-K FLIP FLOP fabricated with silicon gate C2MOS technology. These flip-flop are edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, CLOCK, and

CLEAR input and Q and Q outputs. CLEAR is independent of the clock and accomplished by a logic low on the input.

All inputs are equipped with protection circuits against static discharge and transient excess voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

August 2001

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M74HC107

	INPUT AND OUTPUT EQUIVALENT CIRCUIT				PIN DESCRIPTION
					PIN No	SYMBOL	NAME AND FUNCTION
					1, 8, 4, 11	1J, 2J, 1K,	Synchronous Inputs;
						2K	Flip-Flop 1 And 2
					2, 6	1Q, 2Q	Complement Flip-Flop
							Outputs
					3, 5	1Q, 2Q	True Flip-Flop Outputs
					12, 9	1CK, 2CK	Clock Input
					13, 10	1CLR, 2CLR	Asynchronous Reset
							Inputs
					7	GND	Ground (0V)
					14	Vcc	Positive Supply Voltage
	TRUTH TABLE
			INPUTS		OUTPUTS		FUNCTION
	CLR	J	K	CK	Q	Q
	L	X	X	X	L	H	CLEAR
	H	L	L		Qn	Qn	NO CHANGE
	H	L	H		L	H	----
	H	H	L		H	L	----
	H	H	H		Qn	Qn	TOGGLE
	H	X	X		Qn	Qn	NO CHANGE

X : Don’t Care

LOGIC DIAGRAM

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			M74HC107
ABSOLUTE MAXIMUM RATINGS
Symbol	Parameter	Value		Unit
VCC	Supply Voltage	-0.5 to +7		V
VI	DC Input Voltage	-0.5 to VCC + 0.5		V
VO	DC Output Voltage	-0.5 to VCC + 0.5		V
IIK	DC Input Diode Current	± 20		mA
IOK	DC Output Diode Current	± 20		mA
IO	DC Output Current	± 25		mA
ICC or IGND	DC VCC or Ground Current	± 50		mA
PD	Power Dissipation	500(*)		mW
Tstg	Storage Temperature	-65 to +150		°C
TL	Lead Temperature (10 sec)	300		°C

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied

(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C

RECOMMENDED OPERATING CONDITIONS

Symbol		Parameter		Value	Unit
VCC	Supply Voltage			2 to 6	V
VI	Input Voltage			0 to VCC	V
VO	Output Voltage			0 to VCC	V
Top	Operating Temperature			-55 to 125	°C
	Input Rise and Fall Time		VCC = 2.0V	0 to 1000	ns
tr, tf			VCC = 4.5V	0 to 500	ns
			VCC = 6.0V	0 to 400	ns

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M74HC107

DC SPECIFICATIONS

			Test Condition						Value
Symbol	Parameter	VCC				TA = 25°C			-40 to 85°C		-55 to 125°C		Unit
		(V)			Min.		Typ.	Max.	Min.	Max.	Min.	Max.
VIH	High Level Input	2.0			1.5				1.5		1.5
	Voltage	4.5			3.15				3.15		3.15		V
		6.0			4.2				4.2		4.2
VIL	Low Level Input	2.0						0.5		0.5		0.5
	Voltage	4.5						1.35		1.35		1.35	V
		6.0						1.8		1.8		1.8
VOH	High Level Output	2.0		IO=-20 μA	1.9		2.0		1.9		1.9
	Voltage
		4.5		IO=-20 μA	4.4		4.5		4.4		4.4
		6.0		IO=-20 μA	5.9		6.0		5.9		5.9		V
		4.5		IO=-4.0 mA	4.18		4.31		4.13		4.10
		6.0		IO=-5.2 mA	5.68		5.8		5.63		5.60
VOL	Low Level Output	2.0		IO=20 μA			0.0	0.1		0.1		0.1
	Voltage
		4.5		IO=20 μA			0.0	0.1		0.1		0.1
		6.0		IO=20 μA			0.0	0.1		0.1		0.1	V
		4.5		IO=4.0 mA			0.17	0.26		0.33		0.40
		6.0		IO=5.2 mA			0.18	0.26		0.33		0.40
II	Input Leakage	6.0		VI = VCC or GND				± 0.1		± 1		± 1	μA
	Current
ICC	Quiescent Supply	6.0		VI = VCC or GND				2		20		40	μA
	Current

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