ST M68AF127B User Manual

M68AF127B

1Mbit (128K x8), 5V Asynchronous SRAM

FEATURES SUMMARY

■SUPPLY VOLTAGE: 4.5 to 5.5V

■128K x 8 bits SRAM with OUTPUT ENABLE

■EQUAL CYCLE and ACCESS TIMES: 55ns

■LOW STANDBY CURRENT

■LOW VCC DATA RETENTION: 2V

■TRI-STATE COMMON I/O

■LOW ACTIVE and STANDBY POWER

Figure 1. Packages

SO32 (MC)

PDIP32 (B)

TSOP32 (NK) 8 x 13.4mm

TSOP32 (N) 8 x 20mm

September 2004

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M68AF127B

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

TABLE OF CONTENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. SO Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 4. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 5. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 4. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 7. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 8. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 5. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 9. Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 10.Chip Enable or Output Enable Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . 11 Figure 11.Chip Enable Controlled, Standby Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 12.Write Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 13.Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 14.E1 Controlled, Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 15.E2 Controlled, Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 9. Low VCC Data Retention Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 16.SO32 - 32 lead Plastic Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 10. SO32 - 32 lead Plastic Small Outline, Package Mechanical Data. . . . . . . . . . . . . . . . . . 17 Figure 17.PDIP32 - 32 pin Plastic DIP, 600 mils width, Package Outline . . . . . . . . . . . . . . . . . . . . 18 Table 11. PDIP32 - 32 pin Plastic DIP, 600 mils width, Package Mechanical Data . . . . . . . . . . . . 18 Figure 18.TSOP32 - 32-lead Thin Small Outline Package, 8x13.4mm, Package Outline . . . . . . . . 19

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M68AF127B

Table 12. TSOP32 - 32-lead Thin Small Outline Package, 8x13.4mm, Package Mechanical

Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 19.TSOP32 - 32 lead Plastic Thin Small Outline, 8x20mm, Package Outline . . . . . . . . . . . 20 Table 13. TSOP32 - 32 lead Plastic Thin Small Outline, 8x20mm, Package Mechanical Data . . . 20

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 14. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 15. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

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M68AF127B

SUMMARY DESCRIPTION

The M68AF127B is a 1Mbit (1,048,576 bit) CMOS SRAM, organized as 131,072 words by 8 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 4.5 to 5.5V supply.

This device has an automatic power-down feature, reducing the power consumption by over 99% when deselected.

The M68AF127B is available in SO32, PDIP32, TSOP32 (8x13.4mm) and TSOP32 (8x20mm) packages.

Figure 2. Logic Diagram

Table 1. Signal Names

A0-A16

Address Inputs

VCC

DQ0-DQ7

Data Input/Output

Chip Enable

A0-A16

DQ0-DQ7

Output Enable

Write Enable

M68AF127B

VCC

Supply Voltage

VSS

Ground

VSS

AI05472B

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M68AF127B

Figure 3. SO Connections

NC	1		32	VCC


A16				A15
A16				A15
A14				E2
A14				E2
A12
					W
					W
A7				A13
A6				A8
A5				A9
A4	8	M68AF127B	25	A11

A3	9		24	G
A3	9		24	G
A2				A10
A1
A1				E1
A0				DQ7
DQ0				DQ6
DQ1				DQ5
DQ2				DQ4
VSS	16		17	DQ3
		AI07270B

Figure 5. TSOP Connections

		1
A11		1		32	G
A9					A10
A8
A8					E1
A13					DQ7
					DQ6
	W				DQ6
E2					DQ5
A15					DQ4
VCC		8	M68AF127B	25	DQ3
NC		9	M68AF127B	24	VSS
NC		9		24	VSS
A16					DQ2
A14					DQ1
A12					DQ0
A7					A0
A6					A1
A5					A2
A4		16		17	A3
				AI05473d

Figure 4. DIP Connections

NC	1	32	VCC
A16	2	31	A15
A14	3	30	E2
A12	4	29	W
A7	5	28	A13
A6	6	27	A8
A5	7	26	A9
A4	8	25	A11
A3		M68AF127B
A3	9	24	G
A2	10	23	A10
A1	11	22
A1	11	22	E1
A0	12	21	DQ7
DQ0	13	20	DQ6
DQ1	14	19	DQ5
DQ2	15	18	DQ4
VSS	16	17	DQ3
		AI07203B

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M68AF127B

Figure 6. Block Diagram

	A16
	ROW	MEMORY
	DECODER		ARRAY
	A7
	DQ7	I/O CIRCUITS
		I/O CIRCUITS
		COLUMN
		DECODER
	DQ0
E1	Ex
E2
		A0	A6
W
G
			AI05471

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M68AF127B

OPERATION

The M68AF127B has a Chip Enable power down feature which invokes an automatic standby mode whenever Chip Enable is de-asserted (E1 = High), or Chip Select is asserted (E2 = Low). An Output Enable (G) signal provides a high-speed, tri-state

Read Mode

The M68AF127B is in the Read mode whenever Write Enable (W) is High with Output Enable (G) Low, Chip Enable (E1) is asserted and Chip Select (E2) is de-asserted. This provides access to data from eight of the 1,048,576 locations in the static memory array, specified by the 17 address inputs. Valid data will be available at the eight output pins

Write Mode

control, allowing fast read/write cycles to be achieved with the common I/O data bus. Operational modes are determined by device control inputs W and E1 as summarized in the Operating Modes table (Table 2).

within tAVQV after the last stable address, provid-

ing G is Low and E1 is Low. If Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter

(tELQV or tGLQV) rather than the address. Data out may be indeterminate at tELQX and tGLQX, but data lines will always be valid at tAVQV.

The M68AF127B is in the Write mode whenever the W and E1 pins are Low and the E2 pin is High. Either the Chip Enable input (E1) or the Write Enable input (W) must be de-asserted during Address transitions for subsequent write cycles. Write begins with the concurrence of E1 being active with W low. Therefore, address setup time is referenced to Write Enable and Chip Enable as

tAVWL and tAVEH, respectively, and is determined by the latter occurring edge.

Table 2. Operating Modes

The Write cycle can be terminated by the earlier rising edge of E1, or W.

If the Output is enabled (E1 = Low, E2 = High and G = Low), then W will return the outputs to high im-

pedance within tWLQZ of its falling edge. Care must be taken to avoid bus contention in this type of op-

eration. Data input must be valid for tDVWH before the rising edge of Write Enable, or for tDVEH before the rising edge of E1, whichever occurs first, and

remain valid for tWHDX or tEHDX.

Operation

DQ0-DQ7

Power

Read

VIL

VIH

Hi-Z

Active (ICC)

Read

VIL

VIH

VIL

Data Output

Active (ICC)

Write

VIL

VIH

VIL

Data Input

Active (ICC)

Deselect

VIH

Hi-Z

Standby (ISB)

Deselect

VIL

Hi-Z

Standby (ISB)

Note: X = VIH or VIL.

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