ST M68AF127B User Manual
查询M68AF127B供应商
FEAT URES SUM MARY
■ SUPPLY VOLTAGE: 4.5 to 5.5V
■ 128K x 8 bits SRAM with OUTPUT ENABLE
■ EQUAL CYCLE and ACCESS TIMES: 55ns
■ LOW STANDBY CURRENT
■ LOW V
■ TRI-STATE COMMON I/O
■ LOW ACTIVE and STANDBY POWE R
DATA RETENTION: 2V
CC
M68AF127B
1Mbit (128K x8), 5V Asynchronous SRAM
Figure 1. Packages
SO32 (MC)
32
1
PDIP32 (B)
TSOP32 (NK)
8 x 13.4mm
TSOP32 (N)
8 x 20mm
1/23September 2004
M68AF127B
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
TABLE OF CONTENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. SO Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 5. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Write Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 5. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9. Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 10.Chip Enable or Output Enable Controlled, Read Mode AC Waveform s . . . . . . . . . . . . . 11
Figure 11.Chip Enable Controlled, Standby Mode AC Waveform s. . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12.Write Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 13.Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 14.E1
Figure 15.E2 Controlled, Low V
Table 9. Low V
Controlled, Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 16
Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 16
CC
Data Retention Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
CC
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 16.SO32 - 32 lead Plastic Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 10. SO32 - 32 lead Plastic Small Outline, Package Mechanic al Data. . . . . . . . . . . . . . . . . . 17
Figure 17.PDIP32 - 32 pin Plastic DIP, 600 mils width, Package Outline . . . . . . . . . . . . . . . . . . . . 18
Table 11. PDIP32 - 32 pin Plastic DIP, 600 mils width, Package Mechanical Data . . . . . . . . . . . . 18
Figure 18.TSOP32 - 32-lead Thin Small Outline Package, 8x13.4m m , Package Outline. . . . . . . . 19
2/23
M68AF127B
Table 12. TSOP32 - 32-lead Thin Small Outline Package, 8x13.4mm , Packa ge Mechan ical
Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 19.TSOP32 - 32 lead Plastic Thin Small Outline, 8x20mm, Package Outli ne . . . . . . . . . . . 20
Table 13. TSOP32 - 32 lead Plastic Thin Small Outline, 8x20mm, Package M echanical Data . . . 20
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 14.Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 15. Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3/23
M68AF127B
SUMMARY DESCRIPTION
The M68AF127B is a 1Mbit (1,048,576 bit) CMOS
SRAM, organized as 131,072 words by 8 bits. The
device features fully static operation requiring no
external clocks or timing strobes, with equal address access and cycle times. It requires a single
4.5 to 5.5V supply.
Figure 2. Logic Diagram Table 1. Signal Names
This device has an automatic power-down feature,
reducing the power consumption by over 99%
when deselected.
The M68AF127B is available in SO32, PDIP32,
TSOP32 (8x13.4mm) and TSOP32 (8x20mm)
packages.
A0-A16 Address Inputs
A0-A16
W
E1
E2
V
CC
17
M68AF127B
G
V
SS
8
DQ0-DQ7
AI05472B
DQ0-DQ7 Data Input/Output
E1
E2 Chip Enable
G
W
V
CC
V
SS
Chip Enable
Output Enable
Write Enable
Supply Voltage
Ground
4/23
M68AF127B
Figure 3. SO C on nec ti ons
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
V
SS
1
8
M68AF127B
9
16 17
32
25
24
AI07270B
V
CC
A15
E2
W
A13
A8
A9
A11
G
A10
E1
DQ7
DQ6
DQ5
DQ4
DQ3
Figure 5. TSOP Connection s
A11
A9
A8
A13
E2
A15
V
CC
NC
A16
A14
A12
A7
A6
A5
A4 A3
1
W
8
M68AF127B
9
16 17
32
25
24
AI05473d
G
A10
E1
DQ7
DQ6
DQ5
DQ4
DQ3
V
SS
DQ2
DQ1
DQ0
A0
A1
A2
Figure 4. DIP C on ne ctions
NC
1
A16
2
A14
3
A12
4
A7
5
A6
6
A5
7
8
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
V
SS
M68AF127B
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
AI07203B
V
CC
A15
E2
W
A13
A8
A9
A11
G
A10
E1
DQ7
DQ6
DQ5
DQ4
DQ3
5/23
M68AF127B
Figure 6. Block Diagram
A16
A7
ROW
DECODER
MEMORY
ARRAY
E1
E2
DQ7
DQ0
Ex
W
G
I/O CIRCUITS
COLUMN
DECODER
A0 A6
AI05471
6/23
OPERATION
The M68AF127B has a Chip Enable power down
feature which invokes an automatic standby mode
whenever Chip Enable is de-asserted (E1
or Chip Select is asserted (E2 = Low). An Output
Enable (G
) signal provides a high-speed, tri-state
Read Mode
The M68AF127B is in the Read mode whenever
Write En able (W
Low, Chip Enable (E1
) is High with Output Enable (G)
) is asserted and Chip Select
(E2) is de-asserted. This provid es access to dat a
from eight of the 1,048,576 loca tions in the static
memory array, specified by the 17 address inputs.
Valid data will be available at the eight output pins
Write Mode
The M68AF127B is in the Write mode whenever
and E1 pins are Low and the E2 pin is High.
the W
Either the Chip Enable input (E1
able input (W
) must be de-asserted during Ad-
) or the Write En-
dress transitions for subsequent write cycles.
Write begins with the concurrence of E1
tive w ith W
low. Therefore, address setup time is
referenced to Write Enable and Chip Enable as
t
AVWL
and t
, respectively, and is determined
AVEH
by the latter occurring edge.
= High),
being ac-
M68AF127B
control, allowing fast read/write cycles to be
achieved with the common I/O data bus. Operational modes are determined by device control inputs W
Modes table (Table 2).
within t
ing G
put Enable access times are not met, data access
will be measured from the limiting parameter
(t
may be indeterminate at t
lines will always be valid at t
The Write cycle can be terminated by the earlier
rising edge of E1
If the Output is enabled (E1
G
pedance within t
be taken to avoid bus contention in this type of operation. Data input must be valid for t
the rising edge of Write Enable, or for t
the rising edge of E1
remain valid for t
and E1 as summarized in the Operating
after the last stable addres s, provid-
AVQV
is Low and E1 is Low. If Chip Enable or Out-
ELQV
or t
) rather than the address. Data out
GLQV
ELQX
and t
AVQV
GLQX
.
, but data
, or W.
= Low, E2 = High and
= Low), then W will return the outputs to high im-
of its falling edge. Care must
WLQZ
before
DVWH
before
DVEH
, whichever occurs first, and
WHDX
or t
EHDX
.
Table 2. Operating Modes
Operation E1 E2 W G DQ0-DQ7 Power
Read
Read
Write
Deselect
Deselect X
Note: X = VIH or VIL.
V
IL
V
IL
V
IL
V
IH
V
IH
V
IH
V
IH
X X X Hi-Z
V
IL
V
IH
V
IH
V
IL
X X Hi-Z
V
IH
V
IL
X Data Input
Hi-Z
Data Output
Active (I
Active (I
Active (I
Standby (I
Standby (I
CC
CC
CC
SB
SB
)
)
)
)
)
7/23
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