ST M59DR032A, M59DR032B User Manual

M59DR032A

M59DR032A

M59DR032B

32 Mbit (2Mb x16, Dual Bank, Page) Low Voltage Flash Memory

■SUPPLY VOLTAGE

–VDD = VDDQ = 1.65V to 2.2V: for Program, Erase and Read

–VPP = 12V: optional Supply Voltage for fast Program and Erase

■ASYNCHRONOUS PAGE MODE READ

–Page Width: 4 words

–Page Access: 35ns

–Random Access: 100ns

■PROGRAMMING TIME

–10µs by Word typical

–Double Word Programming Option

■MEMORY BLOCKS

–Dual Bank Memory Array: 4 Mbit - 28 Mbit

–Parameter Blocks (Top or Bottom location)

–Main Blocks

■DUAL BANK OPERATIONS

–Read within one Bank while Program or Erase within the other

–No delay between Read and Write operations

■BLOCK PROTECTION/UNPROTECTION

–All Blocks protected at Power Up

–Any combination of Blocks can be protected

–WP for Block Locking

■COMMON FLASH INTERFACE (CFI)

■64 bit SECURITY CODE

■ERASE SUSPEND and RESUME MODES

■100,000 PROGRAM/ERASE CYCLES per BLOCK

■20 YEARS DATA RETENTION

–Defectivity below 1ppm/year

■ELECTRONIC SIGNATURE

–Manufacturer Code: 20h

–Device Code, M59DR032A: A0h

–Device Code, M59DR032B: A1h

PRELIMINARY DATA

	BGA
TSOP48 (N)	FBGA48 (ZB)
12 x 20mm	8 x 6 solder balls

Figure 1. Logic Diagram

	VDD VDDQ VPP
21	16
A0-A20	DQ0-DQ15

W

E M59DR032A

M59DR032B

G

RP

WP

VSS

AI02544B

October 1999

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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M59DR032A, M59DR032B

Figure 2A. FBGA Connections (Top View)

	1	2	3	4	5	6	7	8
A	A13	A11	A8	VPP	WP	A19	A7	A4
B	A14	A10	W	RP	A18	A17	A5	A2
C	A15	A12	A9	DU	A20	A6	A3	A1
D	A16	DQ14	DQ5	DQ11	DQ2	DQ8	E	A0
E	VDDQ	DQ15	DQ6	DQ12	DQ3	DQ9	DQ0	VSS
F	VSS	DQ7	DQ13	DQ4	VDD	DQ10	DQ1	G
								AI02532C

Figure 2B. TSOP Connections

Table 1. Signal Names

A0-A20

Address Inputs

A15

1

48

A16

DQ0-DQ15

Data Input/Outputs, Command Inputs

A14

VDDQ

A13

VSS

Chip Enable

E

A12

DQ15

A11

DQ7

A10

DQ14

G

Output Enable

A9

DQ6

A8

DQ13

W

Write Enable

NC

DQ5

Reset/Power Down

A20

DQ12

RP

DQ4

W

Write Protect

WP

RP

12

M59DR032A

37

VDD

VDD

VPP

13

M59DR032B

36

DQ11

Circuitry Supply Voltage

WP

DQ3

VDDQ

Input/Output Buffers Supply Voltage

A19

DQ10

A18

DQ2

Optional Supply Voltage for

A17

DQ9

VPP

A7

DQ1

Fast Program & Erase

A6

DQ8

VSS

Ground

A5

DQ0

A4

G

NC

Not Connected Internally

A3

VSS

A2

E

DU

Don’t use as internally connected

A1

24

25

A0

AI02533B

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M59DR032A, M59DR032B

Table 2. Absolute Maximum Ratings (1)

Symbol	Parameter	Value	Unit
TA	Ambient Operating Temperature (2)	–40 to 85	°C
TBIAS	Temperature Under Bias	–40 to 125	°C
TSTG	Storage Temperature	–55 to 155	°C
VIO (3)	Input or Output Voltage	–0.5 to VDDQ+0.5	V
VDD, VDDQ	Supply Voltage	–0.5 to 2.7	V
VPP	Program Voltage	–0.5 to 13	V

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.

2.Depends on range.

3.Minimum Voltage may undershoot to –2V during transition and for less than 20ns.

DESCRIPTION

The M59DR032 is a 32 Mbit non-volatile Flash memory that may be erased electrically at block level and programmed in-system on a Word-by- Word basis using a 1.65V to 2.2V VDD supply for the circuitry. For Program and Erase operations the necessary high voltages are generated internally. The device supports asynchronous page mode from all the blocks of the memory array.

The array matrix organization allows each block to be erased and reprogrammed without affecting other blocks. All blocks are protected against programming and erase at Power Up. Blocks can be unprotected to make changes in the application and then reprotected.

Instructions for Read/Reset, Auto Select, Write Configuration Register, Programming, Block Erase, Bank Erase, Erase Suspend, Erase Resume, Block Protect, Block Unprotect, Block Locking, CFI Query, are written to the memory through a Command Interface using standard microprocessor write timings.

The device is offered in TSOP48 (12 x 20 mm) and in FBGA48 0.75 mm ball pitch packages.

When shipped all bits of the M59DR032 device are at the logical level ‘1’.

Organization

The M59DR032 is organized as 2Mb x16 bits. A0A20 are the address lines, DQ0-DQ15 are the Data Input/Output. Memory control is provided by Chip Enable E, Output Enable G and Write Enable W inputs.

Reset RP is used to reset all the memory circuitry and to set the chip in power down mode if this function is enabled by a proper setting of the Configuration Register. Erase and Program operations are controlled by an internal Program/Erase Controller (P/E.C.). Status Register data output on DQ7 provides a Data Polling signal, DQ6 and DQ2 provide Toggle signals and DQ5 provides error bit to indicate the state of the P/E.C operations.

Memory Blocks

The device features asymmetrically blocked architecture. M59DR032 has an array of 71 blocks and is divided into two banks A and B, providing Dual Bank operations. While programming or erasing in Bank A, read operations are possible into Bank B or vice versa. The memory also features an erase suspend allowing to read or program in another block within the same bank. Once suspended the erase can be resumed. The Bank Size and Sectorization are summarized in Table 7. Parameter Blocks are located at the top of the memory address space for the M59DR032A, and at the bottom for the M59DR032B. The memory maps are shown in Tables 3, 4, 5 and 6.

The Program and Erase operations are managed automatically by the P/E.C. Block protection against Program or Erase provides additional data security. All blocks are protected at Power Up. Instructions are provided to protect or unprotect any block in the application. A second register locks the protection status while WP is low (see Block Locking description). The Reset command does not affect the configuration of unprotected blocks and the Configuration Register status.

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M59DR032A, M59DR032B

Table 3. Bank A, Top Boot Block Address

Size (KWord)	Address Range
4	1FF000h-1FFFFFh
4	1FE000h-1FEFFFh
4	1FD000h-1FDFFFh
4	1FC000h-1FCFFFh
4	1FB000h-1FBFFFh
4	1FA000h-1FAFFFh
4	1F9000h-1F9FFFh
4	1F8000h-1F8FFFh
32	1F0000h-1F7FFFh
32	1E8000h-1EFFFFh
32	1E0000h-1E7FFFh
32	1D8000h-1DFFFFh
32	1D0000h-1D7FFFh
32	1C8000h-1CFFFFh
32	1C0000h-1C7FFFh

Table 4. Bank B, Top Boot Block Address

Size (KWord)	Address Range
32	1B8000h-1BFFFFh
32	1B0000h-1B7FFFh
32	1A8000h-1AFFFFh
32	1A0000h-1A7FFFh
32	198000h-19FFFFh
32	190000h-197FFFh
32	188000h-18FFFFh
32	180000h-187FFFh
32	178000h-17FFFFh
32	170000h-177FFFh
32	168000h-16FFFFh
32	160000h-167FFFh
32	158000h-15FFFFh
32	150000h-157FFFh
32	148000h-14FFFFh
32	140000h-147FFFh
32	138000h-13FFFFh
32	130000h-137FFFh

32	128000h-12FFFFh
32	120000h-127FFFh
32	118000h-11FFFFh
32	110000h-117FFFh
32	108000h-10FFFFh
32	100000h-107FFFh
32	0F8000h-0FFFFFh
32	0F0000h-0F7FFFh
32	0E8000h-0EFFFFh
32	0E0000h-0E7FFFh
32	0D8000h-0DFFFFh
32	0D0000h-0D7FFFh
32	0C8000h-0CFFFFh
32	0C0000h-0C7FFFh
32	0B8000h-0BFFFFh
32	0B0000h-0B7FFFh
32	0A8000h-0AFFFFh
32	0A0000h-0A7FFFh
32	098000h-09FFFFh
32	090000h-097FFFh
32	088000h-08FFFFh
32	080000h-087FFFh
32	078000h-07FFFFh
32	070000h-077FFFh
32	068000h-06FFFFh
32	060000h-067FFFh
32	058000h-05FFFFh
32	050000h-057FFFh
32	048000h-04FFFFh
32	040000h-047FFFh
32	038000h-03FFFFh
32	030000h-037FFFh
32	028000h-02FFFFh
32	020000h-027FFFh
32	018000h-01FFFFh
32	010000h-017FFFh
32	008000h-00FFFFh
32	000000h-007FFFh

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M59DR032A, M59DR032B

Table 5. Bank B, Bottom Boot Block Address

Size (KWord)	Address Range
32	1F8000h-1FFFFFh
32	1F0000h-1F7FFFh
32	1E8000h-1EFFFFh
32	1E0000h-1E7FFFh
32	1D8000h-1DFFFFh
32	1D0000h-1D7FFFh
32	1C8000h-1CFFFFh
32	1C0000h-1C7FFFh
32	1B8000h-1BFFFFh
32	1B0000h-1B7FFFh
32	1A8000h-1AFFFFh
32	1A0000h-1A7FFFh
32	198000h-19FFFFh
32	190000h-197FFFh
32	188000h-18FFFFh
32	180000h-187FFFh
32	178000h-17FFFFh
32	170000h-177FFFh
32	168000h-16FFFFh
32	160000h-167FFFh
32	158000h-15FFFFh
32	150000h-157FFFh
32	148000h-14FFFFh
32	140000h-147FFFh
32	138000h-13FFFFh
32	130000h-137FFFh
32	128000h-12FFFFh
32	120000h-127FFFh
32	118000h-11FFFFh
32	110000h-117FFFh
32	108000h-10FFFFh
32	100000h-107FFFh
32	0F8000h-0FFFFFh
32	0F0000h-0F7FFFh
32	0E8000h-0EFFFFh
32	0E0000h-0E7FFFh

32	0D8000h-0DFFFFh
32	0D0000h-0D7FFFh
32	0C8000h-0CFFFFh
32	0C0000h-0C7FFFh
32	0B8000h-0BFFFFh
32	0B0000h-0B7FFFh
32	0A8000h-0AFFFFh
32	0A0000h-0A7FFFh
32	098000h-09FFFFh
32	090000h-097FFFh
32	088000h-08FFFFh
32	080000h-087FFFh
32	078000h-07FFFFh
32	070000h-077FFFh
32	068000h-06FFFFh
32	060000h-067FFFh
32	058000h-05FFFFh
32	050000h-057FFFh
32	048000h-04FFFFh
32	040000h-047FFFh

Table 6. Bank A, Bottom Boot Block Address

Size (KWord)	Address Range
32	038000h-03FFFFh
32	030000h-037FFFh
32	028000h-02FFFFh
32	020000h-027FFFh
32	018000h-01FFFFh
32	010000h-017FFFh
32	008000h-00FFFFh
4	007000h-007FFFh
4	006000h-006FFFh
4	005000h-005FFFh
4	004000h-004FFFh
4	003000h-003FFFh
4	002000h-002FFFh
4	001000h-001FFFh
4	000000h-000FFFh

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M59DR032A, M59DR032B

Table 7. Bank Size and Sectorization

	Bank Size	Parameter Blocks	Main Blocks
Bank A	4 Mbit	8 blocks of 4 KWord	7 blocks of 32 KWord
Bank B	28 Mbit	-	56 blocks of 32 KWord

SIGNAL DESCRIPTIONS

See Figure 1 and Table 1.

Address Inputs (A0-A20). The address inputs for the memory array are latched during a write operation on the falling edge of Chip Enable E or Write Enable W, whichever occurs last.

Data Input/Output (DQ0-DQ15). The Input is data to be programmed in the memory array or a command to be written to the Command Interface (C.I.) Both input data and commands are latched on the rising edge of Write Enable W. The Ouput is data from the Memory Array, the Common Flash Interface, the Electronic Signature Manufacturer or Device codes, the Block Protection status, the Configuration Register status or the Status Register Data Polling bit DQ7, the Toggle Bits DQ6 and DQ2, the Error bit DQ5. The data bus is high impedance when the chip is deselected, Output Enable G is at VIH, or RP is at VIL.

Chip Enable (E). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. E at VIH deselects the memory and reduces the power consumption to the standby level. E can also be used to control writing to the command register and to the memory array, while W remains at VIL.

Output Enable (G). The Output Enable gates the outputs through the data buffers during a read operation. When G is at VIH the outputs are High impedance.

Write Enable (W). This input controls writing to the Command Register and Data latches. Data are latched on the rising edge of W.

Write Protect (WP). This input gives an additional hardware protection level against program or erase when pulled at VIL, as described in the Block Lock instruction description.

Reset/Power Down Input (RP). The RP input provides hardware reset of the memory (without affecting the Configuration Register status), and/ or Power Down functions, depending on the Configuration Register status. Reset/Power Down of the memory is achieved by pulling RP to VIL for at

least tPLPH. When the reset pulse is given, if the memory is in Read, Erase Suspend Read or

Standby, it will output new valid data in tPHQ7V1 af-

ter the rising edge of RP. If the memory is in Erase or Program modes, the operation will be aborted

and the reset recovery will take a maximum ot

tPLQ7V. The memory will recover from Power Down (when enabled) in tPHQ7V2 after the rising edge of RP. See Tables 25, 26 and Figure 9.

VDD and VDDQ Supply Voltage (1.65V to 2.2V).

The main power supply for all operations (Read,

Program and Erase). VDD and VDDQ must be at the same voltage.

VPP Programming Voltage (11.4V to 12.6V). Used to provide high voltage for fast factory programming. High voltage on VPP pin is required to use the Double Word Program instruction. It is also possible to perform word program or erase instructions with VPP pin grounded.

VSS Ground. VSS is the reference for all the voltage measurements.

DEVICE OPERATIONS

The following operations can be performed using the appropriate bus cycles: Read Array (Random, and Page Modes), Write command, Output Disable, Standby, Reset/Power Down and Block Locking. See Table 8.

Read. Read operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register, the CFI, the Block Protection Status or the Configuration Register status. Read operation of the memory array is performed in asynchronous page mode, that provides fast access time. Data is internally read and stored in a page buffer. The page has a size of 4 words and is addressed by A0-A1 address inputs. Read operations of the Electronic Signature, the Status Register, the CFI, the Block Protection Status, the Configuration Register status and the Security Code are performed as single asyncronous read cycles (Random Read). Both Chip Enable E and Output Enable G must be at VIL in order to read the output of the memory.

Write. Write operations are used to give Instruction Commands to the memory or to latch Input Data to be programmed. A write operation is initiated when Chip Enable E and Write Enable W are at VIL with Output Enable G at VIH. Addresses are latched on the falling edge of W or E whichever occurs last. Commands and Input Data are latched on the rising edge of W or E whichever occurs first. Noise pulses of less than 5ns typical on E, W and G signals do not start a write cycle.

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M59DR032A, M59DR032B

Table 8. User Bus Operations (1)

Operation

E

G

W

RP

WP

DQ15-DQ0

Write

VIL

VIH

VIL

VIH

VIH

Data Input

Output Disable

VIL

VIH

VIH

VIH

VIH

Hi-Z

Standby

VIH

X

X

VIH

VIH

Hi-Z

Reset / Power Down

X

X

X

VIL

VIH

Hi-Z

Block Locking

VIL

X

X

VIH

VIL

X

Note: 1. X = Don’t care.

Table 9. Read Electronic Signature (AS and Read CFI instructions)

Other

Code

Device

E

G

W

A0

A1

A7-A2

DQ15-DQ8

DQ7-DQ0

Addresses

Manufacturer Code

VIL

VIL

VIH

VIL

VIL

0

Don’t Care

00h

20h

Device Code

M59DR032A

VIL

VIL

VIH

VIH

VIL

0

Don’t Care

00h

A0h

M59DR032B

VIL

VIL

VIH

VIH

VIL

0

Don’t Care

00h

A1h

Table 10. Read Block Protection (AS and Read CFI instructions)

Other

Block Status

E

G

W

A0

A1

A20-A12

A7-A2

DQ0

DQ1

DQ15-DQ2

Addresses

Protected Block

VIL

VIL

VIH

VIL

VIH

Block Address

0

Don’t Care

1

0

0000h

Unprotected Block

VIL

VIL

VIH

VIL

VIH

Block Address

0

Don’t Care

0

0

0000h

Locked Block

VIL

VIL

VIH

VIL

VIH

Block Address

0

Don’t Care

X

1

0000h

Table 11. Read Configuration Register (AS and Read CFI instructions)

DQ9-DQ0

RP Function

E

G

W

A0

A1

A7-A2

Other Addresses

DQ10

DQ15-DQ11

Reset

VIL

VIL

VIH

VIH

VIH

0

Don’t Care

0

Don’t Care

Reset/Power Down

VIL

VIL

VIH

VIH

VIH

0

Don’t Care

1

Don’t Care

Dual Bank Operations. The Dual Bank allows to read data from one bank of memory while a program or erase operation is in progress in the other bank of the memory. Read and Write cycles can be initiated for simultaneous operations in different banks without any delay. Status Register during Program or Erase must be monitored using an address within the bank being modified.

Output Disable. The data outputs are high impedance when the Output Enable G is at VIH with Write Enable W at VIH.

Standby. The memory is in standby when Chip Enable E is at VIH and the P/E.C. is idle. The power consumption is reduced to the standby level and the outputs are high impedance, independent of the Output Enable G or Write Enable W inputs.

Automatic Standby. When in Read mode, after 150ns of bus inactivity and when CMOS levels are driving the addresses, the chip automatically enters a pseudo-standby mode where consumption is reduced to the CMOS standby value, while outputs still drive the bus.

Power Down. The memory is in Power Down when the Configuration Register is set for Power Down and RP is at VIL. The power consumption is reduced to the Power Down level, and Outputs are in high impedance, independent of the Chip Enable E, Output Enable G or Write Enable W inputs.

Block Locking. Any combination of blocks can be temporarily protected against Program or Erase by setting the lock register and pulling WP to VIL (see Block Lock instruction).

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M59DR032A, M59DR032B

INSTRUCTIONS AND COMMANDS

Seventeen instructions are defined (see Table 14A), and the internal P/E.C. automatically handles all timing and verification of the Program and Erase operations. The Status Register Data Polling, Toggle, Error bits can be read at any time, during programming or erase, to monitor the progress of the operation.

Instructions, made up of one or more commands written in cycles, can be given to the Program/ Erase Controller through a Command Interface (C.I.). The C.I. latches commands written to the memory. Commands are made of address and data sequences. Two Coded Cycles unlock the Command Interface. They are followed by an input command or a confirmation command. The Coded Sequence consists of writing the data AAh at the address 555h during the first cycle and the data 55h at the address 2AAh during the second cycle.

Instructions are composed of up to six cycles. The first two cycles input a Coded Sequence to the Command Interface which is common to all instructions (see Table 14A). The third cycle inputs the instruction set-up command. Subsequent cycles output the addressed data, Electronic Signature, Block Protection, Configuration Register Status or CFI Query for Read operations. In order to give additional data protection, the instructions for Block Erase and Bank Erase require further command inputs. For a Program instruction, the fourth command cycle inputs the address and data to be programmed. For a Double Word Programming instruction, the fourth and fifth command cycles input the address and data to be programmed. For a Block Erase and Bank Erase instructions, the fourth and fifth cycles input a further Coded Sequence before the Erase confirm command on the sixth cycle. Any combination of blocks of the same memory bank can be erased. Erasure of a memory block may be suspended, in order to read data from another block or to program data in another block, and then resumed. When power is first applied the command interface is reset to Read Array.

Command sequencing must be followed exactly. Any invalid combination of commands will reset the device to Read Array. The increased number of cycles has been chosen to ensure maximum data security.

8/38

Read/Reset (RD) Instruction. The Read/Reset instruction consists of one write cycle giving the command F0h. It can be optionally preceded by the two Coded Cycles. Subsequent read operations will read the memory array addressed and output the data read.

CFI Query (RCFI) Instruction. Common Flash Interface Query mode is entered writing 98h at address 55h. The CFI data structure gives information on the device, such as the sectorization, the command set and some electrical specifications. Tables 15, 16, 17 and 18 show the addresses used to retrieve each data. The CFI data structure contains also a security area; in this section, a 64 bit unique security number is written, starting at address 80h. This area can be accessed only in read mode by the final user and there are no ways of changing the code after it has been written by ST. Write a read instruction (RD) to return to Read mode.

Table 12. Commands

	Hex Code	Command
	00h	Bypass Reset
	10h	Bank Erase Confirm
	20h	Unlock Bypass
	30h	Block Erase Resume/Confirm
	40h	Double Word Program
		Block Protect, or
	60h	Block Unprotect, or
		Block Lock, or
		Write Configuration Register
	80h	Set-up Erase
		Read Electronic Signature, or
	90h	Block Protection Status, or
		Configuration Register Status
	98h	CFI Query
	A0h	Program
	B0h	Erase Suspend
	F0h	Read Array/Reset

M59DR032A, M59DR032B

Auto Select (AS) Instruction. This instruction uses two Coded Cycles followed by one write cycle giving the command 90h to address 555h for command set-up. A subsequent read will output the Manufacturer or the Device Code (Electronic Signature), the Block Protection status or the Configuration Register status depending on the levels of A0 and A1 (see Tables 9, 10 and 11). A7-A2 must be at VIL, while other address input are ignored. The bank address is don’t care for this instruction. The Electronic Signature can be read from the memory allowing programming equipment or applications to automatically match their interface to the characteristics of M59DR032. The Manufacturer Code is output when the address lines A0 and A1 are at VIL, the Device Code is output when A0 is at VIH with A1 at VIL.

The codes are output on DQ0-DQ7 with DQ8DQ15 at 00h. The AS instruction also allows the access to the Block Protection Status. After giving the AS instruction, A0 is set to VIL with A1 at VIH, while A12-A20 define the address of the block to be verified. A read in these conditions will output a 01h if the block is protected and a 00h if the block is not protected.

The AS Instruction finally allows the access to the Configuration Register status if both A0 and A1 are set to VIH. If DQ10 is '0' only the Reset function is active as RP is set to VIL (default at power-up). If DQ10 is '1' both the Reset and the Power Down functions will be achieved by pulling RP to VIL. The other bits of the Configuration Register are reserved and must be ignored. A reset command puts the device in read array mode.

Write Configuration Register (CR) Instruction. This instruction uses two Coded Cycles followed by one write cycle giving the command 60h to address 555h. A further write cycle giving the command 03h writes the contents of address bits A0-A15 to the 16 bits configuration register. Bits written by inputs A0-A9 and A11-A15 are reserved for future use. Address input A10 defines the status of the Reset/Power Down functions. It must be set to VIL to enable only the Reset function and to VIH to enable also the Power Down function. At Power Up all the Configuration Register bits are reset to '0'.

Enter Bypass Mode (EBY) Instruction. This instruction uses the two Coded cycles followed by one write cycle giving the command 20h to address 555h for mode set-up. Once in Bypass mode, the device will accept the Exit Bypass

(XBY) and Program or Double Word Program in Bypass mode (PGBY, DPGBY) commands. The Bypass mode allows to reduce the overall programming time when large memory arrays need to be programmed.

Exit Bypass Mode (XBY) Instruction. This instruction uses two write cycles. The first inputs to the memory the command 90h and the second inputs the Exit Bypass mode confirm (00h). After the XBY instruction, the device resets to Read Memory Array mode.

Program in Bypass Mode (PGBY) Instruction. This instruction uses two write cycles. The Program command A0h is written to any Address on the first cycle and the second write cycle latches the Address on the falling edge of W or E and the Data to be written on the rising edge and starts the P/E.C. Read operations within the same bank output the Status Register bits after the programming has started. Memory programming is made only by writing '0' in place of '1'. Status bits DQ6 and DQ7 determine if programming is on-going and DQ5 allows verification of any possible error.

Program (PG) Instruction. This instruction uses four write cycles. The Program command A0h is written to address 555h on the third cycle after two Coded Cycles. A fourth write operation latches the Address and the Data to be written and starts the P/E.C. Read operations within the same bank output the Status Register bits after the programming has started. Memory programming is made only by writing '0' in place of '1'. Status bits DQ6 and DQ7 determine if programming is on-going and DQ5 allows verification of any possible error. Programming at an address not in blocks being erased is also possible during erase suspend.

Double Word Program (DPG) Instruction. This feature is offered to improve the programming throughput, writing a page of two adjacent words in parallel. High voltage (11.4V to 12.6V) on VPP pin is required. This instruction uses five write cycles. The double word program command 40h is written to address 555h on the third cycle after two Coded Cycles. A fourth write cycle latches the address and data to be written to the first location. A fifth write cycle latches the new data to be written to the second location and starts the P/E.C.. Note that the two locations must have the same address except for the address bit A0. The Double Word Program can be executed in Bypass mode (DPGBY) to skip the two coded cycles at the beginning of each command.

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M59DR032A, M59DR032B

Table 13. Protection States (1)

Current State (2)	Program/Erase		Next State After Event (3)
(WP, DQ1, DQ0)	Allowed	Protect	Unprotect	Lock			WP transition
100	yes	101	100	111			000
101	no	101	100	111			001
110	yes	111	110	111			011
111	no	111	110	111			011
000	yes	001	000	011			100
001	no	001	000	011			101
011	no	011	011	011				111 or 110 (4)

Note: 1. All blocks are protected at power-up, so the default configuration is 001 or 101 according to WP status.

2.Current state and Next state gives the protection status of a block. The protection status is defined by the write protect pin and by DQ1 (= 1 for a locked block) and DQ0 (= 1 for a protected block) as read in the Autoselect instruction with A1 = VIH and A0 = VIL.

3.Next state is the protection status of a block after a Protect or Unprotect or Lock command has been issued or after WP has changed its logic value.

4.A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.

Block Protect (BP), Block Unprotect (BU), Block Lock (BL) Instructions. All blocks are protected at power-up. Each block of the array has two levels of protection against program or erase operation. The first level is set by the Block Protect instruction; a protected block cannot be programmed or erased until a Block Unprotect instruction is given for that block. A second level of protection is set by the Block Lock instruction, and requires the use of the WP pin, according to the following scheme:

–when WP is at VIH, the Lock status is overridden and all blocks can be protected or unprotected;

–when WP is at VIL, Lock status is enabled; the locked blocks are protected, regardless of their previous protect state, and protection status cannot be changed. Blocks that are not locked can still change their protection status, and program or erase accordingly;

–the lock status is cleared for all blocks at power up; once a block has been locked state can be cleared only with a reset command. The protection and lock status can be monitored for each block using the Autoselect (AS) instruction. Protected blocks will output a ‘1’ on DQ0 and locked blocks will output a ‘1’ on DQ1.

Refer to Table 13 for a list of the protection states.

Block Erase (BE) Instruction. This instruction uses a minimum of six write cycles. The Erase Set-up command 80h is written to address 555h on third cycle after the two Coded cycles. The Block Erase Confirm command 30h is similarly written on the sixth cycle after another two Coded cycles and an address within the block to be erased is given and latched into the memory.

Additional block Erase Confirm commands and block addresses can be written subsequently to erase other blocks in parallel, without further Coded cycles. All blocks must belong to the same bank of memory; if a new block belonging to the other bank is given, the operation is aborted. The erase will start after an erase timeout period of 100µs. Thus, additional Erase Confirm commands for other blocks must be given within this delay. The input of a new Erase Confirm command will restart the timeout period. The status of the internal timer can be monitored through the level of DQ3, if DQ3 is '0' the Block Erase Command has been given and the timeout is running, if DQ3 is '1', the timeout has expired and the P/E.C. is erasing the Block(s). If the second command given is not an erase confirm or if the Coded cycles are wrong, the instruction aborts, and the device is reset to Read Array. It is not necessary to program the block with 00h as the P/E.C. will do this automatically before erasing to FFh. Read operations with- in the same bank, after the sixth rising edge of W or E, output the status register bits.

During the execution of the erase by the P/E.C., the memory accepts only the Erase Suspend ES instruction; the Read/Reset RD instruction is accepted during the 100µs time-out period. Data Polling bit DQ7 returns '0' while the erasure is in progress and '1' when it has completed. The Toggle bit DQ6 toggles during the erase operation, and stops when erase is completed.

After completion the Status Register bit DQ5 returns '1' if there has been an erase failure. In such a situation, the Toggle bit DQ2 can be used to determine which block is not correctly erased. In the case of erase failure, a Read/Reset RD instruction is necessary in order to reset the P/E.C.

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M59DR032A, M59DR032B

Bank Erase (BKE) Instruction. This instruction uses six write cycles and is used to erase all the blocks belonging to the selected bank. The Erase Set-up command 80h is written to address 555h on the third cycle after the two Coded cycles. The Bank Erase Confirm command 10h is similarly written on the sixth cycle after another two Coded cycles at an address within the selected bank. If the second command given is not an erase confirm or if the Coded cycles are wrong, the instruction aborts and the device is reset to Read Array. It is not necessary to program the array with 00h first as the P/E.C. will automatically do this before erasing it to FFh. Read operations within the same bank after the sixth rising edge of W or E output the Status Register bits. During the execution of the erase by the P/E.C., Data Polling bit DQ7 returns ’0’, then ’1’ on completion. The Toggle bit DQ6 toggles during erase operation and stops when erase is completed. After completion the Status Register bit DQ5 returns ’1’ if there has been an Erase Failure.

Erase Suspend (ES) Instruction. In a dual bank memory the Erase Suspend instruction is used to read data within the bank where erase is in

progress. It is also possible to program data in blocks not being erased.

The Erase Suspend instruction consists of writing the command B0h without any specific address. No Coded Cycles are required. Erase suspend is accepted only during the Block Erase instruction execution. The Toggle bit DQ6 stops toggling when the P/E.C. is suspended within 15µs after the Erase Suspend (ES) command has been written. The device will then automatically be set to Read Memory Array mode. When erase is suspended, a Read from blocks being erased will output DQ2 toggling and DQ6 at '1'. A Read from a block not being erased returns valid data. During suspension the memory will respond only to the Erase Resume ER and the Program PG instructions. A Program operation can be initiated during erase suspend in one of the blocks not being erased. It will result in DQ6 toggling when the data is being programmed.

Erase Resume (ER) Instruction. If an Erase Suspend instruction was previously executed, the erase operation may be resumed by giving the command 30h, at an address within the bank being erased and without any Coded Cycle.

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M59DR032A, M59DR032B

Table 14A. Instructions (1,2)

	Mne.	Instr.		Cyc.		1st Cyc.	2nd Cyc.	3rd Cyc.	4th Cyc.	5th Cyc.	6th Cyc.
				1+	Addr. (3)	X	Read Memory Array until a new write cycle is initiated.
	RD (4)	Read/Reset			Data	F0h
		Memory Array			Addr.	555h	2AAh	555h	Read Memory Array until a new
				3+
					Data	AAh	55h	F0h	write cycle is initiated.
	RCFI	CFI Query		1+	Addr.	55h	Read CFI data until a new write cycle is initiated.
					Data	98h
					Addr.	555h	2AAh	555h	Read electronic Signature or
	AS (4)	Auto Select		3+					Block Protection or Configuration
					Data	AAh	55h	90h	Register Status until a new cycle
									is initiated.
		Configuration			Addr.	555h	2AAh	555h	Configura-
	CR			4					tion Data
		Register Write
					Data	AAh	55h	60h	03h
					Addr.	555h	2AAh	555h	Program	Read Data Polling or
									Address
	PG	Program		4						Toggle Bit until
									Program
					Data	AAh	55h	A0h		Program completes.
									Data
					Addr.	555h	2AAh	555h	Program	Program
		Double Word							Address 1	Address 2
	DPG			5							Note 6, 7
		Program			Data	AAh	55h	40h	Program	Program
									Data 1	Data 2
	EBY	Enter Bypass		3	Addr.	555h	2AAh	555h
		Mode			Data	AAh	55h	20h
	XBY	Exit Bypass		2	Addr.	X	X
		Mode			Data	90h	00h
					Addr.	X	Program
		Program in					Address	Read Data Polling or Toggle Bit until Program
	PGBY			2
		Bypass Mode			Data	A0h	Program	completes.
							Data
		Double Word			Addr.	X	Program	Program
							Address 1	Address 2
	DPGBY	Program in		3						Note 6, 7
							Program	Program
		Bypass Mode			Data	40h
							Data 1	Data 2
					Addr.	555h	2AAh	555h	Block
	BP	Block Protect		4					Address
					Data	AAh	55h	60h	01h
					Addr.	555h	2AAh	555h	Block
	BU	Block Unprotect		1					Address
					Data	AAh	55h	60h	D0h

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