ST M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB User Manual

M58BW016BT, M58BW016BB M58BW016DT, M58BW016DB

16 Mbit (512Kb x32, Boot Block, Burst)

3V Supply Flash Memories

PE4FEATURES SUMMARY

■SUPPLY VOLTAGE

–VDD = 2.7V to 3.6V for Program, Erase and Read

–VDDQ = VDDQIN = 2.4V to 3.6V for I/O Buffers

–VPP = 12V for fast Program (optional)

■HIGH PERFORMANCE

–Access Time: 80, 90 and 100ns

–56MHz Effective Zero Wait-State Burst Read

–Synchronous Burst Reads

–Asynchronous Page Reads

■HARDWARE BLOCK PROTECTION

–WP pin Lock Program and Erase

■SOFTWARE BLOCK PROTECTION

–Tuning Protection to Lock Program and Erase with 64 bit User Programmable Password (M58BW016B version only)

■OPTIMIZED for FDI DRIVERS

–Fast Program / Erase suspend latency time < 6µs

–Common Flash Interface

■MEMORY BLOCKS

–8 Parameters Blocks (Top or Bottom)

–31 Main Blocks

■LOW POWER CONSUMPTION

–5µA Typical Deep Power Down

–60µA Typical Standby

–Automatic Standby after Asynchronous Read

■ELECTRONIC SIGNATURE

–Manufacturer Code: 20h

–Top Device Code M58BW016xT: 8836h

–Bottom Device Code M58BW016xB: 8835h

Figure 1. Packages

PQFP80 (T)

BGA

LBGA80 (ZA) 10 x 8 ball array

May 2003

1/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

TABLE OF CONTENTS

SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. LBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. PQFP Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Tuning Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 2. Top Boot Block Addresses, M58BW016BT, M58BW016DT . . . . . . . . . . . . . . . . . . . . . . 11 Table 3. Bottom Boot Block Addresses, M58BW016BB, M58BW016DB . . . . . . . . . . . . . . . . . . . 12

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Address Inputs (A0-A18). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Data Inputs/Outputs (DQ0-DQ31). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Output Disable (GD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Reset/Power-Down (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Latch Enable (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Burst Clock (K). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Burst Address Advance (B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Valid Data Ready (R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Supply Voltage (VDD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Output Supply Voltage (VDDQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Input Supply Voltage (VDDQIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Program/Erase Supply Voltage (VPP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Ground (VSS and VSSQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Asynchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Asynchronous Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Asynchronous Latch Controlled Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Asynchronous Page Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Asynchronous Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Asynchronous Latch Controlled Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Automatic Low Power.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Power-Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 4. Asynchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 5. Asynchronous Read Electronic Signature Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

Synchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Synchronous Burst Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Synchronous Burst Read Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 6. Synchronous Burst Read Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Read Select Bit (M15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

X-Latency Bits (M14-M11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Y-Latency Bit (M9). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Valid Data Ready Bit (M8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Burst Type Bit (M7).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Valid Clock Edge Bit (M6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Wrap Burst Bit (M3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Burst Length Bit (M2-M0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 7. Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 8. Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Read Memory Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Read Query Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Set Burst Configuration Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Tuning Protection Unlock Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Tuning Protection Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 9. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 10. Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . 27

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Program Status, Tuning Protection Unlock Status (Bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 VPP Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Block Protection Status (Bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Tuning Protection Status (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 11. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 12. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 13. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 7. AC Measurement Input Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 8. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 14. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 15. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 9. Asynchronous Bus Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 16. Asynchronous Bus Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 10. Asynchronous Latch Controlled Bus Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . 34 Table 17. Asynchronous Latch Controlled Bus Read AC Characteristics . . . . . . . . . . . . . . . . . . . 34 Figure 11. Asynchronous Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 18. Asynchronous Page Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 12. Asynchronous Write AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 13. Asynchronous Latch Controlled Write AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 19. Asynchronous Write and Latch Controlled Write AC Characteristics . . . . . . . . . . . . . . 38 Figure 14. Synchronous Burst Read (Data Valid from ’n’ Clock Rising Edge) . . . . . . . . . . . . . . . 39 Table 20. Synchronous Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 15. Synchronous Burst Read (Data Valid from ’n’ Clock Rising Edge) . . . . . . . . . . . . . . . 40 Figure 16. Synchronous Burst Read - Continuous - Valid Data Ready Output . . . . . . . . . . . . . . . 41 Figure 17. Synchronous Burst Read - Burst Address Advance. . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 18. Reset, Power-Down and Power-up AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 21. Reset, Power-Down and Power-up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 19. LBGA80 10x12mm - 8x10 ball array, 1mm pitch, Bottom View Package Outline . . . . 43 Table 22. LBGA80 10x12mm - 8x10 ball array, 1mm pitch, Package Mechanical Data . . . . . . . . 43 Figure 20. PQFP80 - 80 lead Plastic Quad Flat Pack, Package Outline . . . . . . . . . . . . . . . . . . . . 44 Table 23. PQFP80 - 80 lead Plastic Quad Flat Pack, Package Mechanical Data. . . . . . . . . . . . . 44

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 24. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

APPENDIX A. COMMON FLASH INTERFACE - CFI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 25. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 26. CFI - Query Address and Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 27. CFI - Device Voltage and Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 28. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 29. Extended Query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

APPENDIX B. FLOW CHARTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

49

Figure 21. Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 22. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . 50 Figure 23. Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 24. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . 52 Figure 25. Unlock Device and Change Tuning Protection Code Flowchart . . . . . . . . . . . . . . . . . 53

4/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

Figure 26. Unlock Device and Program a Tuning Protected Block Flowchart . . . . . . . . . . . . . . . . 54 Figure 27. Unlock Device and Erase a Tuning Protected Block Flowchart . . . . . . . . . . . . . . . . . . 55 Figure 28. Power-up Sequence to Burst the Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 29. Command Interface and Program Erase Controller Flowchart (a) . . . . . . . . . . . . . . . . 57 Figure 30. Command Interface and Program Erase Controller Flowchart (b) . . . . . . . . . . . . . . . . 58 Figure 31. Command Interface and Program Erase Controller Flowchart (c) . . . . . . . . . . . . . . . . 59 Figure 32. Command Interface and Program Erase Controller Flowchart (d) . . . . . . . . . . . . . . . . 60 Figure 33. Command Interface and Program Erase Controller Flowchart (e) . . . . . . . . . . . . . . . . 61

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 30. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

SUMMARY DESCRIPTION

The M58BW016B/D is a 16Mbit non-volatile Flash memory that can be erased electrically at the block level and programmed in-system on a DoubleWord basis using a 2.7V to 3.6V VDD supply for the

circuit and a VDDQ supply down to 2.4V for the Input and Output buffers. Optionally a 12V VPP sup-

ply can be used to provide fast program and erase for a limited time and number of program/erase cycles.

The devices support Asynchronous (Latch Controlled and Page Read) and Synchronous Bus operations. The Synchronous Burst Read Interface allows a high data transfer rate controlled by the Burst Clock, K, signal. It is capable of bursting fixed or unlimited lengths of data. The burst type, latency and length are configurable and can be easily adapted to a large variety of system clock frequencies and microprocessors. All Writes are Asynchronous. On power-up the memory defaults to Read mode with an Asynchronous Bus.

The device has a boot block architecture with an array of 8 parameter block of 64Kb each and 31 main blocks of 512Kb each. The parameter blocks can be located at the top of the address space, M58BW016BT, M58BW016DT or at the bottom, M58BW016BB, M58BW016DB.

Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a Program or Erase operation can be detected and any error conditions identified in the Status Regis-

ter. The command set required to control the memory is consistent with JEDEC standards.

Erase can be suspended in order to perform either Read or Program in any other block and then resumed. Program can be suspended to Read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles.

All blocks are protected during power-up. The M58BW016B features four different levels of block protection to avoid unwanted program/erase operations. The WP pin offers an hardware protection on two of the parameter blocks and all of the main blocks. The Program and Erase commands can be password protected by the Tuning Protection command. All Program or Erase operations are blocked when Reset, RP, is held low. The M58BW016D offers the same protection features with the exception of the Tuning Block Protection which is disabled in the factory.

A Reset/Power-down mode is entered when the RP input is Low. In this mode the power consumption is lower than in the normal standby mode, the device is write protected and both the Status and the Burst Configuration Registers are cleared. A recovery time is required when the RP input goes High.

The memory is offered in PQFP80 (14 x 20mm) and LBGA80 (1.0mm pitch) packages and it is supplied with all the bits erased (set to ’1’).

6/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

Figure 2. Logic Diagram

VDD VDDQ VDDQIN VPP

A0-A18 DQ0-DQ31

K

L

EM58BW016BT

M58BW016BB

RP	M58BW016DT	R
G	M58BW016DB

GD

W

WP

B

VSS VSSQ

AI04155

Table 1. Signal Names

	A0-A18								Address inputs
	DQ0-DQ7								Data Input/Output, Command Input
	DQ8-DQ15								Data Input/Output, Burst Configuration
									Register
	DQ16-DQ31								Data Input/Output
									Burst Address Advance
	B
									Chip Enable
	E
									Output Enable
	G
	K								Burst Clock
									Latch Enable
	L
	R								Valid Data Ready (open drain output)
									Reset/Power-down
	RP
									Write Enable
	W
									Output Disable
	GD
									Write Protect
	WP
	VDD								Supply Voltage
	VDDQ								Power Supply for Output Buffers
	VDDQIN								Power Supply for Input Buffers only
	VPP								Optional Supply Voltage for Fast
									Program and Fast Erase Operations
	VSS								Ground
	VSSQ								Input/Output Ground
	NC								Not Connected Internally
	DU								Don’t Use as Internally Connected

7/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

Figure 3. LBGA Connections (Top view through package)

	1	2	3	4	5	6	7	8
A	A15	A14	VDD	VPP	VSS	A6	A3	A2
B	A16	A13	A12	A9	A8	A5	A4	A1
C	A17	A18	A11	A10	NC	A7	DU	A0
D	DQ3	DQ0	DU	DU	DU	DQ31	DQ30	DQ29
E	VDDQ	DQ4	DQ2	DQ1	DQ27	DQ28	DQ26	VDDQ
F	VSSQ	DQ7	DQ6	DQ5	NC	DQ25	DQ24	VSSQ
G	VDDQ	DQ8	DQ10	DQ9	DQ22	DQ21	DQ23	VDDQ
H	DQ13	DQ12	DQ11	WP	DQ17	DQ19	DQ18	DQ20
J	DQ15	DQ14	L	B	E	G	R	DQ16
K	VDDQIN	RP	K	VSS	VDD	W	GD	DU

AI04151b

8/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

Figure 4. PQFP Connections (Top view through package)

DQ16 1 DQ17 DQ18 DQ19 VDDQ

VSSQ

DQ20

DQ21

DQ22

DQ23

DQ24 DQ25 12 DQ26 DQ27 VDDQ

VSSQ

DQ28

DQ29

DQ30

DQ31 DU A0

A1

A2 24

DU

R

GD

WP

W

G E

DD

SS

NC

NC

K

RP

DDQIN

V

B V L

V

80

73

65

DQ15

64

DQ14

DQ13

DQ12

VSSQ

VDDQ

DQ11

DQ10

DQ9

DQ8

M58BW016BT

DQ7

M58BW016BB

53

DQ6

M58BW016DT

DQ5

M58BW016DB

DQ4

VSSQ

VDDQ

DQ3

DQ2

DQ1

DQ0

NC

A18

A17

25

32

41

A16

40

A3

A4

A5

A6

A7

SS

PP

DD

A11

A12

A13

A14

A15

A8 V

V

V A9 A10

AI04152b

9/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

Block Protection

The M58BW016B features four different levels of block protection. The M58BW016D has the same block protection with the exception of the Tuning Block Protection, which is disabled in the factory.

■Write Protect Pin, WP, - When WP is low, VIL, all the lockable parameter blocks (two upper (Top ) or lower (Bottom)) and all the main blocks are protected. When WP is high (VIH) all the lockable parameter blocks and all the main blocks are unprotected.

■Reset/Power-Down Pin, RP, - If the device is held in reset mode (RP at VIL), no program or erase operations can be performed on any block.

■Tuning Block Protection: M58BW016B features a 64 bit password protection for program and erase operations for a fixed number of blocks After power-up or reset the device is tuning protected. An Unlock command is provided to allow program or erase operations in all the blocks.

After a device reset the first two kinds of block protection (WP, RP) can be combined to give a flexible block protection. They do not affect the Tuning Block Protection. When the two protections are disabled, WP and RP at VIH, the blocks locked by the Tuning Block Protection cannot be modified. All blocks are protected during power-up.

Tuning Block Protection. The	Tuning Block
Protection is a software feature	to protect certain

blocks from program or erase operations. It allows the user to lock program and erase operations with a user definable 64 bit code. It is only available on the M58BW016B version.

The code is written once in the Tuning Protection Register and cannot be erased. When shipped the flash memory will have the Tuning Protection Code bits set to ‘1'. The user can program a ‘0’ in any of the 64 positions. Once programmed it is not possible to reset a bit to ‘1’ as the cells cannot be erased. The Tuning Protection Register can be programmed at any moment (after providing the correct code), however once all bits are set to ‘0’ the Tuning Protection Code can no longer be altered.

The Tuning Protection Code locks the program and erase operations of 2 parameter and 24 main blocks, blocks 0, 1 and 15-38 for the bottom configuration and the blocks 0-23, 37 and 38 for the top configuration.

The tuning blocks are "locked" if the tuning protection code has not been provided, and “unlocked" once the correct code has been provided. The tuning blocks are locked after reset or power-up. The tuning protection status can be monitored in the Status Register. Refer to the Status Register section.

Refer to the Command Interface section for the Tuning Protection Block Unlock and Tuning Protection Program commands. See Appendix B, Figure 25, 26 and 27 for suggested flowcharts for using the Tuning Block Protection commands. For further information on the Tuning Block Protection refer to Application Note, AN1361.

10/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

Table 2. Top Boot Block Addresses,

M58BW016BT, M58BW016DT

#	Size (Kbit)	Address Range	TP(1)
38	64	7F800h-7FFFFh	yes
37	64	7F000h-7F7FFh	yes
36	64	7E800h-7EFFFh	no
35	64	7E000h-7E7FFh	no
34	64	7D800h-7DFFFh	no
33	64	7D000h-7D7FFh	no
32	64	7C800h-7CFFFh	no
31	64	7C000h-7C7FFh	no
30	512	78000h-7BFFFh	no
29	512	74000h-77FFFh	no
28	512	70000h-73FFFh	no
27	512	6C000h-6FFFFh	no
26	512	68000h-6BFFFh	no
25	512	64000h-67FFFh	no
24	512	60000h-63FFFh	no
23	512	5C000h-5FFFFh	yes
22	512	58000h-5BFFFh	yes
21	512	54000h-57FFFh	yes
20	512	50000h-53FFFh	yes

#	Size (Kbit)	Address Range	TP(1)
19	512	4C000h-4FFFFh	yes
18	512	48000h-4BFFFh	yes
17	512	44000h-47FFFh	yes
16	512	40000h-43FFFh	yes
15	512	3C000h-3FFFFh	yes
14	512	38000h-3BFFFh	yes
13	512	34000h-37FFFh	yes
12	512	30000h-33FFFh	yes
11	512	2C000h-2FFFFh	yes
10	512	28000h-2BFFFh	yes
9	512	24000h-27FFFh	yes
8	512	20000h-23FFFh	yes
7	512	1C000h-1FFFFh	yes
6	512	18000h-1BFFFh	yes
5	512	14000h-17FFFh	yes
4	512	10000h-13FFFh	yes
3	512	0C000h-0FFFFh	yes
2	512	08000h-0BFFFh	yes
1	512	04000h-07FFFh	yes
0	512	00000h-03FFFh	yes

Note: 1. TP = Tuning Protected Block, only available for the M58BW016B.

11/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

Table 3. Bottom Boot Block Addresses,

M58BW016BB, M58BW016DB

#	Size (Kbit)	Address Range	TP(1)
38	512	7C000h-7FFFFh	yes
37	512	78000h-7BFFFh	yes
36	512	74000h-77FFFh	yes
35	512	70000h-73FFFh	yes
34	512	6C000h-6FFFFh	yes
33	512	68000h-6BFFFh	yes
32	512	64000h-67FFFh	yes
31	512	60000h-63FFFh	yes
30	512	5C000h-5FFFFh	yes
29	512	58000h-5BFFFh	yes
28	512	54000h-57FFFh	yes
27	512	50000h-53FFFh	yes
26	512	4C000h-4FFFFh	yes
25	512	48000h-4BFFFh	yes
24	512	44000h-47FFFh	yes
23	512	40000h-43FFFh	yes
22	512	3C000h-3FFFFh	yes
21	512	38000h-3BFFFh	yes
20	512	34000h-37FFFh	yes

12/63

#	Size (Kbit)	Address Range	TP(1)
19	512	30000h-33FFFh	yes
18	512	2C000h-2FFFFh	yes
17	512	28000h-2BFFFh	yes
16	512	24000h-27FFFh	yes
15	512	20000h-23FFFh	yes
14	512	1C000h-1FFFFh	no
13	512	18000h-1BFFFh	no
12	512	14000h-17FFFh	no
11	512	10000h-13FFFh	no
10	512	0C000h-0FFFFh	no
9	512	08000h-0BFFFh	no
8	512	04000h-07FFFh	no
7	64	03800h-03FFFh	no
6	64	03000h-037FFh	no
5	64	02800h-02FFFh	no
4	64	02000h-027FFh	no
3	64	01800h-01FFFh	no
2	64	01000h-017FFh	no
1	64	00800h-00FFFh	yes
0	64	00000h-007FFh	yes

Note: 1. TP = Tuning Protected Block, only available for the M58BW016B.

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

SIGNAL DESCRIPTIONS

See Figure 2, Logic Diagram and Table 1, Signal Names, for a brief overview of the signals connected to this device.

Address Inputs (A0-A18). The Address Inputs are used to select the cells to access in the memory array during Bus Read operations either to read or to program data to. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. Chip Enable must be low when selecting the addresses.

The address inputs are latched on the rising edge of Latch Enable L or Burst Clock K, whichever occurs first, in a read operation.The address inputs are latched on the rising edge of Chip Enable, Write Enable or Latch Enable, whichever occurs first in a Write operation. The address latch is transparent when Latch Enable is low, VIL. The address is internally latched in an Erase or Program operation.

Data Inputs/Outputs (DQ0-DQ31). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation, or are used to input the data during a program operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine. When used to input data or Write commands they are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first.

When Chip Enable and Output Enable are both

low, VIL, and Output Disable is at VIH, the data bus outputs data from the memory array, the Electron-

ic Signature, the CFI Information or the contents of the Status Register. The data bus is high impedance when the device is deselected with Chip Enable at VIH, Output Enable at VIH, Output Disable at VIL or Reset/Power-Down at VIL. The Status Register content is output on DQ0-DQ7 and DQ8DQ31 are at VIL.

Chip Enable (E). The Chip Enable, E, input activates the memory control logic, input buffers, decoders and sense amplifiers. Chip Enable, E, at VIH deselects the memory and reduces the power consumption to the Standby level.

Output Enable (G). The Output Enable, G, gates the outputs through the data output buffers during a read operation, when Output Disable GD is at VIH. When Output Enable G is at VIH, the outputs are high impedance independently of Output Disable.

Output Disable (GD). The Output Disable, GD, deactivates the data output buffers. When Output Disable, GD, is at VIH, the outputs are driven by the Output Enable. When Output Disable, GD, is at VIL, the outputs are high impedance independent-

ly of Output Enable. The Output Disable pin must be connected to an external pull-up resistor as there is no internal pull-up resistor to drive the pin.

Write Enable (W). The Write Enable, W, input controls writing to the Command Interface, Input Address and Data latches. Both addresses and data can be latched on the rising edge of Write Enable (also see Latch Enable, L).

Reset/Power-Down (RP). The Reset/PowerDown, RP, is used to apply a hardware reset to the memory. A hardware reset is achieved by holding

Reset/Power-Down Low, VIL, for at least tPLPH. Writing is inhibited to protect data, the Command

Interface and the Program/Erase Controller are reset. The Status Register information is cleared and power consumption is reduced to deep powerdown level. The device acts as deselected, that is the data outputs are high impedance.

After Reset/Power-Down goes High, VIH, the memory will be ready for Bus Read operations after a delay of tPHEL or Bus Write operations after tPHWL.

If Reset/Power-Down goes low, VIL, during a Block Erase, a Program or a Tuning Protection Program

the operation is aborted, in a time of tPLRH maximum, and data is altered and may be corrupted.

During Power-up power should be applied simulta-

neously to VDD and VDDQ(IN) with RP held at VIL. When the supplies are stable RP is taken to VIH.

Output Enable, G, Chip Enable, E, and Write Enable, W, should be held at VIH during power-up.

In an application, it is recommended to associate Reset/Power-Down pin, RP, with the reset signal of the microprocessor. Otherwise, if a reset operation occurs while the memory is performing an erase or program operation, the memory may output the Status Register information instead of being initialized to the default Asynchronous Random Read.

See Table 21 and Figure 18, Reset, Power-Down and Power-up Characteristics, for more details.

Latch Enable (L). The Bus Interface can be configured to latch the Address Inputs on the rising edge of Latch Enable, L, for Asynchronous Latch Enable Controlled Read or Write or Synchronous Burst Read operations. In Synchronous Burst Read operations the address is latched on the active edge of the Clock when Latch Enable is Low, VIL. Once latched, the addresses may change without affecting the address used by the memory. When Latch Enable is Low, VIL, the latch is transparent. Latch Enable, L, can remain at VIL for Asynchronous Random Read and Write operations.

Burst Clock (K). The Burst Clock, K, is used to synchronize the memory with the external bus dur-

13/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

ing Synchronous Burst Read operations. Bus signals are latched on the active edge of the Clock. The Clock can be configured to have an active rising or falling edge. In Synchronous Burst Read mode the address is latched on the first active clock edge when Latch Enable is low, VIL, or on the rising edge of Latch Enable, whichever occurs first.

During Asynchronous bus operations the Clock is not used.

Burst Address Advance (B). The Burst Address Advance, B, controls the advancing of the address by the internal address counter during Synchronous Burst Read operations.

Burst Address Advance, B, is only sampled on the active clock edge of the Clock when the X-latency time has expired. If Burst Address Advance is Low, VIL, the internal address counter advances. If Burst Address Advance is High, VIH, the internal address counter does not change; the same data remains on the Data Inputs/Outputs and Burst Address Advance is not sampled until the Y-latency expires.

The Burst Address Advance, B, may be tied to VIL.

Valid Data Ready (R). The Valid Data Ready output, R, is an open drain output that can be used, during Synchronous Burst Read operations, to identify if the memory is ready to output data or not. The Valid Data Ready output can be configured to be active on the clock edge of the invalid data read cycle or one cycle before. Valid Data Ready, at VIH, indicates that new data is or will be available. When Valid Data Ready is Low, VIL, the previous data outputs remain active.

In all Asynchronous operations, Valid Data Ready is high-impedance. It may be tied to other components with the same Valid Data Ready signal to create a unique system Ready signal. The Valid Data Ready output has an internal pull-up resistor of around 1 MΩ powered from VDDQ, designers should use an external pull-up resistor of the correct value to meet the external timing requirements for Valid Data Ready going to VIH.

Write Protect (WP). The Write Protect, WP, provides protection against program or erase operations. When Write Protect, WP, is at VIL the first two (in the bottom configuration) or last two (in the

top configuration) parameter blocks and all main blocks are locked. When Write Protect WP is at VIH all the blocks can be programmed or erased, if no other protection is used.

Supply Voltage (VDD). The Supply Voltage, VDD, is the core power supply. All internal circuits draw their current from the VDD pin, including the Program/Erase Controller.

Output Supply Voltage (VDDQ). The Output Supply Voltage, VDDQ, is the output buffer power supply

for all operations (Read, Program and Erase) used for DQ0-DQ31 when used as outputs.

Input Supply Voltage (VDDQIN). The Input Supply Voltage, VDDIN, is the power supply for all input

signal. Input signals are: K, B, L, W, GD, G, E, A0A18 and D0-D31, when used as inputs.

Program/Erase Supply Voltage (VPP). The Program/Erase Supply Voltage, VPP, is used for program and erase operations. The memory normally executes program and erase operations at VPP1 voltage levels. In a manufacturing environment, programming may be speeded up by applying a higher voltage level, VPPH, to the VPP pin.

The voltage level VPPH may be applied for a total of 80 hours over a maximum of 1000 cycles.

Stressing the device beyond these limits could damage the device.

Ground (VSS and VSSQ). The Ground VSS is the reference for the internal supply voltage VDD. The

Ground VSSQ is the reference for the output and input supplies VDDQ, and VDDQIN. It is essential to connect VSS and VSSQ together.

Note: A 0.1μF capacitor should be connected between the Supply Voltages, VDD, VDDQ and

VDDIN and the Grounds, VSS and VSSQ to decouple the current surges from the power supply.

The PCB track widths must be sufficient to carry the currents required during all operations of the parts, see Table 15, DC Characteristics, for maximum current supply requirements.

Don’t Use (DU). This pin should not be used as it is internally connected. Its voltage level can be between VSS and VDDQ or leave it unconnected.

Not Connected (NC). This pin is not physically connected to the device.

14/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

BUS OPERATIONS

Each bus operations that controls the memory is described in this section, see Tables 4, 5 and 6 Bus Operations, for a summary. The bus operation is selected through the Burst Configuration Register; the bits in this register are described at the end of this section.

On Power-up or after a Hardware Reset the memory defaults to Asynchronous Bus Read and Asynchronous Bus Write, no other bus operation can be performed until the Burst Control Register has been configured.

The Electronic Signature, CFI or Status Register will be read in asynchronous mode regardless of the Burst Control Register settings.

Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations.

Asynchronous Bus Operations

For asynchronous bus operations refer to Table 4 together with the following text.

Asynchronous Bus Read. Asynchronous Bus Read operations read from the memory cells, or specific registers (Electronic Signature, Status Register, CFI and Burst Configuration Register) in the Command Interface. A valid bus operation involves setting the desired address on the Address Inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable and Output Disable High, VIH. The Data Inputs/Outputs will output the value, see Figure 9, Asynchronous Bus Read AC Waveforms, and Table 16, Asynchronous Bus Read AC Characteristics, for details of when the output becomes valid.

Asynchronous Read is the default read mode which the device enters on power-up or on return from Reset/Power-Down.

Asynchronous Latch Controlled Bus Read.

Asynchronous Latch Controlled Bus Read operations read from the memory cells or specific registers in the Command Interface. The address is latched in the memory before the value is output on the data bus, allowing the address to change during the cycle without affecting the address that the memory uses.

A valid bus operation involves setting the desired address on the Address Inputs, setting Chip Enable and Latch Enable Low, VIL and keeping Write Enable High, VIH; the address is latched on the rising edge of Latch Enable. Once latched, the Address Inputs can change. Set Output Enable Low, VIL, to read the data on the Data Inputs/Outputs; see Figure 1, Asynchronous Latch Controlled Bus Read AC Waveforms and Table 17, Asynchronous Latch Controlled Bus Read AC Characteristics for details on when the output becomes valid.

Note that, since the Latch Enable input is transparent when set Low, VIL, Asynchronous Bus Read operations can be performed when the memory is configured for Asynchronous Latch Enable bus operations by holding Latch Enable Low, VIL throughout the bus operation.

Asynchronous Page Read. Asynchronous Page Read operations are used to read from several addresses within the same memory page. Each memory page is 4 Double-Words and is addressed by the address inputs A0 and A1.

Data is read internally and stored in the Page Buffer. Valid bus operations are the same as Asynchronous Bus Read operations but with different timings. The first read operation within the page has identical timings, subsequent reads within the same page have much shorter access times. If the page changes then the normal, longer timings apply again. Page Read does not support Latched Controlled Read.

See Figure 11, Asynchronous Page Read AC Waveforms and Table 18, Asynchronous Page Read AC Characteristics for details on when the outputs become valid.

Asynchronous Bus Write. Asynchronous Bus Write operations write to the Command Interface in order to send commands to the memory or to latch addresses and input data to program. Bus Write operations are asynchronous, the clock, K, is don’t care during Bus Write operations.

A valid Asynchronous Bus Write operation begins by setting the desired address on the Address Inputs, and setting Chip Enable, Write Enable and Latch Enable Low, VIL, and Output Enable High, VIH, or Output Disable Low, VIL. The Address Inputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Commands and Input Data are latched on the rising edge of Chip Enable, E, or Write Enable, W, whichever occurs first. Output Enable must remain High, and Output Disable Low, during the whole Asynchronous Bus Write operation.

See Figure 12, Asynchronous Write AC Waveforms, and Table 19, Asynchronous Write and Latch Controlled Write AC Characteristics, for details of the timing requirements.

Asynchronous Latch Controlled Bus Write.

Asynchronous Latch Controlled Bus Write operations write to the Command Interface in order to send commands to the memory or to latch addresses and input data to program. Bus Write operations are asynchronous, the clock, K, is don’t care during Bus Write operations.

A valid Asynchronous Latch Controlled Bus Write operation begins by setting the desired address on

15/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

the Address Inputs and pulsing Latch Enable Low, VIL. The Address Inputs are latched by the Command Interface on the rising edge of Latch Enable, Write Enable or Chip Enable, whichever occurs first. Commands and Input Data are latched on the rising edge of Chip Enable, E, or Write Enable, W, whichever occurs first. Output Enable must remain High, and Output Disable Low, during the whole Asynchronous Bus Write operation.

See Figure 13, Asynchronous Latch Controlled Write AC Waveforms, and Table 19, Asynchronous Write and Latch Controlled Write AC Characteristics, for details of the timing requirements.

Output Disable. The data outputs are high impedance when the Output Enable, G, is at VIH or Output Disable, GD, is at VIL.

Standby. When Chip Enable is High, VIH, and the Program/Erase Controller is idle, the memory enters Standby mode, the power consumption is reduced to the standby level and the Data Inputs/ Outputs pins are placed in the high impedance state regardless of Output Enable, Write Enable or Output Disable inputs.

Automatic Low Power. If there is no change in the state of the bus for a short period of time during Asynchronous Bus Read operations the memory

Table 4. Asynchronous Bus Operations

enters Auto Low Power mode where the internal Supply Current is reduced to the Auto-Standby Supply Current. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress.

Automatic Low Power is only available in Asynchronous Read modes.

Power-Down. The memory is in Power-down when Reset/Power-Down, RP, is at VIL. The power consumption is reduced to the power-down level and the outputs are high impedance, independent of the Chip Enable, E, Output Enable, G, Output Disable, GD, or Write Enable, W, inputs.

Electronic Signature. Two codes identifying the manufacturer and the device can be read from the memory allowing programming equipment or applications to automatically match their interface to the characteristics of the memory. The Electronic Signature is output by giving the Read Electronic Signature command. The manufacturer code is output when all the Address inputs are at VIL. The device code is output when A1 is at VIH and all the other address pins are at VIL. See Table 5. Issue a Read Memory Array command to return to Read mode.

Bus Operation

Step

E

G

GD

W

RP

L

A0-A18

DQ0-DQ31

Asynchronous Bus Read

VIL

VIL

VIH

VIH

VIH

VIL

Address

Data Output

Asynchronous Latch

Address Latch

VIL

VIH

VIH

VIL

VIH

VIL

Address

High Z

Controlled Bus Read

Read

VIL

VIL

VIH

VIH

VIH

VIH

X

Data Output

Asynchronous Page

VIL

VIL

VIH

VIH

VIH

X

Address

Data Output

Read

Asynchronous Bus Write

VIL

VIH

X

VIL

VIH

VIL

Address

Data Input

Asynchronous Latch

Address Latch

VIL

VIL

VIH

VIH

VIH

VIL

Address

High Z

Controlled Bus Write

Write

VIL

VIH

X

VIL

VIH

VIH

X

Data Input

Output Disable,

VIL

VIH

VIH

VIH

VIH

X

X

High Z

G

Output Disable,

VIL

VIL

VIL

VIH

VIH

X

X

High Z

GD

Standby

VIH

X

X

X

VIH

X

X

High Z

Reset/Power-Down

X

X

X

X

VIL

X

X

High Z

Note: X = Don’t Care

16/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

Table 5. Asynchronous Read Electronic Signature Operation

Code

Device

E

G

GD

W

A18-A0

DQ31-DQ0

Manufacturer

All

VIL

VIL

VIH

VIH

00000h

00000020h

Device

M58BW016xT(1)

VIL

VIL

VIH

VIH

00001h

00008836h

M58BW016xB(1)

VIL

VIL

VIH

VIH

00001h

00008835h

Burst Configuration

VIL

VIL

VIH

VIH

00005h

BCR (2)

Register

Note: 1. x= B or D version of the device.

2. BCR= Burst Configuration Register.

Synchronous Bus Operations

For synchronous bus operations refer to Table 6 together with the following text.

Synchronous Burst Read. Synchronous Burst Read operations are used to read from the memory at specific times synchronized to an external reference clock. The burst type, length and latency can be configured. The different configurations for Synchronous Burst Read operations are described in the Burst Configuration Register section. Refer to Figures 5 and 6 for examples of synchronous burst operations.

In continuous burst read, one burst read operation can access the entire memory sequentially by keeping the Burst Address Advance B at VIL for the appropriate number of clock cycles. At the end of the memory address space the burst read restarts from the beginning at address 000000h.

A valid Synchronous Burst Read operation begins when the Burst Clock is active and Chip Enable and Latch Enable are Low, VIL. The burst start address is latched and loaded into the internal Burst Address Counter on the valid Burst Clock K edge (rising or falling depending on the value of M6) or on the rising edge of Latch Enable, whichever occurs first.

After an initial memory latency time, the memory outputs data each clock cycle (or two clock cycles depending on the value of M9). The Burst Address Advance B input controls the memory burst output. The second burst output is on the next clock valid edge after the Burst Address Advance B has been pulled Low.

Valid Data Ready, R, monitors if the memory burst boundary is exceeded and the Burst Controller of the microprocessor needs to insert wait states.

When Valid Data Ready is Low on the active clock edge, no new data is available and the memory does not increment the internal address counter at the active clock edge even if Burst Address Advance, B, is Low.

Valid Data Ready may be configured (by bit M8 of Burst Configuration Register) to be valid immediately at the valid clock edge or one data cycle before the valid clock edge.

Synchronous Burst Read will be suspended if Burst Address Advance, B, goes High, VIH.

If Output Enable is at VIL and Output Disable is at VIH, the last data is still valid.

If Output Enable, G, is at VIH or Output Disable, GD, is at VIL, but the Burst Address Advance, B, is at VIL the internal Burst Address Counter is incremented at each Burst Clock K valid edge.

The Synchronous Burst Read timing diagrams and AC Characteristics are described in the AC and DC Parameters section. See Figures 14, 15, 16 and 17, and Table 20.

Synchronous Burst Read Suspend. During a Synchronous Burst Read operation it is possible to suspend the operation, freeing the data bus for other higher priority devices.

A valid Synchronous Burst Read operation is suspended when both Output Enable and Burst Address Advance are High, VIH. The Burst Address Advance going High, VIH, stops the burst counter and the Output Enable going High, VIH, inhibits the data outputs. The Synchronous Burst Read operation can be resumed by setting Output Enable Low.

17/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

Table 6. Synchronous Burst Read Bus Operations

K(3)

A0-A18

Bus Operation

Step

E

G

GD

RP

L

B

DQ0-DQ31

Address Latch

VIL

VIH

X

VIH

T

VIL

X

Address Input

Read

VIL

VIL

VIH

VIH

T

VIH

VIL

Data Output

Synchronous Burst

Read Suspend

VIL

VIH

X

VIH

X

VIH

VIH

High Z

Read

Read Resume

VIL

VIL

VIH

VIH

T

VIH

VIL

Data Output

Burst Address Advance

VIL

VIH

X

VIH

T

VIH

VIL

High Z

Read Abort,

VIH

X

X

VIH

X

X

X

High Z

E

Read Abort,

X

X

X

VIL

X

X

X

High Z

RP

Note: 1. X = Don't Care, VIL or VIH.

2.M15 = 0, Bit M15 is in the Burst Configuration Register.

3.T = transition, see M6 in the Burst Configuration Register for details on the active edge of K.

18/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

Burst Configuration Register

The Burst Configuration Register is used to configure the type of bus access that the memory will perform.

The Burst Configuration Register is set through the Command Interface and will retain its information until it is re-configured, the device is reset, or the device goes into Reset/Power-Down mode. The Burst Configuration Register bits are described in Table 7. They specify the selection of the burst length, burst type, burst X and Y latencies and the Read operation. Refer to Figures 5 and 6 for examples of synchronous burst configurations.

Read Select Bit (M15). The Read Select bit, M15, is used to switch between asynchronous and synchronous Bus Read operations. When the Read Select bit is set to ’1’, Bus Read operations are asynchronous; when the Read Select but is set to ’0’, Bus Read operations are synchronous.

On reset or power-up the Read Select bit is set to’1’ for asynchronous accesses.

X-Latency Bits (M14-M11). The X-Latency bits are used during Synchronous Bus Read operations to set the number of clock cycles between the address being latched and the first data becoming available. For correct operation the X-La- tency bits can only assume the values in Table 7, Burst Configuration Register. The X-Latency bits should also be selected in conjunction with Table , Burst Performance to ensure valid settings.

Y-Latency Bit (M9). The Y-Latency bit is used during Synchronous Bus Read operations to set the number of clock cycles between consecutive reads. The Y-Latency value depends on both the X-Latency value and the setting in M9.

When the Y-Latency is 1 the data changes each clock cycle; when the Y-Latency is 2 the data changes every second clock cycle. See Table 7, Burst Configuration Register and Table , Burst Performance, for valid combinations of the Y-La- tency, the X-Latency and the Clock frequency.

Valid Data Ready Bit (M8). The Valid Data Ready bit controls the timing of the Valid Data Ready output pin, R. When the Valid Data Ready bit is ’0’ the Valid Data Ready output pin is driven Low for the active clock edge when invalid data is output on the bus. When the Valid Data Ready bit is ’1’ the Valid Data Ready output pin is driven Low one clock cycle prior to invalid data being output on the bus.

Burst Type Bit (M7). The Burst Type bit is used to configure the sequence of addresses read as sequential or interleaved. When the Burst Type bit is ’0’ the memory outputs from interleaved addresses; when the Burst Type bit is ’1’ the memory outputs from sequential addresses. See Tables 8, Burst Type Definition, for the sequence of addresses output from a given starting address in each mode.

Valid Clock Edge Bit (M6). The Valid Clock Edge bit, M6, is used to configure the active edge of the Clock, K, during Synchronous Burst Read operations. When the Valid Clock Edge bit is ’0’ the falling edge of the Clock is the active edge; when the Valid Clock Edge bit is ’1’ the rising edge of the Clock is active.

Wrap Burst Bit (M3). The burst reads can be confined inside the 4 or 8 Double-Word boundary (wrap) or overcome the boundary (no wrap). The Wrap Burst bit is used to select between wrap and no wrap. When the Wrap Burst bit is set to ‘0’ the burst read wraps; when it is set to ‘1’ the burst read does not wrap.

Burst Length Bit (M2-M0). The Burst Length bits set the maximum number of Double-Words that can be output during a Synchronous Burst Read operation before the address wraps. Burst lengths of 4 or 8 are available for both the Sequential and Interleaved burst types, and a continuous burst is available for the Sequential type.

Table 7, Burst Configuration Register gives the valid combinations of the Burst Length bits that the memory accepts; Table 8, Burst Type Definition, gives the sequence of addresses output from a given starting address for each length.

If either a Continuous or a No Wrap Burst Read has been initiated the device will output data synchronously. Depending on the starting address, the device activates the Valid Data Ready output to indicate that a delay is necessary before the data is output. If the starting address is aligned to an 8 Double Word boundary, the continuous burst mode will run without activating the Valid Data Ready output. If the starting address is not aligned to an 8 Double Word boundary, Valid Data Ready is activated to indicate that the device needs an internal delay to read the successive words in the array.

M10, M5 and M4 are reserved for future use.

19/63