ST M50FW080 User Manual
查询M50FW080供应商
FEATURES SUMMARY
■ SUPPLY VOLTAGE
–V
–V
■ TWO INTERFACES
– Firmware Hub (FWH) Interface for
– Address/Address Multiplexed (A/A Mux)
■ FIRMWARE HUB (FWH) HARDWARE
INTERFACE MODE
– 5 Signal Communication Interface
– Hardware Write Protect Pins for Block
– Register Based Read and Write
– 5 Additional General Purpose Inputs for
– Synchronized with 33MHz PCI clock
■ PROGRAMMING TIME
– 10µs typical
– Quadruple Byte Programming Option
■ 16 UNIFORM 64 KByte MEMORY BLOCKS
■ PROGRAM/ERASE CONTROLLER
– Embedded Byte Program and Block/Chip
– Status Register Bits
■ PROGRAM and ERASE SUSPEND
– Read other Blocks during Program/Erase
– Program other Blocks during Erase
■ FOR USE in PC BIOS APPLICATIONS
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 2Dh
= 3V to 3.6V for Program, Erase and
CC
Read Operations
= 12V for Fast Program and Fast
PP
Erase (optional)
embedded operation with PC Chipsets
Interface for programming equipment
compatibility
supporting Read and Write Operations
Protection
Protection
platform design flexibility
Erase algorithms
Suspend
Suspend
M50FW080
8 Mbit (1M x8, Uniform Block)
3V Supply Firmware Hub Flash Memory
Figure 1. Packages
PLCC32 (K)
TSOP32 (NB)
8 x 14mm
TSOP40 (N)
10 x 20mm
1/47August 2004
M50FW080
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Logic Diagram (FWH Interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Logic Diagram (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 1. Signal Names (FWH Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Signal Names (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. PLCC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. TSOP32 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. TSOP40 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Firmware Hub (FWH) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Input/Output Communications (FWH0-FWH3).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Input Communication Frame (FWH4).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Identification Inputs (ID0-ID3).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
General Purpose Inputs (FGPI0-FGPI4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Interface Configuration (IC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Interface Reset (RP
CPU Reset (INIT
Clock (CLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Top Block Lock (TBL
Write Protect (WP
Reserved for Future Use (RFU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Address/Address Multiplexed (A/A Mux) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 11
Address Inputs (A0-A10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Output Enable (G
Write Enable (W
Row/Column Address Select (RC
Ready/Busy Output (RB
Supply Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
V
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CC
V
Optional Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PP
V
Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
SS
).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Firmware Hub (FWH) Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus Abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/47
M50FW080
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Address/Address Multiplexed (A/A Mux) Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. FWH Bus Read Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. FWH Bus Read Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. FWH Bus Write Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. FWH Bus Write Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6. A/A Mux Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 7. Manufacturer and Device Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Read Memory Array Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8. Read Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Quadruple Byte Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 9. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Program Status (Bit 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
V
Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PP
Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Block Protection Status (Bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 10. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
FIRMWARE HUB (FWH) INTERFACE CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . 21
Lock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Write Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Read Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Lock Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 11. Firmware Hub Register Configuration Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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M50FW080
Firmware Hub (FWH) General Purpose Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Manufacturer Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Device Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 12. Lock Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 13. General Purpose Input Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PROGRAM AND ERASE TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 14. Program and Erase Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 15. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 16. Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 17. FWH Interface AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 18. A/A Mux Interface AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 9. FWH Interface AC Testing Input Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 10.A/A Mux Interface AC Testing Input Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 19. Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 20. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 11.FWH Interface Clock Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 21. FWH Interface Clock Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 12.FWH Interface AC Signal Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 22. FWH Interface AC Signal Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 13.Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 23. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 14.A/A Mux Interface Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 24. A/A Mux Interface Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 15.A/A Mux Interface Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 25. A/A Mux Interface Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 16.PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Outline . . . . . . . . 35
Table 26. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Mechanical Data 36
Figure 17.TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Outline . . . . . . . . . . 37
Table 27. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Mechanical Data. . . 37
Figure 18.TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline. . . . . . . . . 38
Table 28. TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data . 38
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 29. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
APPENDIX A.FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 19.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 20.Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only) . . . . . 41
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Figure 21.Program Suspend and Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . 42
Figure 22.Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only) . . . . . . . . . . . . . . . . 43
Figure 23.Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 24.Erase Suspend and Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 45
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 30. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5/47
M50FW080
SUMMARY DESCRIPTION
The M50FW080 is an 8 Mbit (1Mbit x8) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed
using a single low voltage (3.0 to 3.6V) supply. For
fast programming and fast erasing in production
lines an optional 12V power supply can be used to
reduce the programming and the erasing times.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Blocks can be
protected individually to prevent accidental Program or Erase commands from modifying the
memory. Program and Erase commands are written to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase operation can be detected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.
Two different bus interfaces are supported by the
memory. The primary interface, the Firmware Hub
(or FWH) Interface, uses Intel’s proprietary FWH
protocol. This has been designed to remove the
need for the ISA bus in current PC Chipsets; the
M50FW080 acts as the PC BIOS on the Low Pin
Count bus for these PC Chipsets.
The secondary interface, the Address/Address
Multiplexed (or A/A Mux) Interface, is designed to
be compatible with current Flash Programmers for
production line programming prior to fitting to a PC
Motherboard.
6/47
M50FW080
Figure 2. Logic Diagram (FWH Interface)
V
V
CC
PP
ID0-ID3
FGPI0-
FGPI4
FWH4
CLK
IC
RP
INIT
4
5
M50FW080
V
SS
4
FWH0FWH3
WP
TBL
AI03979
Table 1. Signal Names (FWH Interface)
FWH0-FWH3 Input/Output Communications
FWH4 Input Communication Frame
ID0-ID3 Identification Inputs
FGPI0-FGPI4 General Purpose Inputs
IC Interface Configuration
RP
INIT
CLK Clock
TBL
WP
RFU
V
CC
V
PP
V
SS
NC Not Connected Internally
Interface Reset
CPU Reset
Top Block Lock
Write Protect
Reserved for Future Use. Leave
disconnected
Supply Voltage
Optional Supply Voltage for Fast
Erase Operations
Ground
Figure 3. Logic Diagram (A/A Mux Interface)
V
V
CC
PP
A0-A10
RC
IC
W
RP
11
M50FW080
G
V
SS
8
DQ0-DQ7
RB
AI03981
Table 2. Signal Names (A/A Mux Interface)
IC Interface Configuration
A0-A10 Address Inputs
DQ0-DQ7 Data Inputs/Outputs
G
W
RC
RB
RP
V
CC
V
PP
V
SS
NC Not Connected Internally
Output Enable
Write Enable
Row/Column Address Select
Ready/Busy Output
Interface Reset
Supply Voltage
Optional Supply Voltage for Fast
Program and Fast Erase Operations
Ground
7/47
M50FW080
Figure 4. PLCC Connections
A/A Mux A/A Mux
A7
FGPI1
A6
FGPI0
A5
A4
A3
A2
A1
A0
DQ0
Note: Pins 27 and 28 are not internally connected.
WP
TBL
ID3
ID2
ID1
ID0
FWH0
9
RPA8V
A9
RP
FGPI2
FGPI3
M50FW080
V
FWH1
FWH2
V
DQ1
DQ2
1
17
SS
SS
CC
PP
V
CC
PP
V
V
32
RFU
FWH3
DQ3
DQ4
RC
CLK
RFU
DQ5
A10
FGPI4
25
RFU
DQ6
IC (VIL)
NC
NC
V
SS
V
CC
INIT
FWH4
RFU
RFU
IC (VIH)
NC
NC
V
SS
V
CC
G
W
RB
DQ7
A/A MuxA/A Mux
AI04897
Figure 5. TSOP32 Connections
NC
NC
NC
NC
IC (VIH)
A10
RC
V
CC
V
PP
A/A Mux
RP
A9
A8
A7
A6
A5
A4 A3
NC
NC
NC
V
SS
GPI4
CLK
V
CC
V
PP
RP
GPI3
IC
1
8
9
M50FW080
32
25
24
INIT
FWH4/LFRAME
NC
RFU
RFU
RFU
RFU
FWH3/LAD3
V
SS
FWH2/LAD2
FWH1/LAD1
GPI2 FWH0/LAD0
GPI1 ID0
GPI0
WP
TBL
16 17
ID1
ID2
ID3
G
W
NC
DQ7
DQ6
DQ5
DQ4
DQ3
V
SS
DQ2
DQ1
DQ0
A0
A1
A2
A/A Mux
AI09757B
8/47
Figure 6. TSOP40 Connections
M50FW080
NC
IC (VIH)
NC
NC
NC
NC
A10
NC
RC
V
CC
V
PP
A/A Mux
RP
NC
NC
A9
A8
A7
A6
A5
A4 A3
NC
IC (VIL)
NC
NC INIT
NC RFU
NC
FGPI4
NC
CLK
V
CC
V
PP
RP
NC
NC
FGPI3
FGPI2 FWH0
FGPI1 ID0
FGPI0
WP
TBL
1
10
M50FW080
11
20 21
40
31
30
V
V
FWH4
RFU
RFU
RFU
RFU
V
V
V
FWH3
FWH2
FWH1
ID1
ID2
ID3
SS
CC
CC
SS
SS
V
SS
V
CC
W
G
RB
DQ7
DQ6
DQ5
DQ4
V
CC
V
SS
V
SS
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A/A Mux
AI03980
9/47
M50FW080
SIGNAL DESCRIPTIONS
There are two distinct bus interfaces available on
this device. The active interface is selected before
power-up, or during Reset, using the Interface
Configuration Pin, IC.
The signals for each interface are discussed in the
Firmware Hub (FWH) Signal Descriptions section
and the Address/Address Multiplexed (A/A Mux)
Signal Descriptions section, respectively, while
the supply signals are discussed in the Supply Sig-
nal Descriptions section.
Firmware Hub (FWH) Signal Descriptions
For the Firmware Hub (FWH) Interface see Figure
2. and Table 1..
Input/Output Communications (FWH0-FWH3).
All Input and Output Communication with the
memory take place on these pins. Addresses and
Data for Bus Read and Bus Write operations are
encoded on these pins.
Input Communication Frame (FWH4). The Input Communication Frame (FWH4) signals the
start of a bus operation. When Input Communication Frame is Low, V
Clock a new bus operation is initiated. If Input
Communication Frame is Low, V
operation then the operation is aborted. When Input Communication Frame is High, V
rent bus operation is proceeding or the bus is idle.
Identification Inputs (ID0-ID3). The Identification Inputs select the address that the memory responds to. Up to 16 memories can be addressed
on a bus. For an address bit to be ‘0’ the pin can
be left floating or driven Low, V
down resistor is included with a value of R
an address bit to be ‘1’ the pin must be driven
High, V
; there will be a leakage current of I
IH
through each pin when pulled to VIH; see Table
20..
By convention the boot memory must have address ‘0000’ and all additional memories take sequential addresses starting from ‘0001’.
General Purpose Inputs (FGPI0-FGPI4). The
General Purpose Inputs can be used as digital inputs for the CPU to read. The General Purpose Input Register holds the values on these pins. The
pins must have stable data from before the start of
the cycle that reads the General Purpose Input
Register until after the cycle is complete. These
pins must not be left to float, they should be driven
Low, V
or High, VIH.
IL,
Interface Configuration (IC). The Interface Configuration input selects whether the Firmware Hub
(FWH) or the Address/Address Multiplexed (A/A
Mux) Interface is used. The chosen interface must
be selected before power-up or during a Reset
and, thereafter, cannot be changed. The state of
, on the rising edge of the
IL
, during a bus
IL
, the cur-
IH
; an internal pull-
IL
IL
. For
LI2
the Interface Configuration, IC, should not be
changed during operation.
To select the Firmware Hub (FWH) Interface the
Interface Configuration pin should be left to float or
driven Low, V
; to select the Address/Address
IL
Multiplexed (A/A Mux) Interface the pin should be
driven High, V
included with a value of R
current of I
. An internal pull-down resistor is
IH
through each pin when pulled to VIH;
LI2
; there will be a leakage
IL
see Table 20..
Interface Reset (RP
). The Interface Reset (RP)
input is used to reset the memory. When Interface
Reset (RP
) is set Low, VIL, the memory is in Reset
mode: the outputs are put to high impedance and
the current consumption is minimized. When RP
set High, V
, the memory is in normal operation.
IH
is
After exiting Reset mode, the memory enters
Read mode.
CPU Reset (INIT
). The CPU Reset, INIT, pin is
used to Reset the memory when the CPU is reset.
It behaves identically to Interface Reset, RP
, and
the internal Reset line is the logical OR (electrical
AND) of RP
and INIT.
Clock (CLK). The Clock, CLK, input is used to
clock the signals in and out of the Input/Output
Communication Pins, FWH0-FWH3. The Clock
conforms to the PCI specification.
Top Block Lock (TBL
). The Top Block Lock in-
put is used to prevent the Top Block (Block 15)
from being changed. When Top Block Lock, TBL
is set Low, V
, Program and Block Erase opera-
IL
tions in the Top Block have no effect, regardless of
the state of the Lock Register. When Top Block
Lock, TBL
, is set High, VIH, the protection of the
Block is determined by the Lock Register. The
state of Top Block Lock, TBL
, does not affect the
protection of the Main Blocks (Blocks 0 to 14).
Top Block Lock, TBL
, must be set prior to a Program or Block Erase operation is initiated and
must not be changed until the operation completes
or unpredictable results may occur. Care should
be taken to avoid unpredictable behavior by
changing TBL
Write Protect (WP
during Program or Erase Suspend.
). The Write Protect input is
used to prevent the Main Blocks (Blocks 0 to 14)
from being changed. When Write Protect, WP
set Low, V
, Program and Block Erase operations
IL
, is
in the Main Blocks have no effect, regardless of
the state of the Lock Register. When Write Protect,
, is set High, VIH, the protection of the Block
WP
determined by the Lock Register. The state of
Write Protect, WP
, does not affect the protection of
the Top Block (Block 15).
Write Protect, WP
, must be set prior to a Program
or Block Erase operation is initiated and must not
be changed until the operation completes or un-
,
10/47
M50FW080
predictable results may occur. Care should be taken to avoid unpredictable behavior by changing
during Program or Erase Suspend.
WP
Reserved for Future Use (RFU). These pins do
not have assigned functions in this revision of the
part. They must be left disconnected.
Table 3. Block Addresses
Size
(Kbytes)
64 F0000h-FFFFFh 15 Top Block
64 E0000h-EFFFFh 14 Main Block
64 D0000h-DFFFFh 13 Main Block
64 C0000h-CFFFFh 12 Main Block
64 B0000h-BFFFFh 11 Main Block
64 A0000h-AFFFFh 10 Main Block
64 90000h-9FFFFh 9 Main Block
64 80000h-8FFFFh 8 Main Block
64 70000h-7FFFFh 7 Main Block
64 60000h-6FFFFh 6 Main Block
64 50000h-5FFFFh 5 Main Block
64 40000h-4FFFFh 4 Main Block
64 30000h-3FFFFh 3 Main Block
64 20000h-2FFFFh 2 Main Block
64 10000h-1FFFFh 1 Main Block
64 00000h-0FFFFh 0 Main Block
Address Range
Block
Number
Block Type
Address/Address Multiplexed (A/A Mux)
Signal Descriptions
For the Address/Address Multiplexed (A/A Mux)
Interface see Figure 3. and Table 2..
Address Inputs (A0-A10). The Address Inputs
are used to set the Row Address bits (A0-A10) and
the Column Address bits (A11-A19). They are
latched during any bus operation by the Row/Column Address Select input, RC
.
Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs hold the data that is written to or read
from the memory. They output the data stored at
the selected address during a Bus Read operation. During Bus Write operations they represent
the commands sent to the Command Interface of
the internal state machine. The Data Inputs/Outputs, DQ0-DQ7, are latched during a Bus Write
operation.
Output Enable (G
). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W
). The Write Enable, W, controls
the Bus Write operation of the memory’s Command Interface.
Row/Column Address Select (RC
). The Row/
Column Address Select input selects whether the
Address Inputs should be latched into the Row Address bits (A0-A10) or the Column Address bits
(A11-A19). The Row Address bits are latched on
the falling edge of RC
whereas the Column Ad-
dress bits are latched on the rising edge.
Ready/Busy Output (RB
). The Ready/Busy pin
gives the status of the memory’s Program/Erase
Controller. When Ready/Busy is Low, V
OL
, the
memory is busy with a Program or Erase operation
and it will not accept any additional Program or
Erase command except the Program/Erase Suspend command. When Ready/Busy is High, V
OH
the memory is ready for any Read, Program or
Erase operation.
Supply Signal Descriptions
The Supply Signals are the same for both interfaces.
Supply Voltage. The VCC Supply Voltage
V
CC
supplies the power for all operations (Read, Program, Erase etc.).
The Command Interface is disabled when the V
CC
Supply Voltage is less than the Lockout Voltage,
. This prevents Bus Write operations from ac-
V
LKO
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memory contents being altered will be invalid. After V
CC
becomes valid the Command Interface is reset to
Read mode.
A 0.1µF capacitor should be connected between
the V
Supply Voltage pins and the VSS Ground
CC
pin to decouple the current surges from the power
supply. Both V
Supply Voltage pins must be
CC
connected to the power supply. The PCB track
widths must be sufficient to carry the currents required during program and erase operations.
Optional Supply Voltage. The VPP Optional
V
PP
Supply Voltage pin is used to select the Fast Program (see the Quadruple Byte Program Command
description) and Fast Erase options of the memory
and to protect the memory. When V
PP
< V
PPLK
Program and Erase operations cannot be performed and an error is reported in the Status Register if an attempt to change the memory contents
is made. When V
erations take place as normal. When V
= VCC Program and Erase op-
PP
PP
= V
PPH
Fast Program (if A/A Mux interface is selected)
and Fast Erase operations are used. Any other
voltage input to V
will result in undefined behav-
PP
ior and should not be used.
,
11/47
M50FW080
VPP should not be set to V
for more than 80
PPH
hours during the life of the memory.
BUS OPERATIONS
The two interfaces have similar bus operations but
the signals and timings are completely different.
The Firmware Hub (FWH) Interface is the usual interface and all of the functionality of the part is
available through this interface. Only a subset of
functions are available through the Address/Address Multiplexed (A/A Mux) Interface.
See the sections: The Firmware Hub (FWH) Bus
Operations and Address/Address Multiplexed (A/
A Mux) Bus Operations, for details of the bus op-
erations on each interface.
Firmware Hub (FWH) Bus Operations
The Firmware Hub (FWH) Interface consists of
four data signals (FWH0-FWH3), one control line
(FWH4) and a clock (CLK). In addition protection
against accidental or malicious data corruption
can be achieved using two further signals (TBL
and WP). Finally two reset signals (RP and INIT)
are available to put the memory into a known
state.
The data signals, control signal and clock are designed to be compatible with PCI electrical specifications. The interface operates with clock speeds
up to 33MHz.
The following operations can be performed using
the appropriate bus cycles: Bus Read, Bus Write,
Standby, Reset and Block Protection.
Bus Read. Bus Read operations read from the
memory cells, specific registers in the Command
Interface or Firmware Hub Registers. A valid Bus
Read operation starts when Input Communication
Frame, FWH4, is Low, V
correct Start cycle is on FWH0-FWH3. On the following clock cycles the Host will send the Memory
ID Select, Address and other control bits on
FWH0-FWH3. The memory responds by outputting Sync data until the wait-states have elapsed
followed by Data0-Data3 and Data4-Data7.
See Table 4. and Figure 7., for a description of the
Field definitions for each clock cycle of the transfer. See Table 22. and Figure 12., for details on the
timings of the signals.
Bus Write. Bus Write operations write to the
Command Interface or Firmware Hub Registers. A
valid Bus Write operation starts when Input Communication Frame, FWH4, is Low, V
rises and the correct Start cycle is on FWH0FWH3. On the following Clock cycles the Host will
send the Memory ID Select, Address, other control
bits, Data0-Data3 and Data4-Data7 on FWH0-
, as Clock rises and the
IL
, as Clock
IL
VSS Ground. VSS is the reference for all the volt-
age measurements.
FWH3. The memory outputs Sync data until the
wait-states have elapsed.
See Table 5. and Figure 8., for a description of the
Field definitions for each clock cycle of the transfer. See Table 22. and Figure 12., for details on the
timings of the signals.
Bus Abort. The Bus Abort operation can be used
to immediately abort the current bus operation. A
Bus Abort occurs when FWH4 is driven Low, V
IL
during the bus operation; the memory will tri-state
the Input/Output Communication pins, FWH0FWH3.
Note that, during a Bus Write operation, the Command Interface starts executing the command as
soon as the data is fully received; a Bus Abort during the final TAR cycles is not guaranteed to abort
the command; the bus, however, will be released
immediately.
Standby. When FWH4 is High, V
, the memory
IH
is put into Standby mode where FWH0-FWH3 are
put into a high-impedance state and the Supply
Current is reduced to the Standby level, I
CC1
.
Reset. During Reset mode all internal circuits are
switched off, the memory is deselected and the
outputs are put in high-impedance. The memory is
in Reset mode when Interface Reset, RP
Reset, INIT
Low, V
, is Low, VIL. RP or INIT must be held
, for t
IL
. The memory resets to Read
PLPH
, or CPU
mode upon return from Reset mode and the Lock
Registers return to their default states regardless
of their state before Reset, see Table 14.. If RP
goes Low, VIL, during a Program or Erase op-
INIT
or
eration, the operation is aborted and the memory
cells affected no longer contain valid data; the
memory can take up to t
to abort a Program
PLRH
or Erase operation.
Block Protection. Block Protection can be
forced using the signals Top Block Lock, TBL
Write Protect, WP
, regardless of the state of the
, and
Lock Registers.
Address/Address Multiplexed (A/A Mux) Bus
Operations
The Address/Address Multiplexed (A/A Mux) Interface has a more traditional style interface. The signals consist of a multiplexed address signals (A0A10), data signals, (DQ0-DQ7) and three control
signals (RC
, G, W). An additional signal, RP, can
be used to reset the memory.
The Address/Address Multiplexed (A/A Mux) Inter-
face is included for use by Flash Programming
,
12/47
M50FW080
equipment for faster factory programming. Only a
subset of the features available to the Firmware
Hub (FWH) Interface are available; these include
all the Commands but exclude the Security features and other registers.
The following operations can be performed using
the appropriate bus cycles: Bus Read, Bus Write,
Output Disable and Reset.
When the Address/Address Multiplexed (A/A Mux)
Interface is selected all the blocks are unprotected. It is not possible to protect any blocks through
this interface.
Bus Read. Bus Read operations are used to output the contents of the Memory Array, the Electronic Signature and the Status Register. A valid
Bus Read operation begins by latching the Row
Address and Column Address signals into the
memory using the Address Inputs, A0-A10, and
the Row/Column Address Select RC
Enable (W
High, V
) and Interface Reset (RP) must be
, and Output Enable, G, Low, VIL, in order
IH
. Then Write
to perform a Bus Read operation. The Data Inputs/
Outputs will output the value, see Figure 14. and
Table 24., for details of when the output becomes
valid.
Table 4. FWH Bus Read Field Definitions
Clock
Cycle
Number
1 1 START 1101b I
2 1 IDSEL XXXX I
Clock
Cycle
Count
Field
FWH0-
FWH3
Memory
I/O
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by latching the Row Address and Column
Address signals into the memory using the Address Inputs, A0-A10, and the Row/Column Address Select RC
Data Inputs/Outputs; Output Enable, G
face Reset, RP
able, W
, must be Low, VIL. The Data Inputs/
. The data should be set up on the
, and Inter-
, must be High, VIH and Write En-
Outputs are latched on the rising edge of Write Enable, W
. See Figure 15. and Table 25., for details
of the timing requirements.
Output Disable. The data outputs are high-im-
pedance when the Output Enable, G
, is at VIH.
Reset. During Reset mode all internal circuits are
switched off, the memory is deselected and the
outputs are put in high-impedance. The memory is
in Reset mode when RP
held Low, V
IL
for t
PLPH
is Low, VIL. RP must be
. If RP is goes Low, VIL, during a Program or Erase operation, the operation is
aborted and the memory cells affected no longer
contain valid data; the memory can take up to t
to abort a Program or Erase operation.
RH
Description
On the rising edge of CLK with FWH4 Low, the contents of
FWH0-FWH3 indicate the start of a FWH Read cycle.
Indicates which FWH Flash Memory is selected. The value
on FWH0-FWH3 is compared to the IDSEL strapping on the
FWH Flash Memory pins to select which FWH Flash
Memory is being addressed.
PL-
3-9 7 ADDR XXXX I
10 1 MSIZE 0000b I Always 0000b (only single byte transfers are supported).
11 1 TAR 1111b I
12 1 TAR
13-14 2 WSYNC 0101b O
15 1 RSYNC 0000b O
16-17 2 DATA XXXX O
1111b
(float)
A 28-bit address phase is transferred starting with the most
significant nibble first.
The host drives FWH0-FWH3 to 1111b to indicate a
turnaround cycle.
The FWH Flash Memory takes control of FWH0-FWH3
O
during this cycle.
The FWH Flash Memory drives FWH0-FWH3 to 0101b
(short wait-sync) for two clock cycles, indicating that the data
is not yet available. Two wait-states are always included.
The FWH Flash Memory drives FWH0-FWH3 to 0000b,
indicating that data will be available during the next clock
cycle.
Data transfer is two CLK cycles, starting with the least
significant nibble.
13/47
M50FW080
Clock
Cycle
Number
18 1 TAR 1111b O
19 1 TAR
Clock
Cycle
Count
Field
FWH0-
FWH3
1111b
(float)
Memory
I/O
N/A
Description
The FWH Flash Memory drives FWH0-FWH3 to 1111b to
indicate a turnaround cycle.
The FWH Flash Memory floats its outputs, the host takes
control of FWH0-FWH3.
Figure 7. FWH Bus Read Waveforms
CLK
FWH4
FWH0-FWH3
Number of
clock cycles
START IDSEL ADDR MSIZE TAR SYNC DATA TAR
11712322
Table 5. FWH Bus Write Field Definitions
Clock
Cycle
Number
1 1 START 1110b I
2 1 IDSEL XXXX I
3-9 7 ADDR XXXX I
10 1 MSIZE 0000b I Always 0000b (single byte transfer).
Clock
Cycle
Count
Field
FWH0-
FWH3
Memory
I/O
Description
On the rising edge of CLK with FWH4 Low, the contents of
FWH0-FWH3 indicate the start of a FWH Write Cycle.
Indicates which FWH Flash Memory is selected. The value
on FWH0-FWH3 is compared to the IDSEL strapping on the
FWH Flash Memory pins to select which FWH Flash
Memory is being addressed.
A 28-bit address phase is transferred starting with the most
significant nibble first.
AI03437
11-12 2 DATA XXXX I
13 1 TAR 1111b I
14 1 TAR
1111b
(float)
15 1 SYNC 0000b O
16 1 TAR 1111b O
17 1 TAR
1111b
(float)
14/47
O
N/A
Data transfer is two cycles, starting with the least significant
nibble.
The host drives FWH0-FWH3 to 1111b to indicate a
turnaround cycle.
The FWH Flash Memory takes control of FWH0-FWH3
during this cycle.
The FWH Flash Memory drives FWH0-FWH3 to 0000b,
indicating it has received data or a command.
The FWH Flash Memory drives FWH0-FWH3 to 1111b,
indicating a turnaround cycle.
The FWH Flash Memory floats its outputs and the host takes
control of FWH0-FWH3.
Figure 8. FWH Bus Write Waveforms
CLK
FWH4
M50FW080
FWH0-FWH3
Number of
clock cycles
START IDSEL ADDR MSIZE DATA TAR SYNC TAR
11712212
Table 6. A/A Mux Bus Operations
Operation G W RP
Bus Read
Bus Write
Output Disable
Reset
V
IL
V
IH
V
IH
V
or V
IL
IH
V
IH
V
IL
V
IH
VIL or V
Table 7. Manufacturer and Device Codes
Operation G
Manufacturer Code
Device Code
V
IL
V
IL
W RP A19-A1 A0 DQ7-DQ0
V
IH
V
IH
AI03441
V
PP
V
IH
V
IH
V
IH
IH
V
IL
V
IH
V
IH
Don’t Care Data Output
VCC or V
PPH
Don’t Care Hi-Z
Don’t Care Hi-Z
V
IL
V
IL
V
IL
V
IH
DQ7-DQ0
Data Input
20h
2Dh
15/47
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