ST M50FW080 User Manual

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查询M50FW080供应商

FEATURES SUMMARY

■ SUPPLY VOLTAGE

–V

■ TWO INTERFACES

– Firmware Hub (FWH) Interface for

– Address/Address Multiplexed (A/A Mux)

■ FIRMWARE HUB (FWH) HARDWARE

INTERFACE MODE – 5 Signal Communication Interface

– Hardware Write Protect Pins for Block

– Register Based Read and Write

– 5 Additional General Purpose Inputs for

– Synchronized with 33MHz PCI clock

■ PROGRAMMING TIME

– 10µs typical – Quadruple Byte Programming Option

■ 16 UNIFORM 64 KByte MEMORY BLOCKS

■ PROGRAM/ERASE CONTROLLER

– Embedded Byte Program and Block/Chip

– Status Register Bits

■ PROGRAM and ERASE SUSPEND

– Read other Blocks during Program/Erase

– Program other Blocks during Erase

■ FOR USE in PC BIOS APPLICATIONS

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h – Device Code: 2Dh

= 3V to 3.6V for Program, Erase and

Read Operations

= 12V for Fast Program and Fast

Erase (optional)

embedded operation with PC Chipsets

Interface for programming equipment compatibility

supporting Read and Write Operations

Protection

platform design flexibility

Erase algorithms

Suspend

M50FW080

8 Mbit (1M x8, Uniform Block)

3V Supply Firmware Hub Flash Memory

Figure 1. Packages

PLCC32 (K)

TSOP32 (NB)

8 x 14mm

TSOP40 (N)

10 x 20mm

1/47August 2004

M50FW080

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Logic Diagram (FWH Interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3. Logic Diagram (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 1. Signal Names (FWH Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2. Signal Names (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4. PLCC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 5. TSOP32 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 6. TSOP40 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Firmware Hub (FWH) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Input/Output Communications (FWH0-FWH3).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Input Communication Frame (FWH4).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Identification Inputs (ID0-ID3).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

General Purpose Inputs (FGPI0-FGPI4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Interface Configuration (IC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Interface Reset (RP CPU Reset (INIT

Clock (CLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Top Block Lock (TBL Write Protect (WP

Reserved for Future Use (RFU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 3. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Address/Address Multiplexed (A/A Mux) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 11

Address Inputs (A0-A10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Output Enable (G Write Enable (W Row/Column Address Select (RC Ready/Busy Output (RB

Supply Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Optional Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

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BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Firmware Hub (FWH) Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Bus Abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

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Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Address/Address Multiplexed (A/A Mux) Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 4. FWH Bus Read Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 7. FWH Bus Read Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 5. FWH Bus Write Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 8. FWH Bus Write Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 6. A/A Mux Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 7. Manufacturer and Device Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Read Memory Array Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 8. Read Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Quadruple Byte Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 9. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Program Status (Bit 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Block Protection Status (Bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 10. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

FIRMWARE HUB (FWH) INTERFACE CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . 21

Lock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Write Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Read Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Lock Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 11. Firmware Hub Register Configuration Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

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M50FW080

Firmware Hub (FWH) General Purpose Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Manufacturer Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Device Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 12. Lock Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 13. General Purpose Input Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

PROGRAM AND ERASE TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Table 14. Program and Erase Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 15. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 16. Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 17. FWH Interface AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 18. A/A Mux Interface AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 9. FWH Interface AC Testing Input Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 10.A/A Mux Interface AC Testing Input Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 19. Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 20. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 11.FWH Interface Clock Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 21. FWH Interface Clock Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 12.FWH Interface AC Signal Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 22. FWH Interface AC Signal Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 13.Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 23. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 14.A/A Mux Interface Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 24. A/A Mux Interface Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 15.A/A Mux Interface Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 25. A/A Mux Interface Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 16.PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Outline . . . . . . . . 35

Table 26. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Mechanical Data 36

Figure 17.TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Outline . . . . . . . . . . 37

Table 27. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Mechanical Data. . . 37

Figure 18.TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline. . . . . . . . . 38

Table 28. TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data . 38

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 29. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

APPENDIX A.FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 19.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 20.Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only) . . . . . 41

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Figure 21.Program Suspend and Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . 42

Figure 22.Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only) . . . . . . . . . . . . . . . . 43

Figure 23.Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 24.Erase Suspend and Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 45

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 30. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

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M50FW080

SUMMARY DESCRIPTION

The M50FW080 is an 8 Mbit (1Mbit x8) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (3.0 to 3.6V) supply. For fast programming and fast erasing in production lines an optional 12V power supply can be used to reduce the programming and the erasing times.

The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Blocks can be protected individually to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end

of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.

Two different bus interfaces are supported by the memory. The primary interface, the Firmware Hub (or FWH) Interface, uses Intel’s proprietary FWH protocol. This has been designed to remove the need for the ISA bus in current PC Chipsets; the M50FW080 acts as the PC BIOS on the Low Pin Count bus for these PC Chipsets.

The secondary interface, the Address/Address Multiplexed (or A/A Mux) Interface, is designed to be compatible with current Flash Programmers for production line programming prior to fitting to a PC Motherboard.

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M50FW080

Figure 2. Logic Diagram (FWH Interface)

ID0-ID3

FGPI0-

FGPI4

FWH4

CLK

INIT

M50FW080

FWH0FWH3

TBL

AI03979

Table 1. Signal Names (FWH Interface)

FWH0-FWH3 Input/Output Communications

FWH4 Input Communication Frame

ID0-ID3 Identification Inputs

FGPI0-FGPI4 General Purpose Inputs

IC Interface Configuration

INIT

CLK Clock

TBL

RFU

NC Not Connected Internally

Interface Reset

CPU Reset

Top Block Lock

Write Protect

Reserved for Future Use. Leave disconnected

Supply Voltage

Optional Supply Voltage for Fast Erase Operations

Ground

Figure 3. Logic Diagram (A/A Mux Interface)

A0-A10

M50FW080

DQ0-DQ7

AI03981

Table 2. Signal Names (A/A Mux Interface)

IC Interface Configuration

A0-A10 Address Inputs

DQ0-DQ7 Data Inputs/Outputs

NC Not Connected Internally

Output Enable

Write Enable

Row/Column Address Select

Ready/Busy Output

Interface Reset

Supply Voltage

Optional Supply Voltage for Fast Program and Fast Erase Operations

Ground

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M50FW080

Figure 4. PLCC Connections

A/A Mux A/A Mux

FGPI1

FGPI0 A5 A4 A3 A2 A1 A0

DQ0

Note: Pins 27 and 28 are not internally connected.

TBL

ID3 ID2 ID1 ID0

FWH0

RPA8V

FGPI2

FGPI3

M50FW080

FWH1

FWH2

DQ1

DQ2

RFU

FWH3

DQ3

DQ4

CLK

RFU

DQ5

A10

FGPI4

RFU

DQ6

IC (VIL) NC NC V

INIT FWH4 RFU RFU

IC (VIH) NC NC V

G W RB DQ7

A/A MuxA/A Mux

AI04897

Figure 5. TSOP32 Connections

NC NC NC NC

IC (VIH)

A10

A/A Mux

A9 A8 A7 A6 A5 A4 A3

GPI4

CLK

GPI3

8 9

M50FW080

25 24

INIT FWH4/LFRAME

NC RFU RFU RFU RFU

FWH3/LAD3 V

FWH2/LAD2

FWH1/LAD1 GPI2 FWH0/LAD0 GPI1 ID0 GPI0

TBL

16 17

ID1

ID2

ID3

G W

NC DQ7 DQ6 DQ5 DQ4

DQ3 V

DQ2 DQ1 DQ0 A0 A1 A2

A/A Mux

AI09757B

8/47

Figure 6. TSOP40 Connections

M50FW080

IC (VIH)

NC NC NC NC

A10

NC RC

A/A Mux

RP NC NC

A9 A8 A7 A6 A5 A4 A3

IC (VIL)

NC NC INIT NC RFU NC

FGPI4

CLK

RP NC

NC FGPI3 FGPI2 FWH0 FGPI1 ID0 FGPI0

TBL

M50FW080

20 21

31 30

V V FWH4

RFU RFU RFU RFU V V V FWH3 FWH2 FWH1

ID1 ID2 ID3

SS CC

CC SS SS

W G RB DQ7 DQ6 DQ5 DQ4 V

DQ3 DQ2 DQ1 DQ0 A0 A1 A2

A/A Mux

AI03980

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M50FW080

SIGNAL DESCRIPTIONS

There are two distinct bus interfaces available on this device. The active interface is selected before power-up, or during Reset, using the Interface Configuration Pin, IC.

The signals for each interface are discussed in the

Firmware Hub (FWH) Signal Descriptions section

and the Address/Address Multiplexed (A/A Mux)

Signal Descriptions section, respectively, while

the supply signals are discussed in the Supply Sig-

nal Descriptions section.

Firmware Hub (FWH) Signal Descriptions

For the Firmware Hub (FWH) Interface see Figure

2. and Table 1..

Input/Output Communications (FWH0-FWH3).

All Input and Output Communication with the memory take place on these pins. Addresses and Data for Bus Read and Bus Write operations are encoded on these pins.

Input Communication Frame (FWH4). The Input Communication Frame (FWH4) signals the start of a bus operation. When Input Communication Frame is Low, V Clock a new bus operation is initiated. If Input Communication Frame is Low, V operation then the operation is aborted. When Input Communication Frame is High, V rent bus operation is proceeding or the bus is idle.

Identification Inputs (ID0-ID3). The Identification Inputs select the address that the memory responds to. Up to 16 memories can be addressed on a bus. For an address bit to be ‘0’ the pin can be left floating or driven Low, V down resistor is included with a value of R an address bit to be ‘1’ the pin must be driven High, V

; there will be a leakage current of I

through each pin when pulled to VIH; see Table

20..

By convention the boot memory must have address ‘0000’ and all additional memories take sequential addresses starting from ‘0001’.

General Purpose Inputs (FGPI0-FGPI4). The General Purpose Inputs can be used as digital inputs for the CPU to read. The General Purpose Input Register holds the values on these pins. The pins must have stable data from before the start of the cycle that reads the General Purpose Input Register until after the cycle is complete. These pins must not be left to float, they should be driven Low, V

or High, VIH.

IL,

Interface Configuration (IC). The Interface Configuration input selects whether the Firmware Hub (FWH) or the Address/Address Multiplexed (A/A Mux) Interface is used. The chosen interface must be selected before power-up or during a Reset and, thereafter, cannot be changed. The state of

, on the rising edge of the

, during a bus

, the cur-

; an internal pull-

. For

LI2

the Interface Configuration, IC, should not be changed during operation.

To select the Firmware Hub (FWH) Interface the Interface Configuration pin should be left to float or driven Low, V

; to select the Address/Address

Multiplexed (A/A Mux) Interface the pin should be driven High, V included with a value of R current of I

. An internal pull-down resistor is

through each pin when pulled to VIH;

LI2

; there will be a leakage

see Table 20..

Interface Reset (RP

). The Interface Reset (RP)

input is used to reset the memory. When Interface Reset (RP

) is set Low, VIL, the memory is in Reset mode: the outputs are put to high impedance and the current consumption is minimized. When RP set High, V

, the memory is in normal operation.

After exiting Reset mode, the memory enters Read mode.

CPU Reset (INIT

). The CPU Reset, INIT, pin is

used to Reset the memory when the CPU is reset. It behaves identically to Interface Reset, RP

, and the internal Reset line is the logical OR (electrical AND) of RP

and INIT.

Clock (CLK). The Clock, CLK, input is used to clock the signals in and out of the Input/Output Communication Pins, FWH0-FWH3. The Clock conforms to the PCI specification.

Top Block Lock (TBL

). The Top Block Lock in-

put is used to prevent the Top Block (Block 15) from being changed. When Top Block Lock, TBL is set Low, V

, Program and Block Erase opera-

tions in the Top Block have no effect, regardless of the state of the Lock Register. When Top Block Lock, TBL

, is set High, VIH, the protection of the Block is determined by the Lock Register. The state of Top Block Lock, TBL

, does not affect the

protection of the Main Blocks (Blocks 0 to 14). Top Block Lock, TBL

, must be set prior to a Program or Block Erase operation is initiated and must not be changed until the operation completes or unpredictable results may occur. Care should be taken to avoid unpredictable behavior by changing TBL

Write Protect (WP

during Program or Erase Suspend.

). The Write Protect input is

used to prevent the Main Blocks (Blocks 0 to 14) from being changed. When Write Protect, WP set Low, V

, Program and Block Erase operations

, is

in the Main Blocks have no effect, regardless of the state of the Lock Register. When Write Protect,

, is set High, VIH, the protection of the Block

WP determined by the Lock Register. The state of Write Protect, WP

, does not affect the protection of

the Top Block (Block 15). Write Protect, WP

, must be set prior to a Program or Block Erase operation is initiated and must not be changed until the operation completes or un-

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M50FW080

predictable results may occur. Care should be taken to avoid unpredictable behavior by changing

during Program or Erase Suspend.

WP Reserved for Future Use (RFU). These pins do

not have assigned functions in this revision of the part. They must be left disconnected.

Table 3. Block Addresses

Size

(Kbytes)

64 F0000h-FFFFFh 15 Top Block

64 E0000h-EFFFFh 14 Main Block

64 D0000h-DFFFFh 13 Main Block 64 C0000h-CFFFFh 12 Main Block

64 B0000h-BFFFFh 11 Main Block

64 A0000h-AFFFFh 10 Main Block

64 90000h-9FFFFh 9 Main Block 64 80000h-8FFFFh 8 Main Block

64 70000h-7FFFFh 7 Main Block

64 60000h-6FFFFh 6 Main Block 64 50000h-5FFFFh 5 Main Block

64 40000h-4FFFFh 4 Main Block

64 30000h-3FFFFh 3 Main Block

64 20000h-2FFFFh 2 Main Block 64 10000h-1FFFFh 1 Main Block

64 00000h-0FFFFh 0 Main Block

Address Range

Block

Number

Block Type

Address/Address Multiplexed (A/A Mux) Signal Descriptions

For the Address/Address Multiplexed (A/A Mux) Interface see Figure 3. and Table 2..

Address Inputs (A0-A10). The Address Inputs are used to set the Row Address bits (A0-A10) and the Column Address bits (A11-A19). They are latched during any bus operation by the Row/Column Address Select input, RC

Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs hold the data that is written to or read from the memory. They output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine. The Data Inputs/Outputs, DQ0-DQ7, are latched during a Bus Write operation.

Output Enable (G

). The Output Enable, G, con-

trols the Bus Read operation of the memory.

Write Enable (W

). The Write Enable, W, controls

the Bus Write operation of the memory’s Command Interface.

Row/Column Address Select (RC

). The Row/

Column Address Select input selects whether the Address Inputs should be latched into the Row Address bits (A0-A10) or the Column Address bits (A11-A19). The Row Address bits are latched on the falling edge of RC

whereas the Column Ad-

dress bits are latched on the rising edge.

Ready/Busy Output (RB

). The Ready/Busy pin

gives the status of the memory’s Program/Erase Controller. When Ready/Busy is Low, V

, the memory is busy with a Program or Erase operation and it will not accept any additional Program or Erase command except the Program/Erase Suspend command. When Ready/Busy is High, V

the memory is ready for any Read, Program or Erase operation.

Supply Signal Descriptions

The Supply Signals are the same for both interfaces.

Supply Voltage. The VCC Supply Voltage

supplies the power for all operations (Read, Program, Erase etc.).

The Command Interface is disabled when the V

Supply Voltage is less than the Lockout Voltage,

. This prevents Bus Write operations from ac-

LKO

cidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. After V

becomes valid the Command Interface is reset to Read mode.

A 0.1µF capacitor should be connected between the V

Supply Voltage pins and the VSS Ground

pin to decouple the current surges from the power supply. Both V

Supply Voltage pins must be

connected to the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations.

Optional Supply Voltage. The VPP Optional

Supply Voltage pin is used to select the Fast Program (see the Quadruple Byte Program Command description) and Fast Erase options of the memory and to protect the memory. When V

< V

PPLK

Program and Erase operations cannot be performed and an error is reported in the Status Register if an attempt to change the memory contents is made. When V erations take place as normal. When V

= VCC Program and Erase op-

= V

PPH

Fast Program (if A/A Mux interface is selected) and Fast Erase operations are used. Any other voltage input to V

will result in undefined behav-

ior and should not be used.

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M50FW080

VPP should not be set to V

for more than 80

PPH

hours during the life of the memory.

BUS OPERATIONS

The two interfaces have similar bus operations but the signals and timings are completely different. The Firmware Hub (FWH) Interface is the usual interface and all of the functionality of the part is available through this interface. Only a subset of functions are available through the Address/Address Multiplexed (A/A Mux) Interface.

See the sections: The Firmware Hub (FWH) Bus

Operations and Address/Address Multiplexed (A/ A Mux) Bus Operations, for details of the bus op-

erations on each interface.

Firmware Hub (FWH) Bus Operations

The Firmware Hub (FWH) Interface consists of four data signals (FWH0-FWH3), one control line (FWH4) and a clock (CLK). In addition protection against accidental or malicious data corruption can be achieved using two further signals (TBL and WP). Finally two reset signals (RP and INIT) are available to put the memory into a known state.

The data signals, control signal and clock are designed to be compatible with PCI electrical specifications. The interface operates with clock speeds up to 33MHz.

The following operations can be performed using the appropriate bus cycles: Bus Read, Bus Write, Standby, Reset and Block Protection.

Bus Read. Bus Read operations read from the memory cells, specific registers in the Command Interface or Firmware Hub Registers. A valid Bus Read operation starts when Input Communication Frame, FWH4, is Low, V correct Start cycle is on FWH0-FWH3. On the following clock cycles the Host will send the Memory ID Select, Address and other control bits on FWH0-FWH3. The memory responds by outputting Sync data until the wait-states have elapsed followed by Data0-Data3 and Data4-Data7.

See Table 4. and Figure 7., for a description of the Field definitions for each clock cycle of the transfer. See Table 22. and Figure 12., for details on the timings of the signals.

Bus Write. Bus Write operations write to the Command Interface or Firmware Hub Registers. A valid Bus Write operation starts when Input Communication Frame, FWH4, is Low, V rises and the correct Start cycle is on FWH0FWH3. On the following Clock cycles the Host will send the Memory ID Select, Address, other control bits, Data0-Data3 and Data4-Data7 on FWH0-

, as Clock rises and the

, as Clock

VSS Ground. VSS is the reference for all the volt- age measurements.

FWH3. The memory outputs Sync data until the wait-states have elapsed.

See Table 5. and Figure 8., for a description of the Field definitions for each clock cycle of the transfer. See Table 22. and Figure 12., for details on the timings of the signals.

Bus Abort. The Bus Abort operation can be used to immediately abort the current bus operation. A Bus Abort occurs when FWH4 is driven Low, V

during the bus operation; the memory will tri-state the Input/Output Communication pins, FWH0FWH3.

Note that, during a Bus Write operation, the Command Interface starts executing the command as soon as the data is fully received; a Bus Abort during the final TAR cycles is not guaranteed to abort the command; the bus, however, will be released immediately.

Standby. When FWH4 is High, V

, the memory

is put into Standby mode where FWH0-FWH3 are put into a high-impedance state and the Supply Current is reduced to the Standby level, I

CC1

Reset. During Reset mode all internal circuits are switched off, the memory is deselected and the outputs are put in high-impedance. The memory is in Reset mode when Interface Reset, RP Reset, INIT Low, V

, is Low, VIL. RP or INIT must be held

, for t

. The memory resets to Read

PLPH

, or CPU

mode upon return from Reset mode and the Lock Registers return to their default states regardless of their state before Reset, see Table 14.. If RP

goes Low, VIL, during a Program or Erase op-

INIT

eration, the operation is aborted and the memory cells affected no longer contain valid data; the memory can take up to t

to abort a Program

PLRH

or Erase operation. Block Protection. Block Protection can be

forced using the signals Top Block Lock, TBL Write Protect, WP

, regardless of the state of the

, and

Lock Registers.

Address/Address Multiplexed (A/A Mux) Bus Operations

The Address/Address Multiplexed (A/A Mux) Interface has a more traditional style interface. The signals consist of a multiplexed address signals (A0A10), data signals, (DQ0-DQ7) and three control signals (RC

, G, W). An additional signal, RP, can

be used to reset the memory. The Address/Address Multiplexed (A/A Mux) Inter-

face is included for use by Flash Programming

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M50FW080

equipment for faster factory programming. Only a subset of the features available to the Firmware Hub (FWH) Interface are available; these include all the Commands but exclude the Security features and other registers.

The following operations can be performed using the appropriate bus cycles: Bus Read, Bus Write, Output Disable and Reset.

When the Address/Address Multiplexed (A/A Mux) Interface is selected all the blocks are unprotected. It is not possible to protect any blocks through this interface.

Bus Read. Bus Read operations are used to output the contents of the Memory Array, the Electronic Signature and the Status Register. A valid Bus Read operation begins by latching the Row Address and Column Address signals into the memory using the Address Inputs, A0-A10, and the Row/Column Address Select RC Enable (W High, V

) and Interface Reset (RP) must be

, and Output Enable, G, Low, VIL, in order

. Then Write

to perform a Bus Read operation. The Data Inputs/ Outputs will output the value, see Figure 14. and

Table 24., for details of when the output becomes

valid.

Table 4. FWH Bus Read Field Definitions

Clock Cycle

Number

1 1 START 1101b I

2 1 IDSEL XXXX I

Clock Cycle

Count

Field

FWH0-

FWH3

Memory

I/O

Bus Write. Bus Write operations write to the

Command Interface. A valid Bus Write operation begins by latching the Row Address and Column Address signals into the memory using the Address Inputs, A0-A10, and the Row/Column Address Select RC Data Inputs/Outputs; Output Enable, G face Reset, RP able, W

, must be Low, VIL. The Data Inputs/

. The data should be set up on the

, and Inter-

, must be High, VIH and Write En-

Outputs are latched on the rising edge of Write Enable, W

. See Figure 15. and Table 25., for details

of the timing requirements. Output Disable. The data outputs are high-im-

pedance when the Output Enable, G

, is at VIH.

Reset. During Reset mode all internal circuits are switched off, the memory is deselected and the outputs are put in high-impedance. The memory is in Reset mode when RP held Low, V

for t

PLPH

is Low, VIL. RP must be

. If RP is goes Low, VIL, during a Program or Erase operation, the operation is aborted and the memory cells affected no longer contain valid data; the memory can take up to t

to abort a Program or Erase operation.

Description

On the rising edge of CLK with FWH4 Low, the contents of FWH0-FWH3 indicate the start of a FWH Read cycle.

Indicates which FWH Flash Memory is selected. The value on FWH0-FWH3 is compared to the IDSEL strapping on the FWH Flash Memory pins to select which FWH Flash Memory is being addressed.

PL-

3-9 7 ADDR XXXX I

10 1 MSIZE 0000b I Always 0000b (only single byte transfers are supported).

11 1 TAR 1111b I

12 1 TAR

13-14 2 WSYNC 0101b O

15 1 RSYNC 0000b O

16-17 2 DATA XXXX O

1111b

(float)

A 28-bit address phase is transferred starting with the most significant nibble first.

The host drives FWH0-FWH3 to 1111b to indicate a turnaround cycle.

The FWH Flash Memory takes control of FWH0-FWH3

during this cycle.

The FWH Flash Memory drives FWH0-FWH3 to 0101b (short wait-sync) for two clock cycles, indicating that the data is not yet available. Two wait-states are always included.

The FWH Flash Memory drives FWH0-FWH3 to 0000b, indicating that data will be available during the next clock cycle.

Data transfer is two CLK cycles, starting with the least significant nibble.

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M50FW080

Clock Cycle

Number

18 1 TAR 1111b O

19 1 TAR

Clock Cycle

Count

Field

FWH0-

FWH3

1111b

(float)

Memory

I/O

N/A

Description

The FWH Flash Memory drives FWH0-FWH3 to 1111b to indicate a turnaround cycle.

The FWH Flash Memory floats its outputs, the host takes control of FWH0-FWH3.

Figure 7. FWH Bus Read Waveforms

CLK

FWH4

FWH0-FWH3

Number of clock cycles

START IDSEL ADDR MSIZE TAR SYNC DATA TAR

11712322

Table 5. FWH Bus Write Field Definitions

Clock Cycle

Number

1 1 START 1110b I

2 1 IDSEL XXXX I

3-9 7 ADDR XXXX I

10 1 MSIZE 0000b I Always 0000b (single byte transfer).

Clock Cycle

Count

Field

FWH0-

FWH3

Memory

I/O

Description

On the rising edge of CLK with FWH4 Low, the contents of FWH0-FWH3 indicate the start of a FWH Write Cycle.

Indicates which FWH Flash Memory is selected. The value on FWH0-FWH3 is compared to the IDSEL strapping on the FWH Flash Memory pins to select which FWH Flash Memory is being addressed.

A 28-bit address phase is transferred starting with the most significant nibble first.

AI03437

11-12 2 DATA XXXX I

13 1 TAR 1111b I

14 1 TAR

1111b

(float)

15 1 SYNC 0000b O

16 1 TAR 1111b O

17 1 TAR

1111b

(float)

14/47

N/A

Data transfer is two cycles, starting with the least significant nibble.

The host drives FWH0-FWH3 to 1111b to indicate a turnaround cycle.

The FWH Flash Memory takes control of FWH0-FWH3 during this cycle.

The FWH Flash Memory drives FWH0-FWH3 to 0000b, indicating it has received data or a command.

The FWH Flash Memory drives FWH0-FWH3 to 1111b, indicating a turnaround cycle.

The FWH Flash Memory floats its outputs and the host takes control of FWH0-FWH3.

Figure 8. FWH Bus Write Waveforms

CLK

FWH4

M50FW080

FWH0-FWH3

Number of clock cycles

START IDSEL ADDR MSIZE DATA TAR SYNC TAR

11712212

Table 6. A/A Mux Bus Operations

Operation G W RP

Bus Read

Bus Write

Output Disable

Reset

or V

VIL or V

Table 7. Manufacturer and Device Codes

Operation G

Manufacturer Code

Device Code

W RP A19-A1 A0 DQ7-DQ0

AI03441

Don’t Care Data Output

VCC or V

PPH

Don’t Care Hi-Z

DQ7-DQ0

Data Input

20h

2Dh

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M50FW080

COMMAND INTERFACE

All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations.

After power-up or a Reset operation the memory enters Read mode.

The commands are summarized in Table 9., Commands. The following text descriptions should be read in conjunction with Table 9..

Read Memory Array Command. The Read Memory Array command returns the memory to its Read mode where it behaves like a ROM or EPROM. One Bus Write cycle is required to issue the Read Memory Array command and return the memory to Read mode. Once the command is issued the memory remains in Read mode until another command is issued. From Read mode Bus Read operations will access the memory array.

While the Program/Erase Controller is executing a Program or Erase operation the memory will not accept the Read Memory Array command until the operation completes.

Read Status Register Command. The Read Status Register command is used to read the Status Register. One Bus Write cycle is required to issue the Read Status Register command. Once the command is issued subsequent Bus Read operations read the Status Register until another command is issued. See the section on the Status Register for details on the definitions of the Status Register bits.

Read Electronic Signature Command. The Read Electronic Signature command is used to read the Manufacturer Code and the Device Code. One Bus Write cycle is required to issue the Read Electronic Signature command. Once the command is issued subsequent Bus Read operations read the Manufacturer Code or the Device Code until another command is issued.

After the Read Electronic Signature Command is issued the Manufacturer Code and Device Code can be read using Bus Read operations using the addresses in Table 8..

Table 8. Read Electronic Signature

Code Address Data

Manufacturer Code 00000h 20h

Device Code 00001h 2Dh

Program Command. The Program command can be used to program a value to one address in the memory array at a time. Two Bus Write operations are required to issue the command; the second Bus Write cycle latches the address and data

in the internal state machine and starts the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits.

If the address falls in a protected block then the Program operation will abort, the data in the memory array will not be changed and the Status Register will output the error.

During the Program operation the memory will only accept the Read Status Register command and the Program/Erase Suspend command. All other commands will be ignored. Typical Program times are given in Table 14..

Note that the Program command cannot change a bit set at ‘0’ back to ‘1’ and attempting to do so will not cause any modification on its value. One of the Erase commands must be used to set all of the bits in the block to ‘1’.

See Figure 19., for a suggested flowchart on using the Program command.

Quadruple Byte Program Command. The Quadruple Byte Program Command can be only used in A/A Mux mode to program four adjacent bytes in the memory array at a time. The four bytes must differ only for the addresses A0 and A10. Programming should not be attempted when V not at V

is below V

. The operation can also be executed if

PPH

, but result could be uncertain.

PPH

Five Bus Write operations are required to issue the command. The second, the third and the fourth Bus Write cycle latches respectively the address and data of the first, the second and the third byte in the internal state machine. The fifth Bus Write cycle latches the address and data of the fourth byte in the internal state machine and starts the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits.

During the Quadruple Byte Program operation the memory will only accept the Read Status register command and the Program/Erase Suspend command. All other commands will be ignored. Typical Quadruple Byte Program times are given in Table

8..

Note that the Quadruple Byte Program command cannot change a bit set to ‘0’ back to ‘1’ and attempting to do so will not cause any modification on its value. One of the Erase commands must be used to set all of the bits in the block to ‘1’.

See Figure 20., Quadruple Byte Program Flowchart and Pseudo Code, for a suggested flowchart on using the Quadruple Byte Program command.

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M50FW080

Chip Erase Command. The Chip Erase Com-

mand can be only used in A/A Mux mode to erase the entire chip at a time. Erasing should not be attempted when V

is not at V

can also be executed if V

is below V

. The operation

PPH

, but result could be uncertain. Two Bus Write operations are required to issue the command and start the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Chip Erase operation the memory will only accept the Read Status Register command. All other commands will be ignored. Typical Chip Erase times are given in Table 14.. The Chip Erase command sets all of the bits in the memory to ‘1’. See Figure 22., for a suggested flowchart on using the Chip Erase command.

Block Erase Command. The Block Erase command can be used to erase a block. Two Bus Write operations are required to issue the command; the second Bus Write cycle latches the block address in the internal state machine and starts the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits.

If the block is protected then the Block Erase operation will abort, the data in the block will not be changed and the Status Register will output the error.

During the Block Erase operation the memory will only accept the Read Status Register command and the Program/Erase Suspend command. All other commands will be ignored. Typical Block Erase times are given in Table 14..

The Block Erase command sets all of the bits in the block to ‘1’. All previous data in the block is lost.

See Figure 22., for a suggested flowchart on using the Erase command.

Clear Status Register Command. The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status Register to ‘0’. One Bus Write is required to issue the Clear Status Register command. Once the command is issued the memory returns to its previous mode, subsequent Bus Read operations continue to output the same data.

The bits in the Status Register are sticky and do not automatically return to ‘0’ when a new Program or Erase command is issued. If an error occurs then it is essential to clear any error bits in the Status Register by issuing the Clear Status Register command before attempting a new Program or Erase command.

Program/Erase Suspend Command. The Program/Erase Suspend command can be used to pause a Program or Block Erase operation. One Bus Write cycle is required to issue the Program/ Erase Suspend command and pause the Program/Erase Controller. Once the command is issued it is necessary to poll the Program/Erase Controller Status bit to find out when the Program/ Erase Controller has paused; no other commands will be accepted until the Program/Erase Controller has paused. After the Program/Erase Controller has paused, the memory will continue to output the Status Register until another command is issued.

During the polling period between issuing the Program/Erase Suspend command and the Program/ Erase Controller pausing it is possible for the operation to complete. Once Program/Erase Controller Status bit indicates that the Program/Erase Controller is no longer active, the Program Suspend Status bit or the Erase Suspend Status bit can be used to determine if the operation has completed or is suspended. For timing on the delay between issuing the Program/Erase Suspend command and the Program/Erase Controller pausing see Table 14..

During Program/Erase Suspend the Read Memory Array, Read Status Register, Read Electronic Signature and Program/Erase Resume commands will be accepted by the Command Interface. Additionally, if the suspended operation was Block Erase then the Program command will also be accepted; only the blocks not being erased may be read or programmed correctly.

See Figure 21., and Figure 24., for suggested flowcharts on using the Program/Erase Suspend command.

Program/Erase Resume Command. The Program/Erase Resume command can be used to restart the Program/Erase Controller after a Program/Erase Suspend has paused it. One Bus Write cycle is required to issue the Program/Erase Resume command. Once the command is issued subsequent Bus Read operations read the Status Register.

17/47

M50FW080

Table 9. Commands

Bus Write Operations

Command

Cycles

Read Memory Array 1 X FFh

Read Status Register 1 X 70h

Read Electronic Signature

1X 90h 1X 98h

2X 40hPAPD

Program

2X 10hPAPD

Quadruple Byte Program 5 X 30h

Chip Erase 2 X 80h X 10h

Block Erase 2 X 20h BA D0h

Clear Status Register 1 X 50h Program/Erase Suspend 1 X B0h

Program/Erase Resume 1 X D0h

1X 00h 1X 01h

Invalid/Reserved

1X 60h

1X 2Fh

1XC0h

Note: X Don’t Care, PA Program Address, PD Program Data, A

Read Memory Array. After a Read Memory Array command, read the memory as normal until another command is issued. Read Status Register. After a Read Status Register command, read the Status Register as normal until another command is issued. Read Electronic Signature. After a Read Electronic Signature command, read Manufacturer Code, Device Code until another com-

mand is issued. Block Erase, Program. After these commands read the Status Register until the command completes and another command is issued. Quadruple Byte Program. This command is only valid in A/A Mux mode. Addresses A differing only for address bit A0 and A10. After this command read the Status Register until the command completes and another command is issued. Chip Erase. This command is only valid in A/A Mux mode. After this command read the Status Register until the command completes and another command is issued.

Clear Status Register. After the Clear Status Register command bits 1, 3, 4 and 5 in the Status Register are reset to ‘0’. Program/Erase Suspend. After the Program/Erase Suspend command has been accepted, issue Read Memory Array, Read Status

Register, Program (during Erase suspend) and Program/Erase resume commands. Program/Erase Resume. After the Program/Erase Resume command the suspended Program/Erase operation resumes, read the Status Register until the Program/Erase Controller completes and the memory returns to Read Mode.

Invalid/Reserved. Do not use Invalid or Reserved commands.

1st 2nd 3rd 4th 5th

Addr Data Addr Data Addr Data Addr Data Addr Data

Consecutive Addresses, BA Any address in the Block.

1,2,3,4

, A2, A3 and A4 must be conse cutive addresses

18/47

STATUS REGISTER

The Status Register provides information on the current or previous Program or Erase operation. Different bits in the Status Register convey different information and errors on the operation.

To read the Status Register the Read Status Register command can be issued. The Status Register is automatically read after Program, Erase and Program/Erase Resume commands are issued. The Status Register can be read from any address.

The Status Register bits are summarized in Table

10.. The following text descriptions should be read

in conjunction with Table 10.. Program/Erase Controller Status (Bit 7). The

Program/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive. When the Program/Erase Controller Status bit is ‘0’, the Program/Erase Controller is active; when the bit is ‘1’, the Program/Erase Controller is inactive.

The Program/Erase Controller Status is ‘0’ immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is ‘1’.

During Program and Erase operation the Program/Erase Controller Status bit can be polled to find the end of the operation. The other bits in the Status Register should not be tested until the Program/Erase Controller completes the operation and the bit is ‘1’.

After the Program/Erase Controller completes its operation the Erase Status, Program Status, V Status and Block Protection Status bits should be tested for errors.

Erase Suspend Status (Bit 6). The Erase Suspend Status bit indicates that a Block Erase operation has been suspended and is waiting to be resumed. The Erase Suspend Status should only be considered valid when the Program/Erase Controller Status bit is ‘1’ (Program/Erase Controller inactive); after a Program/Erase Suspend command is issued the memory may still complete the operation rather than entering the Suspend mode.

When the Erase Suspend Status bit is ‘0’ the Program/Erase Controller is active or has completed its operation; when the bit is ‘1’ a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command.

When a Program/Erase Resume command is issued the Erase Suspend Status bit returns to ‘0’.

Erase Status (Bit 5). The Erase Status bit can be used to identify if the memory has applied the maximum number of erase pulses to the block(s)

M50FW080

and still failed to verify that the block(s) has erased correctly. The Erase Status bit should be read once the Program/Erase Controller Status bit is ‘1’ (Program/Erase Controller inactive).

When the Erase Status bit is ‘0’ the memory has successfully verified that the block(s) has erased correctly; when the Erase Status bit is ‘1’ the Program/Erase Controller has applied the maximum number of pulses to the block(s) and still failed to verify that the block(s) has erased correctly.

Once the Erase Status bit is set to ‘1’ it can only be reset to ‘0’ by a Clear Status Register command or a hardware reset. If it is set to ‘1’ it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail.

Program Status (Bit 4). The Program Status bit can be used to identify if the memory has applied the maximum number of program pulses to the byte and still failed to verify that the byte has programmed correctly. The Program Status bit should be read once the Program/Erase Controller Status bit is ‘1’ (Program/Erase Controller inactive).

When the Program Status bit is ‘0’ the memory has successfully verified that the byte has programmed correctly; when the Program Status bit is ‘1’ the Program/Erase Controller has applied the maximum number of pulses to the byte and still failed to verify that the byte has programmed correctly.

Once the Program Status bit is set to ‘1’ it can only be reset to ‘0’ by a Clear Status Register command or a hardware reset. If it is set to ‘1’ it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail.

Status (Bit 3). The VPP Status bit can be

used to identify an invalid voltage on the V during Program and Erase operations. The V pin is only sampled at the beginning of a Program or Erase operation. Indeterminate results can occur if V

becomes invalid during a Program or

Erase operation. When the V

pin was sampled at a valid voltage; when the

Status bit is ‘1’ the VPP pin has a voltage that

is below the V

Status bit is ‘0’ the voltage on the

Lockout Voltage, V

memory is protected; Program and Erase operation cannot be performed.

Once the V

Status bit set to ‘1’ it can only be re-

set to ‘0’ by a Clear Status Register command or a hardware reset. If it is set to ‘1’ it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail.

PPLK

, the

19/47

M50FW080

Program Suspend Status (Bit 2). The Program

Suspend Status bit indicates that a Program operation has been suspended and is waiting to be resumed. The Program Suspend Status should only be considered valid when the Program/Erase Controller Status bit is ‘1’ (Program/Erase Controller inactive); after a Program/Erase Suspend command is issued the memory may still complete the operation rather than entering the Suspend mode.

When the Program Suspend Status bit is ‘0’ the Program/Erase Controller is active or has completed its operation; when the bit is ‘1’ a Program/ Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command.

When a Program/Erase Resume command is issued the Program Suspend Status bit returns to ‘0’.

Block Protection Status (Bit 1). The Block Pro-

gram or Block Erase operation has tried to modify the contents of a protected block. When the Block Protection Status bit is to ‘0’ no Program or Block Erase operations have been attempted to protected blocks since the last Clear Status Register command or hardware reset; when the Block Protection Status bit is ‘1’ a Program or Block Erase operation has been attempted on a protected block.

Once it is set to ‘1’ the Block Protection Status bit can only be reset to ‘0’ by a Clear Status Register command or a hardware reset. If it is set to ‘1’ it should be reset before a new Program or Block Erase command is issued, otherwise the new command will appear to fail.

Using the A/A Mux Interface the Block Protection Status bit is always ‘0’.

Reserved (Bit 0). Bit 0 of the Status Register is reserved. Its value should be masked.

tection Status bit can be used to identify if the Pro-

Table 10. Status Register Bits

Operation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

(1)

Program active ‘0’

Program suspended ‘1

Program completed successfully ‘1’

Program failure due to V

Program failure due to Block Protection (FWH Interface only) ‘1’

Program failure due to cell failure ‘1’

Erase active ‘0’‘0’‘0’‘0’‘0’‘0’‘0’

Block Erase suspended ‘1’‘1’‘0’‘0’‘0’‘0’‘0’

Error

‘1’

‘0’‘0’‘0’‘0’‘0’

(1)

‘0’‘0’‘0’‘1’‘0’

(1)

‘0’‘0’‘0’‘0’‘0’

(1)

‘0’‘0’‘1’‘0’‘0’

(1)

‘0’‘0’‘0’‘0’‘1’

(1)

‘0’‘1’‘0’‘0’‘0’

Erase completed successfully ‘1’‘0’‘0’‘0’‘0’‘0’‘0’

Erase failure due to V

Block Erase failure due to Block Protection (FWH Interface only)

Erase failure due to failed cell(s) ‘1’‘0’‘1’‘0’‘0’‘0’‘0’

Note: 1. For Program operations during Erase Suspend Bit 6 is ‘1’, otherwise Bit 6 is ‘0’.

20/47

Error

‘1’‘0’‘0’‘0’‘1’‘0’‘0’

‘1’‘0’‘0’‘0’‘0’‘0’‘1’

FIRMWARE HUB (FWH) INTERFACE CONFIGURATION REGISTERS

When the Firmware Hub Interface is selected several additional registers can be accessed. These registers control the protection status of the Blocks, read the General Purpose Input pins and identify the memory using the Electronic Signature codes. See Table 11. for the memory map of the Configuration Registers.

Lock Registers

The Lock Registers control the protection status of the Blocks. Each Block has its own Lock Register. Three bits within each Lock Register control the protection of each block, the Write Lock Bit, the Read Lock Bit and the Lock Down Bit.

The Lock Registers can be read and written, though care should be taken when writing as, once the Lock Down Bit is set, ‘1’, further modifications to the Lock Register cannot be made until cleared, to ‘0’, by a reset or power-up.

See Table 12. for details on the bit definitions of the Lock Registers.

Write Lock. The Write Lock Bit determines whether the contents of the Block can be modified (using the Program or Block Erase Command). When the Write Lock Bit is set, ‘1’, the block is write protected; any operations that attempt to change the data in the block will fail and the Status Register will report the error. When the Write Lock Bit is reset, ‘0’, the block is not write protected through the Lock Register and may be modified unless write protected through some other means.

When V tected and cannot be modified, regardless of the state of the Write Lock Bit. If Top Block Lock, TBL is Low, V protected and cannot be modified. Similarly, if Write Protect, WP Blocks (Blocks 0 to 14) are write protected and cannot be modified.

After power-up or reset the Write Lock Bit is always set to ‘1’ (write protected).

Read Lock. The Read Lock bit determines whether the contents of the Block can be read (from Read mode). When the Read Lock Bit is set, ‘1’, the block is read protected; any operation that attempts to read the contents of the block will read 00h instead. When the Read Lock Bit is reset, ‘0’, read operations in the Block return the data programmed into the block as expected.

After power-up or reset the Read Lock Bit is always reset to ‘0’ (not read protected).

Lock Down. The Lock Down Bit provides a mechanism for protecting software data from simple hacking and malicious attack. When the Lock Down Bit is set, ‘1’, further modification to the Write Lock, Read Lock and Lock Down Bits cannot be performed. A reset or power-up is required before changes to these bits can be made. When the Lock Down Bit is reset, ‘0’, the Write Lock, Read Lock and Lock Down Bits can be changed.

is less than V

, then the Top Block (Block 15) is write

all blocks are pro-

PPLK

, is Low, VIL, then the Main

M50FW080

21/47

M50FW080

Table 11. Firmware Hub Register Configuration Map

Mnemonic Register Name

T_BLOCK_LK Top Block Lock Register (Block 15) FBF0002h 01h R/W T_MINUS01_LK Top Block [-1] Lock Register (Block 14) FBE0002h 01h R/W T_MINUS02_LK Top Block [-2] Lock Register (Block 13) FBD0002h 01h R/W T_MINUS03_LK Top Block [-3] Lock Register (Block 12) FBC0002h 01h R/W T_MINUS04_LK Top Block [-4] Lock Register (Block 11) FBB0002h 01h R/W T_MINUS05_LK Top Block [-5] Lock Register (Block 10) FBA0002h 01h R/W T_MINUS06_LK Top Block [-6] Lock Register (Block 9) FB90002h 01h R/W T_MINUS07_LK Top Block [-7] Lock Register (Block 8) FB80002h 01h R/W T_MINUS08_LK Top Block [-8] Lock Register (Block 7) FB70002h 01h R/W T_MINUS09_LK Top Block [-9] Lock Register (Block 6) FB60002h 01h R/W T_MINUS10_LK Top Block [-10] Lock Register (Block 5) FB50002h 01h R/W T_MINUS11_LK Top Block [-11] Lock Register (Block 4) FB40002h 01h R/W T_MINUS12_LK Top Block [-12] Lock Register (Block 3) FB30002h 01h R/W T_MINUS13_LK Top Block [-13] Lock Register (Block 2) FB20002h 01h R/W T_MINUS14_LK Top Block [-14] Lock Register (Block 1) FB10002h 01h R/W T_MINUS15_LK Top Block [-15] Lock Register (Block 0) FB00002h 01h R/W

FGPI_REG Firmware Hub (FWH) General Purpose Input Register FBC0100h N/A R

MANUF_REG Manufacturer Code Register FBC0000h 20h R

DEV_REG Device Code Register FBC0001h 2Dh R

Memory

Address

Default

Value

Access

22/47

M50FW080

Firmware Hub (FWH) General Purpose Input Register

The Firmware Hub (FWH) General Purpose Input Register holds the state of the Firmware Hub Interface General Purpose Input pins, FGPI0-FGPI4. When this register is read, the state of these pins is returned. This register is read-only and writing to it has no effect.

The signals on the Firmware Hub Interface General Purpose Input pins should remain constant

throughout the whole Bus Read cycle in order to guarantee that the correct data is read.

Manufacturer Code Register

Reading the Manufacturer Code Register returns the manufacturer code for the memory. The manufacturer code for STMicroelectronics is 20h. This register is read-only and writing to it has no effect.

Device Code Register

Reading the Device Code Register returns the device code for the memory, 2Dh. This register is read-only and writing to it has no effect.

Table 12. Lock Register Bit Definitions

Bit Bit Name Value Function

7-3 Reserved

‘1’ Bus Read operations in this Block always return 00h.

2 Read-Lock

1 Lock-Down

0 Write-Lock

Note: Applies to Top Block Lock Register (T_BLOCK_LK) and Top Block [-1] Lock Register (T_MINUS01_LK) to Top Block [-15] Lock Reg-

ister (T_MINUS15_LK).

Bus read operations in this Block return the Memory Array contents. (Default

‘0’

value).

Changes to the Read-Lock bit and the Write-Lock bit cannot be performed. Once a

‘1’

‘1’ is written to the Lock-Down bit it cannot be cleared to ‘0’; the bit is always reset

to ‘0’ following a Reset (using RP

Read-Lock and Write-Lock can be changed by writing new values to them. (Default

‘0’

value).

Program and Block Erase operations in this Block will set an error in the Status

‘1’

Program and Block Erase operations in this Block are executed and will modify the

‘0’

Block contents.

or INIT) or after power-up.

Table 13. General Purpose Input Register Definition

Bit Bit Name Value Function

7-5 Reserved

Input Pin FGPI4 is at V

4FGPI4

3FGPI3

2FGPI2

1FGPI1

0FGPI0

Note: Applies to the General Purpose Input Register (FGPI_REG).

‘1’

Input Pin FGPI4 is at V

‘0’

Input Pin FGPI3 is at V

‘1’

Input Pin FGPI3 is at V

‘0’

Input Pin FGPI2 is at V

‘1’

Input Pin FGPI2 is at V

‘0’

Input Pin FGPI1 is at V

‘1’

Input Pin FGPI1 is at V

‘0’

Input Pin FGPI0 is at V

‘1’

Input Pin FGPI0 is at V

‘0’

23/47

M50FW080

PROGRAM AND ERASE TIMES

The Program and Erase times are shown in Table

14..

Table 14. Program and Erase Times

Parameter Interface Test Condition Min

Byte Program 10 200

Quadruple Byte Program A/A Mux

Chip Erase A/A Mux

A/A Mux

Block Program

Block Erase

Program/Erase Suspend to Program pause

Program/Erase Suspend to Block Erase pause

Note: 1. TA = 25°C, VCC = 3.3V

2. This time is obtained executing the Quadruple Byte Program Command.

3. Sampled only, not 100% tested.

(3)

= 12V ± 5%

= V

(1)

Typ

Max Unit

10 200

9sec

(2)

0.1

0.4 5 sec

0.75 8 sec

110sec

µs µs

5sec

5 µs

30 µs

24/47

MAXIMUM RATING

Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im-

Table 15. Absolute Maximum Ratings

Symbol Parameter Min. Max. Unit

STG

LEAD

IO Input or Output range

Storage Temperature –65 150 °C

Lead Temperature during Soldering

plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.

See note

–0.50

+ 0.6

M50FW080

°C

ESD

Note: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK® 7191395 specification, and

the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU

2. Minimum voltage may undershoot to –2V for less than 20ns during transitions. Maximum voltage may overshoot to V less than 20ns during transitions.

3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500

Supply Voltage –0.50 4 V

Program Voltage –0.6 13 V

Electrostatic Discharge Voltage (Human Body model)

Ω, R2=500 Ω)

–2000 2000 V

+ 2V for

25/47

M50FW080

DC AND AC PARAMETERS

This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement

Table 16. Operating Conditions

Symbol Parameter Min. Max. Unit

Conditions summarized in Table 16., Table 17. and Table 18.. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters.

Supply Voltage 3.0 3.6 V

Ambient Operating Temperature (Device Grade 5) –20 85 °C

Ambient Operating Temperature (Device Grade 1) 0 70 °C

Table 17. FWH Interface AC Measurement Conditions

Parameter Value Unit

Load Capacitance (C

Input Rise and Fall Times

Input Pulse Voltages

Input and Output Timing Ref. Voltages

)

0.2 V

10 pF

≤ 1.4 ns

and 0.6 V

0.4 V

Table 18. A/A Mux Interface AC Measurement Conditions

Parameter Value Unit

Load Capacitance (C

Input Rise and Fall Times

Input Pulse Voltages 0 to 3 V

Input and Output Timing Ref. Voltages 1.5 V

)

30 pF

≤ 10 ns

26/47

Figure 9. FWH Interface AC Testing Input Output Waveforms

0.6 V

0.2 V

Input and Output AC Testing Waveform

0.4 V

M50FW080

IO < I

Output AC Tri-state Testing Waveform

IO > I

IO < I

AI03404

Figure 10. A/A Mux Interface AC Testing Input Output Waveform

1.5V

AI01417

Table 19. Impedance

Symbol Parameter Test Condition Min Max Unit

(1)

CLK

(2)

Note: 1. Sampled only, not 100% tested.

2. See PCI Specification.

3. T

= 25°C, f = 1MHz.

Input Capacitance

Clock Capacitance

Recommended Pin Inductance

= 0V

13 pF

312pF

20 nH

27/47

M50FW080

Table 20. DC Characteristics

Symbol Parameter Interface Test Condition Min Max Unit

Input High Voltage

Input Low Voltage

A/A Mux

FWH –0.5

A/A Mux -0.5 0.8 V

FWH

0.5 V

0.7 V

CCVCC

+ 0.5

+ 0.3

0.3 V

PPLK

(INIT)

(2)

LI2

PP1

PPH

LKO

CC1

Input High Voltage FWH 1.35

INIT

Input Low Voltage FWH –0.5

INIT

Input Leakage Current

IC, IDx Input Leakage Current

IC, IDx Input Pull Low Resistor

Output High Voltage

Output Low Voltage

Output Leakage Current

VPP Voltage

VPP Voltage (Fast Program/Fast Erase)

(1)

VPP Lockout Voltage

(1)

VCC Lockout Voltage

Supply Current (Standby) FWH

IC, ID0, ID1, ID2, ID3 = V

FWH I

A/A Mux

FWH

A/A Mux

FWH4 = 0.9 V

All other inputs 0.9 VCC to 0.1 V

VCC = 3.6V, f(CLK) = 33MHz

≤ V

20 100 kΩ

= –500µA

= –100µA

= 1.5mA 0.1 V

= 1.8mA

≤ V

OUT

0.9 V

– 0.4

33.6V

11.4 12.6 V

1.5 V

1.8 2.3 V

, VPP = V

+ 0.5

0.2 V

±10

200

0.45 V

±10

100

µA

, VPP = V

CC2

Supply Current (Standby) FWH

FWH4 = 0.1 V

All other inputs 0.9 VCC to 0.1 V

VCC = 3.6V, f(CLK) = 33MHz

= VCC max, VPP = V

CC3

(Any internal operation

FWH

active)

Supply Current

CC4

CC5

PP1

Note: 1. Sampled only, not 100% tested.

Supply Current (Read) A/A Mux

Supply Current

(1)

(Program/Erase)

A/A Mux Program/Erase Controller Active 20 mA

VPP Supply Current (Read/Standby)

VPP Supply Current

(1)

(Program/Erase active)

2. Input leakage currents include High-Z output leakage for all bi-directional buffers with tri-state outputs.

f(CLK) = 33MHz

OUT

= VIH, f = 6MHz

= 0mA

> V

= V

= 12V ± 5%

28/47

10 mA

60 mA

20 mA

400 µA

40 mA

15 mA

M50FW080

Figure 11. FWH Interface Clock Waveform

tCYC

tHIGH tLOW

0.6 V

0.5 V

0.4 V

0.3 V

0.2 V

Table 21. FWH Interface Clock Characteristics

Symbol Parameter Test Condition Value Unit

CYC

HIGH

LOW

CLK Cycle Time

CLK High Time Min 11 ns

CLK Low Time Min 11 ns

CLK Slew Rate peak to peak

Note: 1. Devices on the PCI Bus must work with any clock frequency between DC and 33MHz. Below 16MHz devices may be guaranteed

by design rather than tested. Refer to PCI Specification.

(1)

Min 30 ns

Min 1 V/ns

Max 4 V/ns

0.4 VCC, (minimum)

p-to-p

AI03403

29/47

M50FW080

Figure 12. FWH Interface AC Signal Timing Waveforms

CLK

tCHQV

FWH0-FWH3

VALID OUTPUT DATA FLOAT OUTPUT DATA VALID INPUT DATA

tCHQZ

tCHQX

tDVCH

tCHDX

VALID

AI03405

Table 22. FWH Interface AC Signal Timing Characteristics

Symbol

CHQV

(1)

CHQX

CHQZ

AV CH

DVC H

CHAX

CHDX

Note: 1. The timing measurements for Active/Float transitions are defined when the current through the pin equals the leakage current spec-

ification.

2. Applies to all inputs except CLK.

PCI

Symbol

val

off

Parameter Test Condition Value Unit

CLK to Data Out

CLK to Active (Float to Active Delay)

CLK to Inactive (Active to Float Delay)

Input Set-up Time

Input Hold Time

(2)

Min 2 ns

Max 11 ns

Min 2 ns

Max 28 ns

Min 7 ns

Min 0 ns

30/47

Figure 13. Reset AC Waveforms

RP, INIT

tPLPH

M50FW080

tPHWL, tPHGL, tPHFL

W, G, FWH4

tPLRH

AI03420

Table 23. Reset AC Characteristics

Symbol Parameter Test Condition Value Unit

PLPH

PLRH

PHFL

PHWL

PHGL

Note: 1. See Chapter 4 of the PCI Specification.

RP or INIT Reset Pulse Width Min 100 ns

Program/Erase Inactive Max 100 ns

RP or INIT Low to Reset

Program/Erase Active Max 30

or INIT Slew Rate

(1)

Rising edge only Min 50 mV/ns

RP or INIT High to FWH4 Low FWH Interface only Min 30 µs

RP High to Write Enable or Output Enable Low

A/A Mux Interface only Min 50

µs

31/47

M50FW080

Figure 14. A/A Mux Interface Read AC Waveforms

tAVAV

A0-A10

DQ0-DQ7

ROW ADDR VALID NEXT ADDR VALID

tAVCL tAVCH

tCLAX tCHAX

tPHAV

COLUMN ADDR VALID

tCHQV

tGLQV

tGLQX

tGHQZ

tGHQX

VALID

AI03406

Table 24. A/A Mux Interface Read AC Characteristics

Symbol Parameter Test Condition Value Unit

AVAV

AVCL

CLAX

AV CH

CHAX

CHQV

GLQV

PHAV

GLQX

GHQZ

GHQX

Note: 1. G may be delayed up to t

32/47

Read Cycle Time Min 250 ns

Row Address Valid to RC Low Min 50 ns

RC Low to Row Address Transition Min 50 ns

Column Address Valid to RC high Min 50 ns

RC High to Column Address Transition Min 50 ns

(1)

RC High to Output Valid Max 150 ns

(1)

Output Enable Low to Output Valid Max 50 ns

RP High to Row Address Valid Min 1 µs

Output Enable Low to Output Transition Min 0 ns

Output Enable High to Output Hi-Z Max 50 ns

Output Hold from Output Enable High Min 0 ns

– t

CHQV

after the rising edge of RC without impact on t

GLQV

CHQV

Figure 15. A/A Mux Interface Write AC Waveforms

M50FW080

A0-A10

DQ0-DQ7

Write erase or program setup

tAVCL

tWLWH

tCLAX

tWHWL

Write erase confirm or valid address and data

R2 C2

tAVCH

tCHAX

tVPHWH tWHGL

IN1

tWHRL

Automated erase

or program delay

tCHWH

IN2

Read Status

tQVVPL

tWHDXtDVWH

VALID SRD

Ready to write

another command

AI04194

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M50FW080

Table 25. A/A Mux Interface Write AC Characteristics

Symbol Parameter Test Condition Value Unit

WLWH

DVW H

WHDX

AVCL

CLAX

AV CH

CHAX

WHWL

CHWH

VPHWH

WHGL

WHRL

QVVPL

Note: 1. Sampled only, not 100% tested.

2. Applicable if V

Write Enable Low to Write Enable High Min 100 ns

Data Valid to Write Enable High Min 50 ns

Write Enable High to Data Transition Min 5 ns

Row Address Valid to RC Low Min 50 ns

RC Low to Row Address Transition Min 50 ns

Column Address Valid to RC High Min 50 ns

RC High to Column Address Transition Min 50 ns

Write Enable High to Write Enable Low Min 100 ns

RC High to Write Enable High Min 50 ns

(1)

VPP High to Write Enable High

Min 100 ns

Write Enable High to Output Enable Low Min 30 ns

Write Enable High to RB Low Min 0 ns

(1,2)

Output Valid, RB High to VPP Low

is seen as a logic input (VPP < 3.6V).

Min 0 ns

34/47

PACKAGE MECHANICAL

Figure 16. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Outline

M50FW080

D2 D2

Note: Drawing is not to scale.

1 N

E1 E

0.51 (.020)

1.14 (.045)

A1 A2

PLCC-A

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M50FW080

Table 26. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Mechanical Data

Symbol

Typ Min Max Typ Min Max

A 3.18 3.56 0.125 0.140

A1 1.53 2.41 0.060 0.095

A2 0.38 – 0.015 –

B 0.33 0.53 0.013 0.021

B1 0.66 0.81 0.026 0.032

CP 0.10 0.004

D 12.32 12.57 0.485 0.495

D1 11.35 11.51 0.447 0.453

D2 4.78 5.66 0.188 0.223

D3 7.62 ––0.300 ––

E 14.86 15.11 0.585 0.595

E1 13.89 14.05 0.547 0.553

E2 6.05 6.93 0.238 0.273

millimeters inches

E3 10.16 ––0.400 ––

e1.27 ––0.050 ––

F 0.00 0.13 0.000 0.005

R0.89 ––0.035 ––

N32 32

36/47

Figure 17. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Outline

M50FW080

N/2

DIE

TSOP-a

Note: Drawing is not to scale.

LA1 α

Table 27. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Mechanical Data

Symbol

Typ Min Max Typ Min Max

A 1.200 0.0472

A1 0.050 0.150 0.0020 0.0059

millimeters inches

A2 0.950 1.050 0.0374 0.0413

α 05 05

B 0.170 0.270 0.0067 0.0106

C 0.100 0.210 0.0039 0.0083

CP 0.100 0.0039

D 13.800 14.200 0.5433 0.5591

D1 12.300 12.500 0.4843 0.4921

e0.500 ––0.0197 ––

E 7.900 8.100 0.3110 0.3189

L 0.500 0.700 0.0197 0.0276

N32 32

37/47

M50FW080

Figure 18. TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline

N/2

DIE

TSOP-a

Note: Drawing is not to scale.

LA1 α

Table 28. TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data

Symbol

Typ Min Max Typ Min Max

A1.200 0

A1 0.050 0.150 0 0

millimeters inches

A2 0.950 1.050 0 0

B 0.170 0.270 0 0

C 0.100 0.210 0 0

CP 0.100 0

D 19.800 20.200 1 1

D1 18.300 18.500 1 1

e0.500 ––0 ––

E 9.900 10.100 0 0

L 0.500 0.700 0 0

α 05 05

N40 40

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PART NUMBERING

Table 29. Ordering Information Scheme

Example: M50FW080 N 5 T G

Device Type

M50 = Flash Memory for PC BIOS

Architecture

F = Firmware Hub Interface

Operating Voltage

W = V

Device Function

080 = 8 Mbit (1Mbx8), Uniform Blocks

Package

K = PLCC32 NB = TSOP32: 8 x 14mm N = TSOP40: 10 x 20mm

= 3.0 to 3.6V

M50FW080

Device Grade

5 = Temperature range –20 to 85 °C. Device tested with standard test flow

1 = Temperature range 0 to 70 °C. Device tested with standard test flow

Option

blank = Standard Packing T = Tape and Reel Packing

Plating Technology

blank = Standard SnPb plating G = Lead-Free, RoHS compliant, Sb

-free and TBBA-free

2O3

Devices are shipped from the factory with the memory content bits erased to ’1’.

For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.

39/47

M50FW080

APPENDIX A. FLOWCHARTS AND PSEUDO CODES

Figure 19. Program Flowchart and Pseudo Code

Start

FWH/LPC

Interface

Only

Write 40h or 10h

Write Address

and Data

Read Status

SR7 = 1

YES

SR3 = 0

YES

SR4 = 0

YES

SR1 = 0

YES

End

Suspend

Program to Protected

YES

VPP Invalid

Error (1, 2)

Program

Error (1, 2)

Block Error (1, 2)

Program command:

– Write 40h or 10h – Write Address and Data

(memory enters read status state after the Program command)

do:

– Read Status Register – If SR7=0 and a Program/Erase Suspend

command has been executed – SR7 is set to 1 – Enter suspend program loop

Suspend

Loop

If SR3 = 1, – Enter the "VPP invalid" error handler

If SR4 = 1, – Enter the "Program error" error handler

If SR1 = 1, – Enter the "Program to protected block" error handler

AI08425B

Note: 1. A Status check of SR1 (Protected Block), SR3 (VPP invalid) and SR4 (Program Error) can be made after each Program operation

by following the correct command sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

40/47

M50FW080

Figure 20. Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only)

Start

Write 30h

Write Address 1

Write Address 2

Write Address 3

Write Address 4

Read Status

& Data 1

& Data 2

& Data 3

& Data 4

SR7 = 1

SR3 = 0

(3)

YES

Suspend

YES

Suspend

VPP Invalid

Error (1, 2)

Loop

Quadruple Byte Program command:

– write 30h – write Address 1 & Data 1 – write Address 2 & Data 2 – write Address 3 & Data 3 – write Address 4 & Data 4

(memory enters read status state after the Quadruple Byte Program command)

do:

– Read Status Register – If SR7=0 and a Program/Erase Suspend

command has been executed – SR7 is set to 1 – Enter suspend program loop

If SR3 = 1, VPP invalid error: – error handler

(3) (3) (3) (3)

SR4 = 0

End

Note: 1. A Status check of SR3 (VPP invalid) and SR4 (Program Error) can be made after each Program operation by following the correct

command sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

3. Address1, Address 2, Address 3 and Address 4 must be consecutive addresses differing only for address bits A0 and A1.

YES

Program

Error (1, 2)

If SR4 = 1, Program error: – error handler

AI08437B

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M50FW080

Figure 21. Program Suspend and Resume Flowchart and Pseudo Code

Start

Write B0h

Program/Erase Suspend command:

Write 70h

Read Status

– write B0h – write 70h

do: – read Status Register

SR7 = 1

YES

SR2 = 1

YES

Write a read

Command

Read data from

another address

Write D0h

Program Continues

Program Complete

Write FFh

Read Data

while SR7 = 0

If SR2 = 0 Program completed

Program/Erase Resume command:

– write D0h to resume the program – if the Program operation completed

then this is not necessary. The device returns to Read as normal (as if the Program/Erase suspend was not issued).

AI08426B

Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase operations.

2. Any address within the bank can equally be used.

42/47

Figure 22. Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only)

Start

M50FW080

Write 80h

Write 10h

Read Status

SR7 = 1

YES

SR3 = 0

YES

SR4, SR5 = 0

YES

SR5 = 0

VPP Invalid

Error (1)

Command

Sequence Error (1)

Erase Error (1)

Chip Erase command:

– write 80h – write 10h

(memory enters read Status Register after the Chip Erase command)

do: – read Status Register

while SR7 = 0

If SR3 = 1, VPP invalid error: – error handler

If SR4, SR5 = 1, Command sequence error: – error handler

If SR5 = 1, Erase error: – error handler

YES

End

Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

AI08428B

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M50FW080

Figure 23. Block Erase Flowchart and Pseudo Code

Start

Write 20h/32h

Write Block

Address and D0h

Read Status

SR7 = 1

YES

SR3 = 0

YES

SR4, SR5 = 0

YES

SR5 = 0

Suspend

VPP Invalid

Sequence Error (1)

Erase Error (1)

YES

Suspend

Error (1)

Command

Block Erase command:

– Write 20h/32h – Write block Address and D0h

(memory enters read Status Register after the Block Erase command)

do:

– Read Status Register – If SR7=0 and a Program/Erase Suspend

command has been executed – SR7 is set to 1 – Enter suspend program loop

Loop

If SR3 = 1, – Enter the "VPP invalid" error handler

If SR4, SR5 = 1, – Enter the "Command sequence"error handler

If SR5 = 1, – Enter the "Erase Error" error handler

YES

FWH/LPC

Interface

Only

Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

SR1 = 0

End

YES

Erase to Protected

Block Error (1)

If SR1 = 1, – Enter the "Erase to protected block" error handler

44/47

AI08424B

Figure 24. Erase Suspend and Resume Flowchart and Pseudo Code

Start

Write B0h

Program/Erase Suspend command:

Write 70h

– write B0h – write 70h

M50FW080

Read Status

SR7 = 1

YES

SR6 = 1

YES

Read data from

another block/sector

Program

Write D0h

Erase Continues

Erase Complete

Write FFh

Read Data

do: – read Status Register

while SR7 = 0

If SR6 = 0, Erase completed

Program/Erase Resume command:

– write D0h to resume erase – if the Erase operation completed

then this is not necessary. The device returns to Read as normal (as if the Program/Erase suspend was not issued).

AI08429B

45/47

M50FW080

REVISION HISTORY

Table 30. Document Revision History

Date Version Revision Details

April 2001 -01 First Issue

18-May-2001 -02 Document type: from Product Preview to Preliminary Data

22-Jun-2001 -03 PLCC32 package added

6-Jul-2001 -04 Note 2 changed (Table 15., Absolute Maximum Ratings)

30-Jan-2002 -05 Document promoted from Preliminary Data to Full Data Sheet

01-Mar-2002 -06 RFU pins must be left disconnected

12-Mar-2002 -07 Specification of PLCC32 package mechanical data revised

19-May-2004 8.0

19-Aug-2004 9.0 Pins 2 and 5 of the TSOP32 Connections illustration corrected

TSOP32 package added. Part numbering information updated. Flow-chart illustrations, in Appendix, updated. Document reformatted

46/47

M50FW080

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners

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47/47

ST M50FW080 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual