ST M48Z02, M48Z12 User Manual

5 V, 16 Kbit (2 Kb x 8) ZEROPOWER® SRAM

Features

■ Integrated, ultra low power SRAM and power-

fail control circuit

■ Unlimited WRITE cycles

■ READ cycle time equals WRITE cycle time

■ Automatic power-fail chip deselect and WRITE

protection

■ WRITE protect voltages

(V

= power-fail deselect voltage):

PFD

–M48Z02: V

4.5 V ≤ V

–M48Z12: V

4.2 V ≤ V

■ Self-contained battery in the CAPHAT™ DIP

package

■ Pin and function compatible with JEDEC

standard 2 K x 8 SRAMs

■ RoHS compliant

– Lead-free second level interconnect

= 4.75 to 5.5 V;

CC

≤ 4.75 V

PFD

= 4.5 to 5.5 V;

CC

≤ 4.5 V

PFD

M48Z02
M48Z12

24

1

PCDIP24

Battery CAPHAT™

June 2011 Doc ID 2420 Rev 9 1/22

www.st.com

1

Contents M48Z02, M48Z12

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.4 V

noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 12

CC

3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7 Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2/22 Doc ID 2420 Rev 9

M48Z02, M48Z12 List of tables

List of tables

Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 2. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3. READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 4. WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 6. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 7. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 8. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 9. Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 10. Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 11. PCDIP24 – 24-pin plastic DIP, battery CAPHAT™, package mechanical data . . . . . . . . . 17

Table 12. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 13. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Doc ID 2420 Rev 9 3/22

List of figures M48Z02, M48Z12

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 5. WRITE enable controlled, WRITE AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 6. Chip enable controlled, WRITE AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 7. Checking the BOK flag status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 8. Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 9. AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 10. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 11. PCDIP24 – 24-pin plastic DIP, battery CAPHAT™, package outline . . . . . . . . . . . . . . . . . 17

Figure 12. Shipping tube dimensions for PCDIP24 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 13. Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4/22 Doc ID 2420 Rev 9

M48Z02, M48Z12 Description

1 Description

The M48Z02/12 ZEROPOWER® RAM is a 2 K x 8 non-volatile static RAM which is pin and
function compatible with the DS1220.

A special 24-pin, 600 mil DIP CAPHAT™ package houses the M48Z02/12 silicon with a
long-life lithium button cell to form a highly integrated battery-backed memory solution.

The M48Z02/12 button cell has sufficient capacity and storage life to maintain data
functionality for an accumulated time period of at least 10 years in the absence of power
over commercial operating temperature range.

The M48Z02/12 is a non-volatile pin and function equivalent to any JEDEC standard 2 K x 8
SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the
non-volatility of PROMs without any requirement for special WRITE timing or limitations on
the number of WRITEs that can be performed.

Figure 1. Logic diagram

V

CC

11

A0-A10

W

E

G

Table 1. Signal names

A0-A10 Address inputs

DQ0-DQ7 Data inputs / outputs

E Chip enable

G Output enable

W WRITE enable

M48Z02
M48Z12

V

SS

8

DQ0-DQ7

AI01186

V

CC

V

SS

Supply voltage

Ground

Doc ID 2420 Rev 9 5/22

Description M48Z02, M48Z12

Figure 2. DIP connections

Figure 3. Block diagram

LITHIUM

CELL

A7
A6
A5
A4
A3
A2
A1
A0

DQ0

DQ2

SS

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

1
2

3

4
5
6
7

8

9
10
11
12

M48Z02
M48Z12

POWER

V

PFD

24
23
22
21
20
19
18
17
16
15
14
13

V

CC

A8
A9
W
G
A10
E
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V

2K x 8

SRAM ARRAY

AI01187

A0-A10

DQ0-DQ7

E

W

V

CC

6/22 Doc ID 2420 Rev 9

G

V

SS

AI01255

M48Z02, M48Z12 Operation modes

2 Operation modes

The M48Z02/12 also has its own power-fail detect circuit. The control circuitry constantly
monitors the single 5 V supply for an out of tolerance condition. When V
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low V

. As VCC falls below

CC

approximately 3 V, the control circuitry connects the battery which maintains data operation
until valid power returns.

Table 2. Operating modes

Mode V

CC

E G W

DQ0-

DQ7

is out of

CC

Power

Deselect

WRITE V

READ V

READ V

Deselect VSO to V

Deselect ≤ V

1. See Table 10 on page 16 for details.

Note: X = V

or VIL; VSO = battery backup switchover voltage.

IH

4.75 to 5.5 V

2.1 READ mode

The M48Z02/12 is in the READ mode whenever W (WRITE enable) is high and E (chip
enable) is low. The device architecture allows ripple-through access of data from eight of
16,384 locations in the static storage array. Thus, the unique address specified by the 11
Address Inputs defines which one of the 2,048 bytes of data is to be accessed. Valid data
will be available at the data I/O pins within address access time (t
address input signal is stable, providing that the E
the E

and G access times are not met, valid data will be available after the latter of the chip

enable access time (t

The state of the eight three-state data I/O signals is controlled by E
activated before t
the address inputs are changed while E
for output data hold time (t

X X High Z Standby

XVILD

V

IL

V

IH

V

IH

V

IH

IN

D

OUT

High Z Active

AVQ V

or

4.5 to 5.5 V

(min)

PFD

(1)

SO

(1)

V

IH

IL

IL

IL

X X X High Z CMOS standby

X X X High Z Battery backup mode

and G access times are also satisfied. If

) or output enable access time (t

ELQV

GLQV

).

and G. If the outputs are

, the data lines will be driven to an indeterminate state until t

AVQ V

and G remain active, output data will remain valid

) but will go indeterminate until the next address access.

AXQX

Active

Active

) after the last

AVQ V

. If

Doc ID 2420 Rev 9 7/22