ST M48T58, M48T58Y User Manual
M48T58Y-70MH1
M48T58
M48T58Y
5.0V, 64 Kbit (8 Kb x 8) TIMEKEEPER®SRAM
FEATURES SUMMARY
■INTEGRATED, ULTRA LOW POWER SRAM, REAL TIME CLOCK, POWER-FAIL CONTROL CIRCUIT and BATTERY
■BYTEWIDE™ RAM-LIKE CLOCK ACCESS
■BCD CODED YEAR, MONTH, DAY, DATE, HOURS, MINUTES, and SECONDS
■FREQUENCY TEST OUTPUT FOR REAL TIME CLOCK
■AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION
■WRITE PROTECT VOLTAGES (VPFD = Power-fail Deselect Voltage):
–M48T58: VCC = 4.75 to 5.5V 4.5V ≤ VPFD ≤ 4.75V
–M48T58Y: VCC = 4.5 to 5.5V 4.2V ≤ VPFD ≤ 4.5V
■SELF-CONTAINED BATTERY and CRYSTAL IN THE CAPHAT™ DIP PACKAGE
■PACKAGING INCLUDES a 28-LEAD SOIC and SNAPHAT®TOP (to be Ordered Separately)
■SOIC PACKAGE PROVIDES DIRECT CONNECTION FOR A SNAPHAT HOUSING CONTAINING THE BATTERY and CRYSTAL
■PIN and FUNCTION COMPATIBLE WITH JEDEC STANDARD 8 Kb x 8 SRAMs
Figure 1. 28-pin PCDIP, CAPHAT™ Package
28
1
PCDIP28 (PC)
Battery/Crystal
CAPHAT
Figure 2. 28-pin SOIC Package
SNAPHAT (SH)
Battery/Crystal
28 
1
SOH28 (MH)
May 2002 |
1/27 |
M48T58, M48T58Y
TABLE OF CONTENTS
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Logic Diagram (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Signal Names (Table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
DIP Connections (Figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SOIC Connections (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute Maximum Ratings (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Operating and AC Measurement Conditions (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 AC Measurement Load Circuit (Figure 7.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Capacitance (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 DC Characteristics (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Operating Modes (Table 6.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 READ Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 READ Mode AC Waveforms (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 READ Mode AC Characteristics (Table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 WRITE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 WRITE Enable Controlled, WRITE AC Waveform (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Chip Enable Controlled, WRITE AC Waveforms (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 WRITE Mode AC Characteristics (Table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power Down/Up Mode AC Waveforms (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power Down/Up AC Characteristics (Table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power Down/Up Trip Points DC Characteristics (Table 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/27
M48T58, M48T58Y
CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Reading the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Register Map (Table 11.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Stopping and Starting the Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Calibrating the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Battery Low Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Century Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Crystal Accuracy Across Temperature (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Clock Calibration (Figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
VCC Noise And Negative Going Transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Supply Voltage Protection (Figure 14.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SNAPHAT Battery Table (Table 13.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3/27
M48T58, M48T58Y
SUMMARY DESCRIPTION
The M48T58/Y TIMEKEEPER®RAM is a 8Kb x 8 non-volatile static RAM and real time clock. The monolithic chip is available in two special packages to provide a highly integrated battery backed-up memory and real time clock solution.
The M48T58/Y is a non-volatile pin and function equivalent to any JEDEC standard 8Kb x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed.
The 28-pin, 600mil DIP CAPHAT™ houses the M48T58/Y silicon with a quartz crystal and a long life lithium button cell in a single package.
The 28-pin, 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT® housing containing the battery and crystal. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surfacemounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SOIC and battery/crystal packages are shipped separately in plastic antistatic tubes or in Tape & Reel form.
For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT) part number is “M4T28BR12SH” (see Table 13, page 21).
Figure 3. Logic Diagram
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VCC |
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13 |
8 |
A0-A12 |
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DQ0-DQ7 |
W |
M48T58 |
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E1 |
M48T58Y |
FT |
E2 |
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G |
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VSS
AI01374B
4/27
Table 1. Signal Names
A0-A12 |
Address Inputs |
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DQ0-DQ7 |
Data Inputs / Outputs |
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FT |
Frequency Test Output (Open |
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Drain) |
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Chip Enable 1 |
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E1 |
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E2 |
Chip Enable 2 |
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Output Enable |
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G |
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WRITE Enable |
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VCC |
Supply Voltage |
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VSS |
Ground |
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M48T58, M48T58Y
Figure 4. DIP Connections
FT |
1 |
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28 |
VCC |
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A12 |
2 |
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27 |
W |
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A7 |
3 |
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26 |
E2 |
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A6 |
4 |
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25 |
A8 |
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A5 |
5 |
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24 |
A9 |
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A4 |
6 |
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23 |
A11 |
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A3 |
7 |
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22 |
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M48T58 |
G |
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A2 |
8 |
M48T58Y |
21 |
A10 |
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A1 |
9 |
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20 |
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E1 |
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A0 |
10 |
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19 |
DQ7 |
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DQ0 |
11 |
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18 |
DQ6 |
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DQ1 |
12 |
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17 |
DQ5 |
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DQ2 |
13 |
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16 |
DQ4 |
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VSS |
14 |
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15 |
DQ3 |
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AI01375B |
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Figure 5. SOIC Connections
FT |
1 |
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28 |
VCC |
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A12 |
2 |
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27 |
W |
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A7 |
3 |
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26 |
E2 |
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A6 |
4 |
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25 |
A8 |
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A5 |
5 |
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24 |
A9 |
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A4 |
6 |
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23 |
A11 |
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A3 |
7 |
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22 |
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M48T58Y |
G |
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A2 |
8 |
21 |
A10 |
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A1 |
9 |
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20 |
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E1 |
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A0 |
10 |
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19 |
DQ7 |
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DQ0 |
11 |
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18 |
DQ6 |
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DQ1 |
12 |
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17 |
DQ5 |
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DQ2 |
13 |
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16 |
DQ4 |
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VSS |
14 |
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15 |
DQ3 |
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AI01376B |
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Figure 6. Block Diagram
FT |
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OSCILLATOR AND |
8 x 8 BiPORT |
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CLOCK CHAIN |
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SRAM ARRAY |
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32,768 Hz |
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CRYSTAL |
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A0-A12 |
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POWER |
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8184 x 8 |
DQ0-DQ7 |
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LITHIUM |
SRAM ARRAY |
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CELL |
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E1 |
VOLTAGE SENSE |
VPFD |
E2 |
AND |
W |
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SWITCHING |
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CIRCUITRY |
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G |
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VCC |
VSS |
AI01377C |
5/27
M48T58, M48T58Y
MAXIMUM RATING
Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is
Table 2. Absolute Maximum Ratings
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Symbol |
Parameter |
Value |
Unit |
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TA |
Ambient Operating Temperature |
0 to 70 |
°C |
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TSTG |
Storage Temperature (VCC Off, Oscillator Off) |
–40 to 85 |
°C |
TSLD(1,2) |
Lead Solder Temperature for 10 seconds |
260 |
°C |
VIO |
Input or Output Voltages |
–0.3 to 7 |
V |
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VCC |
Supply Voltage |
–0.3 to 7 |
V |
IO |
Output Current |
20 |
mA |
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PD |
Power Dissipation |
1 |
W |
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Note: 1. For DIP package: Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
2.For SO package: Reflow at peak temperature of 215°C to 225°C for < 60 seconds (total thermal budget not to exceed 180°C for between 90 to 120 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
6/27
M48T58, M48T58Y
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
Table 3. Operating and AC Measurement Conditions
Parameter |
M48T58 |
M48T58Y |
Unit |
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Supply Voltage (VCC) |
4.75 to 5.5 |
4.5 to 5.5 |
V |
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Ambient Operating Temperature (TA) |
0 to 70 |
0 to 70 |
°C |
Load Capacitance (CL) |
100 |
100 |
pF |
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Input Rise and Fall Times |
≤ 5 |
≤ 5 |
ns |
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Input Pulse Voltages |
0 to 3 |
0 to 3 |
V |
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Input and Output Timing Ref. Voltages |
1.5 |
1.5 |
V |
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Note: Output Hi-Z is defined as the point where data is no longer driven.
Figure 7. AC Measurement Load Circuit
5V
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1.9kΩ |
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DEVICE |
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UNDER |
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OUT |
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TEST |
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1kΩ |
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CL |
= 100pF or 5pF |
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CL includes JIG capacitance
AI01030
Table 4. Capacitance
Symbol |
Parameter(1,2) |
Min |
Max |
Unit |
CIN |
Input Capacitance |
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10 |
pF |
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COUT(3) |
Output Capacitance |
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10 |
pF |
Note: 1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested.
2.At 25°C, f = 1MHz.
3.Outputs deselected.
7/27
M48T58, M48T58Y
Table 5. DC Characteristics
Symbol |
Parameter |
Test Condition(1) |
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M48T58 |
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M48T58Y |
Unit |
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Min |
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Max |
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Min |
Max |
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ILI |
Input Leakage Current |
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0V ≤ VIN ≤ VCC |
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±1 |
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±1 |
µA |
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ILO(2) |
Output Leakage Current |
0V ≤ VOUT ≤ VCC |
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±1 |
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±1 |
µA |
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ICC |
Supply Current |
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Outputs open |
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50 |
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50 |
mA |
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ICC1 |
Supply Current (Standby) |
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E1 = VIH |
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3 |
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3 |
mA |
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TTL |
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E2 = VIO |
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= VCC – 0.2V |
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ICC2 |
Supply Current (Standby) |
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E1 |
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3 |
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3 |
mA |
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CMOS |
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E2 = VSS + 0.2V |
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VIL(3) |
Input Low Voltage |
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–0.3 |
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0.8 |
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–0.3 |
0.8 |
V |
VIH |
Input High Voltage |
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2.2 |
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VCC + 0.3 |
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2.2 |
VCC + 0.3 |
V |
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VOL |
Output Low Voltage |
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IOL = 2.1mA |
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0.4 |
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0.4 |
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Output Low Voltage (FT)(4) |
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IOL = 10mA |
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0.4 |
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0.4 |
V |
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VOH |
Output High Voltage |
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IOH = –1mA |
2.4 |
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2.4 |
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V |
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Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; V CC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
2.Outputs deselected.
3.Negative spikes of –1V allowed for up to 10ns once per Cycle.
4.The FT pin is Open Drain.
8/27
M48T58, M48T58Y
OPERATION MODES
As Figure 6, page 5 shows, the static memory array and the quartz controlled clock oscillator of the M48T58/Y are integrated on one silicon chip. The two circuits are interconnected at the upper eight memory locations to provide user accessible BYTEWIDE™ clock information in the bytes with addresses 1FF8h-1FFFh. The clock locations contain the century, year, month, date, day, hour, minute, and second in 24 hour BCD format (except for the century). Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are made automatically. Byte 1FF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting.
The eight clock bytes are not the actual clock counters themselves; they are memory locations
Table 6. Operating Modes
consisting of BiPORT™ READ/write memory cells. The M48T58/Y includes a clock control circuit which updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array.
The M48T58/Y also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single 5V supply for an out-of-tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below the Battery Back-up Switchover Voltage (VSO), the control circuitry connects the battery which maintains data and clock operation until valid power returns.
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VCC |
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Mode |
E1 |
E2 |
|
G |
|
W |
DQ0-DQ7 |
Power |
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Deselect |
|
VIH |
X |
|
X |
|
X |
High Z |
Standby |
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Deselect |
4.75 to 5.5V |
|
X |
VIL |
|
X |
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X |
High Z |
Standby |
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WRITE |
VIL |
VIH |
|
X |
VIL |
DIN |
Active |
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or |
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4.5 to 5.5V |
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READ |
VIL |
VIH |
VIL |
VIH |
DOUT |
Active |
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READ |
|
VIL |
VIH |
VIH |
VIH |
High Z |
Active |
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Deselect |
VSO to VPFD (min)(1) |
|
X |
X |
|
X |
|
X |
High Z |
CMOS Standby |
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Deselect |
≤ VSO(1) |
|
X |
X |
|
X |
|
X |
High Z |
Battery Back-up Mode |
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Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. 1. See Table 10, page 16 for details.
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