ST M48T35AV User Manual

M48T35AV
3.3 V, 256 Kbit (32 Kbit x 8) TIMEKEEPER® SRAM
Features
Integrated, ultra low power SRAM, real-time
BYTEWIDE
BCD coded year, month, day, date, hours,
minutes, and seconds
Battery low flag (BOK)
Frequency test output for real-time clock
Automatic power-fail chip deselect and WRITE
protection
WRITE protect voltage
(V
PFD
–M48T35AV: V
2.7 V ≤ V
Self-contained battery and crystal in the
CAPHAT
SOIC package provides direct connection for a
SNAPHAT crystal
SNAPHAT
replaceable
Pin and function compatible with JEDEC
standard 32 Kbit x 8 SRAMs
RoHS compliant
– Lead-free second level interconnect
RAM-like clock access
= power-fail deselect voltage):
= 3.0 to 3.6 V;
CC
3.0 V
PFD
DIP package
®
housing containing the battery and
®
housing (battery and crystal) is
28
1
PCDIP28
battery/crystal
CAPHAT™
SNAPHAT
battery/crystal
2
8
®
1
SOH28
June 2011 Doc ID 6845 Rev 9 1/29
www.st.com
1
Contents M48T35AV
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 Clock operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 Reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Stopping and starting the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5 Century bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.6 V
noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 17
CC
4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8 Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2/29 Doc ID 6845 Rev 9
M48T35AV List of tables
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 6. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 7. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 8. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 9. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 10. Power down/up AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 11. Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 12. PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, pack. mech. data . . . . . . . . . . . . . . . . 22
Table 13. SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT Table 14. SH – 4-pin SNAPHAT Table 15. SH – 4-pin SNAPHAT
Table 16. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 17. SNAPHAT
®
battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
®
housing for 48 mAh battery & crystal, pack. mech. data . . . . . . . 24
®
housing for 120 mAh battery & crystal, pack. mech. data . . . . . . 25
Table 18. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
®
, pack. mech. data . . 23
Doc ID 6845 Rev 9 3/29
List of figures M48T35AV
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. WRITE enable controlled, WRITE mode AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. Chip enable controlled, WRITE mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 8. Checking the BOK flag status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12. AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 14. PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package outline . . . . . . . . . . . . . . . . . 22
Figure 15. SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT Figure 16. SH – 4-pin SNAPHAT Figure 17. SH – 4-pin SNAPHAT
Figure 18. Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
®
housing for 48 mAh battery & crystal, pack. outline . . . . . . . . . . . 24
®
housing for 120 mAh battery & crystal, pack. outline . . . . . . . . . . 25
®
, package outline . . . 23
4/29 Doc ID 6845 Rev 9
M48T35AV Description

1 Description

The M48T35AV TIMEKEEPER® RAM is a 32 Kbit x 8 non-volatile static RAM and real-time clock. The monolithic chip is available in two special packages to provide a highly integrated battery-backed memory and real-time clock solution.
The M48T35AV is a non-volatile pin and function equivalent to any JEDEC standard 32 Kb x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed.
The 28-pin, 600 mil DIP CAPHAT a long-life lithium button cell in a single package.
houses the M48T35AV silicon with a quartz crystal and
The 28-pin, 330 mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT
®
housing containing the battery and crystal. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion.
The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or in tape & reel form.
For the 28-lead SOIC, the battery/crystal package part numbers are M4T28-BR12SH1 (48 mAh lithium battery SNAPHAT), M4T32-BR12SH1 (120 mAh lithium battery SNAPHAT), and M4T32-BR12SH6 (120 mAh lithium battery SNAPHAT, –40 to +85 °C crystal).

Figure 1. Logic diagram

V
CC
15
A0-A14
W
M48T35AV
E
8
DQ0-DQ7
G
V
SS
Doc ID 6845 Rev 9 5/29
AI02797B
Description M48T35AV

Table 1. Signal names

A0-A14 Address inputs
DQ0-DQ7 Data inputs / outputs
E Chip enable
G Output enable
W WRITE enable
V
CC
V
SS

Figure 2. DIP connections

DQ0
DQ2

Figure 3. SOIC connections

Supply voltage
Ground
A14 V
1
A12
2
A7
3
A6
4
A5
5
A4
6
A3
7
M48T35AV
8
A2 A1
9
A0
10 11 12 13 14
SS
28 27 26 25 24 23 22 21 20 19 18 17 16 15
CC
W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5DQ1 DQ4 DQ3V
AI02798B
A7 A6 A5 A4 A3 A2 A1 A0
1
2
3
4
5
6
7
M48T35AV
8
9
10
11
A14 V A12
DQ0
12
DQ2
SS
13
14
6/29 Doc ID 6845 Rev 9
28 27 26 25 24 23 22 21 20 19 18 17 16 15
CC
W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5DQ1 DQ4 DQ3V
AI02799
M48T35AV Description

Figure 4. Block diagram

32,768 Hz CRYSTAL
LITHIUM
CELL
OSCILLATOR AND
CLOCK CHAIN
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
V
CC
POWER
V
PFD
8 x 8 BiPORT
SRAM ARRAY
32,760 x 8
SRAM ARRAY
V
SS
A0-A14
DQ0-DQ7
E
W
G
AI01623
Doc ID 6845 Rev 9 7/29
Operation modes M48T35AV

2 Operation modes

As Figure 4 on page 7 shows, the static memory array and the quartz controlled clock oscillator of the M48T35AV are integrated on one silicon chip. The two circuits are interconnected at the upper eight memory locations to provide user accessible BYTEWIDE™ clock information in the bytes with addresses 7FF8h-7FFFh.
The clock locations contain the year, month, date, day, hour, minute, and second in 24-hour BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are made automatically. Byte 7FF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting.
The eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of BiPORT™ READ/WRITE memory cells. The M48T35AV includes a clock control circuit which updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array.
The M48T35AV also has its own power-fail detect circuit. The control circuitry constantly monitors the single 3 V supply for an out of tolerance condition. When V tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low V battery backup switchover voltage (V
), the control circuitry connects the battery which
SO
. As VCC falls below the
CC
maintains data and clock operation until valid power returns.
is out of
CC

Table 2. Operating modes

Mode V
Deselect
WRITE V
READ V
READ V
Deselect VSO to V
Deselect V
1. See Table 11 on page 21 for details.
Note: X = V
or VIL; VSO = Battery backup switchover voltage.
IH

2.1 READ mode

The M48T35AV is in the READ mode whenever W (WRITE enable) is high and E (chip enable) is low. The unique address specified by the 15 address inputs defines which one of the 32,768 bytes of data is to be accessed. Valid data will be available at the data I/O pins within address access time (t the E
and G access times are also satisfied.
If the E enable access time (t
and G access times are not met, valid data will be available after the latter of the chip
CC
3.0 to 3.6 V
(min)
PFD
(1)
SO
) or output enable access time (t
ELQV
E G W DQ0-DQ7 Power
V
IH
IL
IL
(1)
AVQ V
IL
XXXHigh ZCMOS standby
XXXHigh Z
) after the last address input signal is stable, providing that
X X High Z Standby
XVILD
V
IL
V
IH
V
IH
V
IH
GLQV
IN
D
OUT
High Z Active
).
Active
Active
Battery backup mode
8/29 Doc ID 6845 Rev 9
M48T35AV Operation modes
The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are activated before t the Address Inputs are changed while E for output data hold time (t
, the data lines will be driven to an indeterminate state until t
AVQ V
and G remain active, output data will remain valid
) but will go indeterminate until the next address access.
AXQX
AVQ V
. If

Figure 5. READ mode AC waveforms

tAVAV
A0-A14
E
G
DQ0-DQ7
Note: WRITE enable (W

Table 3. READ mode AC characteristics

Symbol Parameter
t
AVAV
t
AVQ V
t
ELQV
t
GLQV
t
ELQX
t
GLQX
t
EHQZ
t
GHQZ
t
AXQX
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 3.0 to 3.6 V (except where noted).
2. CL = 5 pF.
READ cycle time 100 ns
Address valid to output valid 100 ns
Chip enable low to output valid 100 ns
Output enable low to output valid 50 ns
(2)
Chip enable low to output transition 10 ns
(2)
Output enable low to output transition 5 ns
(2)
Chip enable high to output Hi-Z 50 ns
(2)
Output enable high to output Hi-Z 40 ns
Address transition to output transition 10 ns
) = High.
VAL ID
tAVQV tAXQX
tELQV
tELQX
tGLQX
tGLQV
tGHQZ
VAL ID
tEHQZ
M48T35AV
(1)
Unit–100
Min Max
AI00925
Doc ID 6845 Rev 9 9/29
+ 20 hidden pages