ST M48T08, M48T18 User Manual

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INTEGRATED ULTRA LOW POWER SRAM, REAL TIME CLOCK , PO WE R-FAIL C O NTRO L CIRCUIT and BA T TER Y

BYTEWIDE RAM-LIKE CLOCK ACCE S S BCD CODED YEAR, MONTH, DAY, DA TE,

HOURS, MINUTES and SECONDS TYPICAL CLOCK A CCURA CY of ± 1 MINUTE

a MONTH, at 25°C AUTOMATIC POWER-F AIL CHIP DES ELECT and

WRITE PROTECTION WRITE PROTECT VOLT AGES

= Power-fail Deselect Voltage):

(V

PFD

– M48T08: 4.5V ≤ V – M48T18: 4.2V ≤ V SOFTWARE CONTROLLED CLOCK

CALIBRA TION for HIGH ACCURACY APPLICATIONS

SELF-CONTAINED BA TTER Y and CRYST AL in the CAPHA T DIP P ACKAGE

PACKAGING INCLUDES a 28-LEAD SOIC and SNAPHAT

®

TOP

(to be Ordered Separately) SOIC PACKAGE PROVIDES DIRECT

CONNECTION for a SNAPHAT TOP which CONTAINS the BATTERY and CRYSTAL

PIN and FUNCTION COMPATIBLE with DS1643 and JEDEC STANDARD 8K x 8 SRAMs

PFD PFD

4.75V

≤

4.5V

≤

M48T08 M48T18

64 Kbit (8Kb x 8) TIMEKEEPER® SRAM

SNAPHAT (SH)

Battery/Crystal

28

1

SOH28 (MH)

Figure 1. Logic Diagram

V

CC

13

A0-A12

1

PCDIP28 (PC)

Battery/Crystal

CAPHAT

8

DQ0-DQ7

T ab le 1. Signal Names

A0-A12 Address Inputs DQ0-DQ7 Data Inputs / Outputs INT Power Fail Interrupt (Open Drain) E1 Chip Enable 1 E2 Chip Enable 2 G Output Enable W Write Enable V

CC

V

SS

May 1999 1/19

Supply Voltage Ground

W

E1 INT

E2

G

M48T08 M48T18

V

SS

AI01020

M48T08, M48T18

Figure 2A. DIP Pin Connections

INT V

1

A12

2 3

A7

4

A6

5

A5

6

A4

7

A3 A2 A1 A0

DQ0

8 9 10 11

M48T08 M48T18

12 13

DQ2

14

SS

28 27 26 25 24 23 22 21 20 19 18 17 16 15

AI01182

CC

W E2 A8 A9 A11 G A10 E1 DQ7 DQ6 DQ5DQ1 DQ4 DQ3V

T ab le 2. Absolute Maximum Ratings

(1)

Figure 2B. SOIC Pin Connections

A7 A6 A5 A4 A3 A2 A1 A0

1 2 3 4 5 6 7 8 9 10 11

M48T18

INT V

A12

DQ0

12

DQ2

SS

13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

AI01021B

Symbol Parameter Value Unit

T

A

T

STG

(2)

T

SLD

V

IO

V

CC

I

O

P

D

Notes:

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indi cat ed in the operati onal section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect reliability.

2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).

CAUTION: Negat i ve undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.

Ambient Operating Temperature 0 to 70 °C Storage T emper ature (VCC Off, Oscillator Off) –40 to 85 °C Lead Solder Temperature for 10 seconds 260 °C Input or Output Voltages –0.3 to 7 V Supply Voltage –0.3 to 7 V Output Current 20 mA Power Dissipation 1 W

T ab le 3. Operating Modes

CC

W E2 A8 A9 A11 G A10 E1 DQ7 DQ6 DQ5DQ1 DQ4 DQ3V

Mode V

CC

Deselect Deselect X V Write V

4.75V to 5.5V or

4.5V to 5.5V Read V Read V

to V

Deselect V

SO

Deselect ≤ V

Notes:

1. X = V

or VIL; VSO = Battery Back-up Switchover Voltage.

IH

(min) X X X X High Z CMOS Standby

PFD

SO

E1 E2 G W DQ0-DQ7 Power

V

IH

IL

X X X X High Z Battery Back-up Mode

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X X X High Z Standby

IL

V

IH

V

IH

V

IH

X X High Z Standby XVILD

V

IL

V

IH

V

IH

V

IH

IN

D

OUT

High Z Active

Active Active

Figure 3. Block Diagram

M48T08, M48T18

OSCILLATOR AND

CLOCK CHAIN

32,768 Hz

CRYSTAL

POWER

LITHIUM

CELL

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

CC

INTV

DESCRIPTION

The M48T08/18 TIMEKEEPE R

®

RAM is an 8K x 8 non-volatile static RAM and real time clock which is pin and functional compatible with the DS1643. The monolithic chip is available in two special packages to provide a highly integrated battery backed-up memory and real time clock solution.

The M48T08/18 is a non-volatile pin and function equivalent to any JEDEC standard 8K x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special write timing or limitations on the number of writes t hat can be performed.

The 28 pin 600mil DIP CAPHAT houses the M48T08/18 silicon with a quartz crystal and a long life lithium button cell in a single package.

The 28 pin 330mil SOIC provides s ockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery and crystal. The unique design allows the SNAPHAT bat tery package to be mounted on t op of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the hig h temperatures required for device surface-mounting. The SNAPHA T housing is keyed to prevent reverse insertion.

8 x 8 BiPORT

SRAM ARRAY

A0-A12

DQ0-DQ7

E1 E2 W G

V

PFD

8184 x 8

SRAM ARRAY

V

SS

T able 4. AC Measurement Conditions

Input Rise and Fall Times ≤ 5ns Input Pulse Voltages 0 to 3V Input and Output Timing Ref. Voltages 1.5V

Note that Output Hi-Z is defined as the point where data is no longer driven.

Figure 4. AC Testing Load Circuit

5V

1.8kΩ

DEVICE UNDER

TEST

1kΩ

CL includes JIG capacitance

AI01333

OUT

CL = 100pF

AI01019

3/19

M48T08, M48T18

(1, 2)

T ab le 5. Capacitance

= 25 °C, f = 1 MHz )

(T

A

Symbol Parameter Test Condition Min Max Unit

C

IN

(3)

C

IO

Notes:

1. Effective capacitance measured with power supply at 5V .

2. Sampled only, not 100% tested.

3. Outputs deselected.

Input Capacitance VIN = 0V 10 pF Input / Output Capacitance V

= 0V 10 pF

OUT

T ab le 6. DC Characteristics

= 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)

(T

A

Symbol Parameter Test Condition Min Max Unit

(1)

I

LI

(1)

I

LO

Supply Current Outputs open 80 mA

I

CC

(2)

I

CC1

(2)

I

CC2

(3)

V

IL

V

IH

V

OL

V

OH

Notes:

1. Outputs Deselected.

2. Measured with Control Bits set as follows: R = ’1’; W, ST , FT = ’0’.

3. Negative spikes of –1V allowed for up to 10ns once per Cycle.

4. The

T able 7. Power Down/Up Trip Points DC Characteristics

= 0 to 70°C)

(T

A

Input Leakage Current 0V ≤ VIN ≤ V Output Leakage Current 0V ≤ V

OUT

CC

≤ V

Supply Current (Standby) TTL E1 = VIH, E2 = V

Supply Current (Standby) CMOS

E1 = VCC – 0.2V, E2 = V

+ 0.2V

SS

CC

IL

±1 µA ±5 µA

3mA

Input Low Voltage –0.3 0.8 V Input High Voltage 2.2 VCC + 0.3 V Output Low Voltage IOL = 2.1mA 0.4 V Output Low Voltage (

INT)

(4)

IOL = 0.5mA 0.4 V

Output High Voltage IOH = –1mA 2.4 V

INT pin is Open Drain.

(1)

Symbol Parameter Min Typ Max Unit

V

PFD

V

PFD

V

SO

t

DR

Notes:

1. All voltages referenced to V

2. At 25°C

DESCRIPTION

Power-fail Deselect Voltage (M48T08) 4.5 4.6 4.75 V Power-fail Deselect Voltage (M48T18) 4.2 4.3 4.5 V Battery Back-up Switchover Voltage 3.0 V

(2)

Expected Data Retention Time 10 YEARS

.

SS

(cont’d)

As Figure 3 shows, the static memory array and the

quartz controlled clock oscillator of the M48T08/18 The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or in Tape & Reel form. For the 28 lead SOIC, the battery/crystal package (i.e. SNAPHAT) part number is "M4T28-BR12SH1".

4/19

are integrated on one silicon chip. The two circuits

are interconnected at the upper eight memory lo-

cations to provide user accessible BYTEWIDE

clock information in the bytes with addresses

1FF8h-1FFFh.



M48T08, M48T18

T able 8. Power Down/Up Mode AC Characteristics

= 0 to 70°C)

(T

A

Symbol Parameter Min Max Unit

E1 or W at VIH or E2 at VIL before Power Down 0 µs V

(max) to V

PFD

V

(min) to VSO VCC Fall Time 10 µs

PFD

V

(min) to V

PFD

VSO to V

PFD

(min) VCC Fall Time 300 µs

PFD

(max) VCC Rise Time 0 µs

PFD

(min) VCC Rise Time 1 µs E1 or W at VIH or E2 at VIL after Power Up 1 ms INT Low to Auto Deselect 10 40 µs V

(max) to INT High 120 µs

PFD

(max) to V

PFD

passes V

CC

(min) to VSO fall time of less than tFB may cause corruption of RAM data.

PFD

(min) fall time of less than tF may result in deselection/writ e protection not occ urri ng until 200 µs after

PFD

(min).

PFD

(min) and is guaranteed to go high t

PFD

after VCC exceeds V

PFH

PFD

(max).

Notes

t

PD

(1)

t

F

(2)

t

FB

t

R

t

RB

t

REC

t

PFX

(3)

t

PFH

:1.V

V

2. V INT may go high anytime after VCC exceeds V

3.

Figure 5. Power Down/Up Mode AC Waveforms

V

CC

V

(max)

PFD

V

(min)

PFD

VSO

tF

tPD tRB

tFB

tDR

tPFX

tR

tPFH

INT

tREC

INPUTS

OUTPUTS

Note:

Inputs may or may not be recognized at this time. Caution should be taken to keep Some systems may perform inadvertent write cycles after V though a power on reset is being applied to the processor, a reset condition may not occur until after the system clock is runn ing.

VALID VALID

(PER CONTROL INPUT)

rises above V

CC

DON'T CARE

HIGH-Z

E1 high or E2 low as VCC rises past V

(min) but before normal system operations begin. Even

PFD

NOTE

RECOGNIZEDRECOGNIZED

(PER CONTROL INPUT)

AI00566

PFD

(min).

5/19

M48T08, M48T18

T ab le 9. Read Mode AC Characteristics

= 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)

(T

A

Symbol Parameter

t

AVAV

t

AVQV

t

E1LQV

t

E2HQV

t

GLQV

t

E1LQX

t

E2HQX

t

GLQX

t

E1HQZ

t

E2LQZ

t

GHQZ

t

AXQX

Read Cycle Time 100 150 ns Address Valid to Output Valid 100 150 ns Chip Enable 1 Low to Output Valid 100 150 ns Chip Enable 2 High to Output Valid 100 150 ns Output Enable Low to Output Valid 50 75 ns Chip Enable 1 Low to Output Transition 10 10 ns Chip Enable 2 High to Output Transition 10 10 ns Output Enable Low to Output Transition 5 5 ns Chip Enable 1 High to Output Hi-Z 50 75 ns Chip Enable 2 Low to Output Hi-Z 50 75 ns Output Enable High to Output Hi-Z 40 60 ns Address Transition to Output Transition 5 5 ns

M48T08 / M48T18

-100 -150

Min Max Min Max

Unit

Figure 6. Read Mode AC Waveforms

A0-A12

E1

tE1LQX

E2

tE2HQX

G

DQ0-DQ7

Note:

Write Enable (

W) = High.

tAVAV VALID

tAVQV tAXQX

tE1LQV

tE2HQV

tGLQV

tGLQX

tGHQZ

VALID

tE1HQZ

tE2LQZ

AI00962

6/19