5 V, 64 Kbit (8 Kb x 8) TIMEKEEPER® SRAM
Features
■ Integrated ultra low power SRAM, real-time
clock, power-fail control circuit, and battery
■ BYTEWIDE
■ BCD coded year, month, day, date, hours,
minutes, and seconds
■ Typical clock accuracy of ±1 minute a month, at
25 °C
■ Automatic power-fail chip deselect and WRITE
protection
■ WRITE protect
V
PFD
–M48T08: V
4.5 V ≤ V
– M48T18/T08Y: V
4.2 V ≤ V
■ Software controlled clock calibration for high
accuracy applications
■ Self-contained battery and crystal in the
CAPHAT
■ Packaging includes a 28-lead SOIC and
SNAPHAT
■ SOIC package provides direct connection for a
snaphat top which contains the battery and
crystal
■ Pin and function compatible with DS1643 and
JEDEC standard 8 K x 8 SRAMs
■ RoHS compliant
– Lead-free second level interconnect
™
RAM-like clock access
= power-fail deselect voltage):
= 4.75 to 5.5 V;
CC
≤ 4.75 V
PFD
= 4.5 to 5.5 V;
CC
≤ 4.5 V
PFD
™
DIP package
®
top (to be ordered separately)
M48T08
M48T08Y, M48T18
28
1
PCDIP28
battery/crystal
CAPHAT™
SNAPHAT
battery/crystal
2
8
®
1
SOH28
June 2011 Doc ID 2411 Rev 11 1/31
www.st.com
1
Contents M48T08, M48T08Y, M48T18
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 Power-fail interrupt pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Clock operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 Reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 Stopping and starting the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5 V
noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 18
CC
4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8 Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2/31 Doc ID 2411 Rev 11
M48T08, M48T08Y, M48T18 List of tables
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5. Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 7. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10. Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 11. Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 12. PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package mech. data . . . . . . . . . . . . . 23
Table 13. SOH28 – 28-lead plastic SO, 4-socket battery SNAPHAT
Table 14. SH – 4-pin SNAPHAT
Table 15. SH – 4-pin SNAPHAT
Table 16. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 17. SNAPHAT® battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 18. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
®
housing for 48 mAh battery & crystal, package mech. data . . . . . 25
®
housing for 120 mAh battery & crystal, package mech. data . . . . 26
®
, package mech. data. . . . . . . 24
Doc ID 2411 Rev 11 3/31
List of figures M48T08, M48T08Y, M48T18
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. WRITE enable controlled, WRITE AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7. Chip enable controlled, WRITE AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9. Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 10. Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 12. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13. PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package outline . . . . . . . . . . . . . . . . . 23
Figure 14. SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT
Figure 15. SH – 4-pin SNAPHAT
Figure 16. SH – 4-pin SNAPHAT
Figure 17. Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
®
housing for 48 mAh battery & crystal, package outline. . . . . . . . . 25
®
housing for 120 mAh battery & crystal, package outline. . . . . . . . 26
®
, package outline . . . 24
4/31 Doc ID 2411 Rev 11
M48T08, M48T08Y, M48T18 Description
1 Description
The M48T08/18/08Y TIMEKEEPER® RAM is an 8 K x 8 non-volatile static RAM and realtime clock which is pin and function compatible with the DS1643. The monolithic chip is
available in two special packages to provide a highly integrated battery-backed memory and
real-time clock solution.
The M48T08/18/08Y is a non-volatile pin and function equivalent to any JEDEC standard
8 K x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing
the non-volatility of PROMs without any requirement for special WRITE timing or limitations
on the number of WRITEs that can be performed.
The 28-pin, 600 mil DIP CAPHAT™ houses the M48T08/18/08Y silicon with a quartz crystal
and a long-life lithium button cell in a single package.
The 28-pin, 330 mil SOIC provides sockets with gold-plated contacts at both ends for direct
connection to a separate SNAPHAT
design allows the SNAPHAT
®
after the completion of the surface mount process. Insertion of the SNAPHAT
reflow prevents potential battery and crystal damage due to the high temperatures required
for device surface-mounting. The SNAPHAT
The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or
in tape & reel form. For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT
®
housing containing the battery and crystal. The unique
battery package to be mounted on top of the SOIC package
®
housing is keyed to prevent reverse insertion.
®
housing after
®
)
part number is “M4T28-BR12SH” or “M4T32-BR12SH”.
Figure 1. Logic diagram
V
CC
13
A0-A12
W
E1 INT
E2
M48T08
M48T08Y
M48T18
8
DQ0-DQ7
G
V
SS
Doc ID 2411 Rev 11 5/31
AI01020
Description M48T08, M48T08Y, M48T18
Table 1. Signal names
A0-A12 Address inputs
DQ0-DQ7 Data inputs / outputs
INT Power fail interrupt (open drain)
E1 Chip enable 1
E2 Chip enable 2
G Output enable
W WRITE enable
V
CC
V
SS
Supply voltage
Ground
Figure 2. DIP connections
Figure 3. SOIC connections
INT V
1
A12
2
A7
3
A6
4
A5
5
A4
6
A3
7
8
9
10
11
M48T08
M48T18
A2
A1
A0
DQ0
12
DQ2
13
14
SS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CC
W
E2
A8
A9
A11
G
A10
E1
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V
AI01182
INT V
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
1
2
3
4
5
6
7
M48T08Y
8
9
10
11
12
DQ2
SS
13
14
6/31 Doc ID 2411 Rev 11
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CC
W
E2
A8
A9
A11
G
A10
E1
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V
AI01021B
M48T08, M48T08Y, M48T18 Description
Figure 4. Block diagram
32,768 Hz
CRYSTAL
LITHIUM
CELL
OSCILLATOR AND
CLOCK CHAIN
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
CC
INTV
POWER
V
PFD
8 x 8 BiPORT
SRAM ARRAY
8184 x 8
SRAM ARRAY
V
SS
A0-A12
DQ0-DQ7
E1
E2
W
G
AI01333
Doc ID 2411 Rev 11 7/31
Operation modes M48T08, M48T08Y, M48T18
2 Operation modes
As Figure 4 on page 7 shows, the static memory array and the quartz-controlled clock
oscillator of the M48T08/18/08Y are integrated on one silicon chip. The two circuits are
interconnected at the upper eight memory locations to provide user accessible
BYTEWIDE™ clock information in the bytes with addresses 1FF8h-1FFFh.
The clock locations contain the year, month, date, day, hour, minute, and second in 24-hour
BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are
made automatically. Byte 1FF8h is the clock control register. This byte controls user access
to the clock information and also stores the clock calibration setting.
The eight clock bytes are not the actual clock counters themselves; they are memory
locations consisting of BiPORT™ READ/WRITE memory cells. The M48T08/18/08Y
includes a clock control circuit which updates the clock bytes with current information once
per second. The information can be accessed by the user in the same manner as any other
location in the static memory array.
The M48T08/18/08Y also has its own power-fail detect circuit. The control circuitry
constantly monitors the single 5 V supply for an out-of-tolerance condition. When V
of tolerance, the circuit write protects the SRAM, providing a high degree of data security in
the midst of unpredictable system operation brought on by low V
battery backup switchover voltage (V
), the control circuitry connects the battery which
SO
. As VCC falls below the
CC
maintains data and clock operation until valid power returns.
CC
is out
Table 2. Operating modes
Mode V
Deselect
Deselect X V
WRITE V
READ V
READ V
Deselect
Deselect ≤ V
1. See Table 11 on page 22 for details.
Note: X = V
IH
or V
CC
4.75 to 5.5 V
or
4.5 to 5.5 V
to
V
SO
(1)
(min)
V
PFD
(1)
SO
IL ; VSO
= Battery backup switchover voltage.
E1 E2 G W DQ0-DQ7 Power
V
IH
IL
IL
IL
X X X High Z Standby
IL
V
IH
V
IH
V
IH
X X High Z Standby
XVILD
V
IL
V
IH
V
IH
V
IH
IN
D
OUT
High Z Active
Active
Active
XXXXHigh ZCMOS standby
X X X X High Z Battery backup mode
8/31 Doc ID 2411 Rev 11
M48T08, M48T08Y, M48T18 Operation modes
2.1 READ mode
The M48T08/18/08Y is in the READ mode whenever W (WRITE enable) is high, E1 (chip
enable 1) is low, and E2 (chip enable 2) is high. The device architecture allows ripplethrough access of data from eight of 65,536 locations in the static storage array. Thus, the
unique address specified by the 13 address inputs defines which one of the 8,192 bytes of
data is to be accessed. Valid data will be available at the data I/O pins within address access
time (t
access times are also satisfied. If the E1
be available after the latter of the chip enable access times (t
enable access time (t
The state of the eight three-state data I/O signals is controlled by E1
outputs are activated before t
until t
will remain valid for output data hold time (t
address access.
Figure 5. READ mode AC waveforms
) after the last address input signal is stable, providing that the E1, E2, and G
AVQ V
, E2 and G access times are not met, valid data will
GLQV
or t
E1LQV
).
E2HQV
) or output
, E2 and G. If the
, the data lines will be driven to an indeterminate state
. If the address inputs are changed while E1, E2 and G remain active, output data
AVQ V
AVQ V
tAVAV
) but will go indeterminate until the next
AXQX
A0-A12
E1
E2
G
DQ0-DQ7
Note: WRITE enable (W
VAL ID
tAVQV tAXQX
tE1LQV
tE1LQX
tE2HQV
tE2HQX
tGLQV
tGLQX
VAL ID
tGHQZ
) = high.
tE1HQZ
tE2LQZ
AI00962
Doc ID 2411 Rev 11 9/31
Operation modes M48T08, M48T08Y, M48T18
Table 3. READ mode AC characteristics
M48T08/M48T18/T08Y
Symbol Parameter
(1)
Unit–100/–10 (T08Y) –150/–15 (T08Y)
Min Max Min Max
t
AVAV
t
AVQ V
t
E1LQV
t
E2HQV
t
GLQV
t
E1LQX
t
E2HQX
t
GLQX
t
E1HQZ
t
E2LQZ
t
GHQZ
t
AXQX
READ cycle time 100 150 ns
Address valid to output valid 100 150 ns
Chip enable 1 low to output valid 100 150 ns
Chip enable 2 high to output valid 100 150 ns
Output enable low to output valid 50 75 ns
Chip enable 1 low to output transition 10 10 ns
Chip enable 2 high to output transition 10 10 ns
Output enable low to output transition 5 5 ns
Chip enable 1 high to output Hi-Z 50 75 ns
Chip enable 2 low to output Hi-Z 50 75 ns
Output enable high to output Hi-Z 40 60 ns
Address transition to output transition 5 5 ns
Note: Valid for ambient operating temperature: T
(except where noted).
2.2 WRITE mode
The M48T08/18/08Y is in the WRITE mode whenever W, E1, and E2 are active. The start of
a WRITE is referenced from the latter occurring falling edge of W
E2. A WRITE is terminated by the earlier rising edge of W
The addresses must be held valid throughout the cycle. E1
for a minimum of t
initiation of another READ or WRITE cycle. Data-in must be valid t
WRITE and remain valid for t
avoid bus contention; however, if the output bus has been activated by a low on E1
and a high on E2, a low on W
E1HAX
or t
from chip enable or t
E2LAX
afterward. G should be kept high during WRITE cycles to
WHDX
will disable the outputs t
= 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V
A
or E1, or the rising edge of
or E1, or the falling edge of E2.
or W must return high or E2 low
from WRITE enable prior to the
WHAX
prior to the end of
DVW H
and G
after W falls.
WLQZ
10/31 Doc ID 2411 Rev 11
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