ST M45PE10 User Manual
查询M45PE10供应商
1 Mbit, Low Voltage, Page-Erasable Serial Flash Memory
With Byte-Alterability and a 33 MHz SPI Bus Interface
FEATURES SUMMARY
■ 1Mbit of Page-Erasable Flash Memory
■ Page Write (up to 256 Bytes) in 11ms (typical)
■ Page Program (up to 256 Bytes) in 1.2ms
(typical)
■ Page Erase (256 Bytes) in 10ms (typical)
■ Sector Erase (512 Kbit)
■ 2.7 to 3.6V Single Supply Voltage
■ SPI Bus Compatible Serial Interface
■ 33MHz Clock Rate (maximum)
■ Deep Power-down Mode 1µA (typical)
■ Electronic Signature
– JEDEC Standard Two-Byte Signature
(4011h)
■ More than 100,000 Write Cycles
■ More than 20 Year Data Retention
■ Packages
– ECOPACK® (RoHS compliant)
M45PE10
Figure 1. Packages
8
1
SO8 (MN)
150 mil width
VDFPN8 (MP)
(MLP8)
1/34October 2005
M45PE10
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Data Output (Q). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Reset (Reset
Write Protect (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SPI MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
OPERATING FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Sharing the Overhead of Modifying Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
An Easy Way to Modify Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
A Fast Way to Modify Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Polling During a Write, Program or Erase Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Active Power, Standby Power and Deep Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write Disable (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Read Status Register (RDSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Read Data Bytes (READ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read Data Bytes at Higher Speed (FAST_READ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Page Write (PW). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Page Erase (PE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Deep Power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Release from Deep Power-down (RDP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/34
M45PE10
POWER-UP AND POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3/34
M45PE10
SUMMARY DESCRIPTION
The M45PE10 is a 1Mbit (128K x 8 bit) Serial
Paged Flash Memory accessed by a high speed
SPI-compatible bus.
The memory can be written or programmed 1 to
256 bytes at a time, using the Page Write or Page
Program instruction. The Page Write instruction
consists of an integrated Page Erase cycle followed by a Page Program cycle.
The memory is organized as 2 sectors, each containing 256 pages. Each page is 256 bytes wide.
Thus, the whole memory can be viewed as consisting of 512 pages, or 131,072 bytes.
The memory can be erased a page at a time, using
the Page Erase instruction, or a sect or at a time,
using the Sector Erase instruction.
In order to meet environmental requirements, ST
offers these devices in ECOPACK® packages.
ECOPACK® packages are Lead-free and RoHS
compliant.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 2. Logic Diagram
V
CC
Figure 3. SO and VDFPN Connections
M45PE10
DQ
1
C
2
Reset
Note: 1. The re is an exposed d ie paddle on th e underside of th e
MLP8 package. This is pulled, internally, to VSS, and
must not be allowed to be connecte d to any oth er voltage
or signal line on the PCB.
2. See PACKAGE MECHANICAL section for packag e dimensions, and how to identify pin-1.
3
4
8
7
6
5
AI07404
V
SS
V
CC
WS
W
Reset
Table 1. Signal Names
D
C
S
M45PE10
V
SS
Q
AI07403
C Serial Clock
D Serial Data Input
Q Serial Data Output
S
Write Protect
W
Reset
Reset
V
CC
V
SS
Chip Select
Supply Voltage
Ground
4/34
SIGNAL DESCRIPTION
Serial Data Output (Q). This output signal is
used to transfer data serially out of the device.
Data is shifted out on the falling edge of Serial
Clock (C).
Serial Data Input (D). This input signal is used to
transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the risin g edge of
Serial Clock (C).
Serial Clock (C). This input signal provides the
timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are
latched on the rising edge of Serial Clock (C). Data
on Serial Data Output (Q) changes after the falling
edge of Serial Clock (C).
Chip Select (S
the device is deselected and Serial Data Output
(Q) is at high impedance. Unless an interna l Read,
Program, Erase or Write cycle is in progress, the
device will be in the Standby Power mode (this is
not the Deep Power-down mode). Driving Chip
Select (S
Active Power mode.
). When this input signal is High,
) Low selects the device, placing it in the
M45PE10
After Power-up, a falling edge on Chip Select (S
is required prior to the start of any instruction.
Reset (Reset
a hardware reset for the memory. In this mode, the
outputs are high impedance.
When Reset (Reset
in the normal operating mode. When Reset (Reset) is driven Low, the memory will enter the Reset
mode, provided that no internal operation is currently in progress. Driving Reset (Reset
an internal operation is in progress has no effect
on that internal operation (a write cycle, program
cycle, or erase cycle).
Write Protect (W
vice in the Hardware Protected mode, when Write
Protect (W
256 pages of memory to become read-o nly by protecting them from write, program and erase operations. When Write Protect (W
, the first 256 pages of memory behave like
V
CC
the other pages of memory.
). Th e Reset (Reset) input provides
) is driven High, the memory is
) Low while
). This input signal puts the de-
) is connected to VSS, causing the first
) is connected to
)
5/34
M45PE10
SPI MODES
These devices can be driven by a microcon troller
with its SPI peripheral running in either of the two
following modes:
– CPOL=0, CPHA=0
– CPOL=1, CPHA=1
For these two modes, input data is latched in on
the rising edge of Serial Clock (C), and output data
Figure 4. Bus Master and Memory Devices on the SPI Bus
is available from the falling edge of Serial Clock
(C).
The difference between the two modes, as shown
in Figure 5., is the clock polarity when the bus
master is in Stand-by mode and not transferring
data:
– C remains at 0 for (CPOL=0, CPHA=0)
– C remains at 1 for (CPOL=1, CPHA=1)
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
Bus Master
(ST6, ST7, ST9,
ST10, Others)
CS3 CS2 CS1
Note: The Write Protect (W) signal should be driven, High or Low as appropriate.
SDO
SDI
SCK
CQD
SPI Memory
Device
S
RP
W
Figure 5. SPI Modes Supported
CQD
SPI Memory
Device
S
CQD
SPI Memory
Device
RP
W
S
W
AI04043B
RP
CPOL
6/34
CPHA
0
0
1
1
C
C
D
Q
MSB
MSB
AI01438B
OPERATING FEATURES
Sharing the Overhead of Modifying Data
To write or program one (or more) data bytes, two
instructions are required: Write Enable (WREN),
which is one byte, and a Page Write (PW) or Page
Program (PP) sequence, which consists of four
bytes plus data. This is followed by the internal cycle (of duration t
To share this overhead, the Page Write (PW) or
Page Program (PP) instruction allows up to 256
bytes to be programmed (changing bits from 1 to
0) or written (changing bits to 0 or 1) at a time, provided that they lie in consecutive addresses on the
same page of memory.
An Easy Way to Modify Data
The Page Write (PW) instruction provides a convenient way of modifying data (up to 256 contiguous bytes at a time), and simply requires the start
address, and the new data in the instruction sequence.
The Page Write (PW) instruction is entered by
driving Chip Select (S
the instruction byte, three address bytes (A23-A0)
and at least one data byte, and then driving Chip
Select (S
) High. While Chip Select (S) is being
held Low, the data bytes are written to the data
buffer, starting at the addr ess given in the third address byte (A7-A0). When Chip Select (S
High, the Write cycle starts. The remaining, unchanged, bytes of the data buffer are automatically
loaded with the values of the corresponding bytes
of the addressed memory page. The addressed
memory page then automatically put into an Erase
cycle. Finally, the addressed memory page is programmed with the contents of the data buffer.
All of this buffer management is handled internally,
and is transparent to the user. The user is given
the facility of being able to alter the contents of the
memory on a byte-by-byte basis.
For optimized timings, it is recommended to use
the Page Write (PW) instruction to write all consecutive targeted Bytes in a single sequence versus using several Page Write (PW) sequences
with each containing only a few Bytes (see Page
Write (PW) and AC Characteristics (33MHz operation)).
A Fast Way to Modify Data
The Page Program (PP) instruction provides a fast
way of modifying data (up to 256 contiguous byte s
at a time), provided that it only involves resetting
bits to 0 that had previously been set to 1.
This might be:
– when the designer is programming the device
for the first time
– when the designer knows that the page has
already been erased by an earlier Page Erase
or tPP).
PW
) Low, and then transmitting
) is driven
M45PE10
(PE) or Sector Erase (SE) instruction. This is
useful, for example, when storing a fast
stream of data, having first performed the
erase cycle when time was available
– when the designer knows that the only
changes involve resetting bits to 0 that are still
set to 1. When this method is possible, it has
the additional advantage of minimising the
number of unnecessary erase ope rations, and
the extra stress incurred by each page.
For optimized timings, it is recommended to use
the Page Program (PP) instruction to program all
consecutive targeted Bytes in a single sequence
versus using several Page Program (PP) sequences with each containing only a few Bytes
(see Page Program (PP) and AC Characteristics
(33MHz operation)).
Polling During a Write, Program or Eras e Cycle
A further improvement in the write, program or
erase time can be achieved by not waiting for the
worst case delay (t
In Progress (WIP) bit is provided in the Status
Register so that the application program can monitor its value, polling it to establish when the previous cycle is complete.
Reset
An internal Power On Reset circuit helps protect
against inadvertent data writes. Addition protection is provided by driving Reset (Reset
ing the Power-on process, and only driving it High
when V
V
CC
has reached the correct voltage level,
CC
(min).
Active Power, Standby Power and Deep
Power-Down Modes
When Chip Select (S
ed, and in the Active Power mode.
When Chip Select (S
lected, but could remain in the Active Power mode
until all internal cycles have completed (Program,
Erase, Write). The device then goes in to the
Standby Power mode. The device consumption
drops to I
CC1
.
The Deep Power-down mode is entered when the
specific instruction (the Deep Power-down (DP) instruction) is executed. The device consumption
drops further to I
mode until another specific instruction (the Release from Deep Power-down and Re ad Electro nic Signature (RES) instruction) is executed.
All other instructions are ignored while the device
is in the Deep Power-down mode. This can be
used as an extra software protection mechanism,
when the device is not in active use, to protect the
device from inadvertent Write, Program or Erase
instructions.
, tPP, tPE, or tSE). The Write
PW
) Low dur-
) is Low, the device is select-
) is High, the device is dese-
. The device remains in this
CC2
7/34
M45PE10
Status Register
The Status Register contains two status bits that
can be read by the Read Status Register (RDSR)
instruction.
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write, Progr am
or Erase cycle.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Writ e Enable Latch.
Table 2. Status Register Format
b7 b0
0 0 0 0 0 0 WEL WIP
Note: WEL and WIP are volatile read-only bits (WEL is set and re-
set by specific instructions; WIP is automatically set and reset by the internal logic of the device).
Protection Modes
The environments where non-volatile memor y devices are used can be very noisy. No SPI device
can operate correctly in the presence of excessive
noise. To help combat this, the M45PE10 features
the following data protection mechanisms:
■ Power On Reset and an internal timer (t
PUW
can provide protection against inadvertant
changes while the power supply is outside the
operating specification.
■ Program, Erase and Write instructions are
checked that they consist of a number of clock
pulses that is a multiple of eight, before they
are accepted for execution.
■ All instructions that modify data must be
preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch
(WEL) bit. This bit is returned to its reset state
by the following events:
– Power-up
– Reset (RESET
) driven Low
– Write Disable (WRDI) instruction
completion
– Page Write (PW) instruction completion
– Page Program (PP) instruction completion
– Page Erase (PE) instruction completion
– Sector Erase (SE) instruction completion
■ The Hardware Protected mode is entere d
when Write Protect (W
) is driven Low, causing
the first 256 pages of memory to become
read-only. When Write Protect (W
High, the first 256 pages of memory behave
like the other pages of memory
■ The Reset (Reset) signal can be driven Low to
)
protect the contents of the memory during any
critical time, not just during Power-up and
Power-down.
■ In addition to the low power consumption
feature, the Deep Power-down mode offers
extra software protection from inadvertant
Write, Program and Erase instructions while
the device is not in active use.
) is driven
8/34
MEMORY ORGANIZATION
The memory is organized as:
■ 512 pages (256 bytes each).
■ 131,072 bytes (8 bits each)
■ 2 sectors (512 Kbits, 65536 bytes each)
Each page can be individually:
– programmed (bits are programmed from 1 to
0)
– erased (bits are erased from 0 to 1)
– written (bits are changed to either 0 or 1)
Figure 6. Block Diagram
M45PE10
The device is Page or Sector Erasable (bits ar e
erased from 0 to 1).
Table 3. Memory Organization
Sector Address Range
1 10000h 1FFFFh
0 00000h 0FFFFh
Reset
W
S
C
D
Q
Control Logic
Address Register
and Counter
10000h
Y Decoder
High Voltage
Generator
I/O Shift Register
256 Byte
Data Buffer
Status
Register
1FFFFh
First 256 Pages can
be made read-only
00000h
000FFh
256 Bytes (Page Size)
X Decoder
AI07405
9/34
M45PE10
INSTRUCTIONS
All instructions, addresses and data are shifted in
and out of the device, most significant bit firs t.
Serial Data Input (D) is sampled on the first rising
edge of Serial Clock (C) after Chip Select (S
) is
driven Low. Then, the one-byte instruction code
must be shifted in to the device, most significant bit
first, on Serial Data Input (D), each bit being
latched on the rising edges of Serial Clock (C).
The instruction set is listed in Table 4.
Every instruction sequence starts with a one-byte
instruction code. Depending on the instruction,
this might be followed by address bytes, or by data
bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read
Data Bytes at Higher Speed (Fast_Read) or Read
Status Register (RDSR) instruction, the shifted-in
instruction sequence is followed by a data-out se-
quence. Chip Select (S
any bit of the data-out sequence is being shifted
out.
In the case of a Page Write (PW), Page Program
(PP), Page Erase (PE), Sector Erase (SE), Write
Enable (WREN), Write Disable (WRDI), Deep
Power-down (DP) or Release from Deep Pow erdown (RDP) instruction, Chip Select (S
driven High exactly at a byte boundary, otherwise
the instruction is rejected, and is not executed.
That is, Chip Select (S
number of clock pulses after Chip Select (S
driven Low is an exact multiple of eight.
All attempts to access the memory array during a
Write cycle, Program cycle or Erase cycle are ignored, and the internal Write cycle, Program cycle
or Erase cycle continues unaffected.
Table 4. Instruction Set
Instruction Description One-byte Instruction Code
WREN Write Enable 0000 0110 06h 0 0 0
WRDI Write Disable 0000 0100 04h 0 0 0
RDID Read Identification 1001 1111 9Fh 0 0 1 to 3
RDSR Read Status Register 0000 0101 05h 0 0 1 to ∞
READ Read Data Bytes 0000 0011 03h 3 0 1 to ∞
FAST_READ Read Data Bytes at Higher Speed 0000 1011 0Bh 3 1 1 to ∞
PW Page Write 0000 1010 0Ah 3 0 1 to 256
PP Page Program 0000 0010 02h 3 0 1 to 256
PE Page Erase 1101 1011 DBh 3 0 0
SE Sector Erase 1101 1000 D8h 3 0 0
DP Deep Power-down 1011 1001 B9h 0 0 0
RDP Release from Deep Power-down 1010 1011 ABh 0 0 0
) can be driven High after
) must be
) must driven High when the
) being
Address
Bytes
Dummy
Bytes
Data
Bytes
10/34
M45PE10
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 7.)
sets the Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set pr ior to every Page Write (PW), Page Progr am (PP),
Page Erase (PE), and Sector Erase (SE) instruction.
The Write Enable (WREN) instruction is entered
by driving Chip Select (S
struction code, and then driving Chip Select (S
High.
Figure 7. Write Enable (WREN) Instruction Sequence
S
0
21 34567
C
Instruction
D
High Impedance
Q
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 8.)
resets the Write Enable Latch (WEL) bit.
The Write Disable (WRDI) instruction is entered by
driving Chip Select (S
tion code, and then driving Chip Select (S
) Low, sending the instruc-
) High.
The Write Enable Latch (WEL) bit is r eset under
–Power-up
– Write Disable (WRDI) instruction completion
– Page Write (PW) instruction comple tio n
– Page Program (PP) instruction completion
– Page Erase (PE) instruction completion
– Sector Erase (SE) instruction completion
the following conditions:
) Low, sending the in-
)
AI02281E
Figure 8. Write Disable (WRDI) Instruction Sequence
S
0
21 34567
C
Instruction
D
High Impedance
Q
AI03750D
11/34
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