ST M41T93 User Manual
Serial SPI bus real-time clock with battery switchover
Features
■ Ultra-low battery supply current of 365 nA
■ Factory calibrated accuracy ±5 ppm
guaranteed after 2 reflows (SOX18)
– Much better accuracies achievable using
built-in programmable analog and digital
calibration circuits
■ 2.0 V to 5.5 V clock operating voltage
■ Counters for tenths/hundredths of seconds,
seconds, minutes, hours, day, date, month,
year, and century
■ Automatic switchover and reset output circuitry
(fixed reference)
–M41T93S: V
(2.85 V ≤ V
–M41T93R: V
(2.55 V ≤ V
–M41T93Z: V
(2.25 V ≤ V
■ Compatible with SPI bus serial interface
(supports SPI mode 0 [CPOL = 0, CPHA = 0])
■ Programmable alarm with interrupt function
(valid even during battery backup mode)
■ Optional 2
■ Square wave output (defaults to 32 KHz on
nd
power-up)
■ RESET (RST) output
■ Watchdog timer
■ Programmable 8-bit counter/timer
■ 7 bytes of battery-backed user SRAM
■ Battery low flag
■ Low operating current of 80 µA
■ Oscillator stop detection
■ Battery or SuperCap™ backup
■ Operating temperature of –40 °C to +85 °C
= 3.0 V to 5.5 V
CC
≤ 3.00 V)
RST
= 2.7 V to 5.5 V
CC
≤ 2.70 V)
RST
= 2.38 V to 5.50 V
CC
≤ 2.38 V)
RST
programmable alarm available
M41T93
QFN16, 4 mm x 4 mm
18
1
SOX18 (18-pin, 300 mil SOIC
with embedded crystal)
■ Package options include:
– a 16-lead QFN or an 18-lead embedded
crystal SOIC
■ RoHS compliance: lead-free components are
compliant with the RoHS directive
October 2011 Doc ID 12615 Rev 6 1/51
www.st.com
1
Contents M41T93
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 SPI signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1.1 Serial data output (SDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1.2 Serial data input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1.3 Serial clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1.4 Chip enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 SPI bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2 READ and WRITE cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3 Data retention and battery switchover (V
2.4 Power-on reset (t
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
rec
SO
= V
) . . . . . . . . . . . . . . . . 15
RST
3 Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 Clock data coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1.1 Example of incoherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1.2 Accessing the device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2 Halt bit (HT) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.1 Power-down time stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3 Real-time clock accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4 Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4.1 Digital calibration (periodic counter correction) . . . . . . . . . . . . . . . . . . . 22
3.4.2 Analog calibration (programmable load capacitance) . . . . . . . . . . . . . . 24
3.5 Setting the alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.6 Optional second programmable alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.7 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.8 8-bit (countdown) timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.8.1 TI/TP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.8.2 TF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.8.3 TIE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.8.4 TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.8.5 TD1/0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.9 Square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2/51 Doc ID 12615 Rev 6
M41T93 Contents
3.10 Battery low warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.11 Century bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.12 Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.13 Oscillator fail detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.14 Oscillator fail interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.15 Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.16 OTP bit operation (SOX18 package only) . . . . . . . . . . . . . . . . . . . . . . . . 36
4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Doc ID 12615 Rev 6 3/51
List of tables M41T93
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Function table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Clock/control register map (32 bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 4. Digital calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 5. Analog calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 6. Alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 7. Timer control register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 8. Interrupt operation (bit TI
Table 9. Timer source clock frequency selection (244.1 µs to 4.25 hrs). . . . . . . . . . . . . . . . . . . . . . 32
Table 10. Timer countdown value register bits (addr 11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 11. Square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 12. Century bits examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 13. Initial power-on default values (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 14. Initial power-up default values (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 15. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 16. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 17. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 18. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 19. Crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 20. Oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 21. Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 22. AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 23. QFN16 – 16-lead, quad, flat package, no lead, 4 x 4 mm body, mech. data . . . . . . . . . . . 45
Table 24. SOX18 – 18-lead plastic SO, 300 mils, embedded crystal, pkg. mech. data . . . . . . . . . . . 47
Table 25. Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 26. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
/TP = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4/51 Doc ID 12615 Rev 6
M41T93 List of figures
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. QFN16 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. SOX18 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. Data and clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. WRITE mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. Clock data coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 10. Internal load capacitance adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 11. Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 12. Clock accuracy vs. on-chip load capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 13. Clock divider chain and calibration circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 14. Crystal isolation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 15. Alarm interrupt reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 16. Backup mode alarm waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 17. Measurement AC I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 18. I
Figure 19. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 20. Input timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 21. Output timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 22. QFN16 – 16-lead, quad, flat package, no lead, 4 x 4 mm body size, outline . . . . . . . . . . . 45
Figure 23. QFN16 – 16-lead, quad, flat, no lead, 4 x 4 mm, recommended footprint . . . . . . . . . . . . . 46
Figure 24. 32 KHz crystal + QFN16 vs. VSOJ20 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 25. SOX18 – 18-lead plastic small outline, 300 mils, embedded crystal . . . . . . . . . . . . . . . . . 47
vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
CC2
Doc ID 12615 Rev 6 5/51
Description M41T93
1 Description
The M41T93 is a low-power serial SPI bus real-time clock with a built-in 32.768 kHz
oscillator (external crystal-controlled for the QFN16 package, and embedded crystal for the
SOX18 package). Eight bytes of the register map are used for the clock/calendar function
and are configured in binary coded decimal (BCD) format. An additional 17 bytes of the
register map provide status/control of the two alarms, watchdog, 8-bit counter, and square
wave functions. An additional seven bytes are made available as user SRAM.
Addresses and data are transferred serially via a serial SPI bus-compatible interface. The
built-in address register is incremented automatically after each WRITE or READ data byte.
The M41T93 has a built-in power sense circuit which detects power failures and
automatically switches to the battery supply when a power failure occurs. The energy
needed to sustain the clock operations can be supplied by a small lithium button battery
when a power failure occurs.
Functions available to the user include a non-volatile, time-of-day clock/calendar, alarm
interrupt, watchdog timer, programmable 8-bit counter, and square wave outputs. The eight
clock address locations contain the century, year, month, date, day, hour, minute, second,
and tenths/hundredths of a second in 24-hour BCD format. Corrections for 28, 29 (leap
year), 30, and 31 day months are made automatically. The M41T93 is supplied in either a
QFN16 or an SOX18, 300 mil SOIC which includes an embedded 32 KHz crystal. The
SOX18 package requires only a user-supplied battery to provide non-volatile operation.
6/51 Doc ID 12615 Rev 6
M41T93 Description
Figure 1. Logic diagram
V
V
BAT
CC
(1)
1. For QFN16 package only
2. Defaults to 32 KHz on power-up
3. Open drain
Table 1. Signal names
Symbol Description
(1)
XI
(1)
XO
/FT/OUT Interrupt /frequency test/output driver (open drain)
IRQ
(2)
SQW
RST
E
32 KHz oscillator input
32 KHz oscillator output
32 KHz programmable square wave output
Power-on reset output (open drain)
Chip enable
XO
SCL
XI
SDI
(1)
E
V
SS
(2)
SQW
IRQ/OUT/FT
(3)
RST
SDO
(3)
AI11818
SDI Serial data address input
SDO Serial data address output
SCL Serial clock input
V
BAT
(3)
DU
V
CC
V
SS
1. For QFN16 package only
2. Defaults to 32 KHz on power-up
3. Do not use (must be tied to VCC)
Battery supply voltage (Tie V
Do not use
Supply voltage
Ground
to VSS if no battery is connected.)
BAT
Doc ID 12615 Rev 6 7/51
Description M41T93
Figure 2. QFN16 connections
CC
15
V
XI
14
13
E
12
11
SDO
IRQ/FT/OUT
(1)
RST
NC
(1)
XO
16
1
2
M41T93
SQW
NC
(2)
3
4
6
5
BAT
V
7
SS
NC
V
SCL
10
9
SDI
8
NC
AI11819
1. Open drain output
2. Defaults to 32 KHz on power-up
Figure 3. SOX18 connections
NF
NF
RST
DU
SQW
V
V
NC
NC
BAT
SS
1
(1)
2
(1)
3
4
(2)
5
6
7
M41T93
(3)
(4)
8
9
18
17
16
15
14
13
12
11
10
NC
(1)
NF
(1)
NF
V
CC
E
SDO
IRQ/FT/OUT
SCL
SDI
(2)
1. NF pins must be tied to VSS. Pins 2 and 3, and 16 and 17 are internally shorted together.
2. Open drain output
3. Do not use (must be tied to V
CC
)
4. Defaults to 32 KHz on power-up
AI11820
8/51 Doc ID 12615 Rev 6
M41T93 Description
Figure 4. Block diagram
REAL TIME CLOCK
CALENDAR
CRYSTAL
SDI
SCL
SDO
V
CC
V
E
BAT
V
RST/VSO
XI
OSCILLATOR
XO
INTERFACE
COMPARE
(2)
32KHz
SPI
WRITE
PROTECT
VCC < V
RST
OSCILLATOR FAIL
CIRCUIT
ALARM1
ALARM2
WATCHDOG
FREQUENCY TEST
OUTPUT DRIVER
8-BIT COUNTER
SQUARE WAVE
8 BITS OF OTP
USER SRAM (7 Bytes)
OFIE
A1IE
FT
OUT
TIE
SQWE
INTERNAL
POWER
t
rec
TIMER
IRQ/FT/OUT
SQW
(1)
RST
(1)
AI11821
1. Open drain output
2. V
= VSO = 2.93 V (S), 2.63 V (R), and 2.32 V (Z)
RST
Doc ID 12615 Rev 6 9/51
Description M41T93
Figure 5. Hardware hookup
V
CC
MCU
M41T93
V
CC
XI
XO
V
V
BAT
SS
IRQ/FT/OUT
RST
SQW
(1)
(1)
SCL
SDO
SDI
E
1. Open drain output
2. CPOL (clock polarity) and CPHA (clock phase) are bits that may be set in the SPI control register of the MCU.
Table 2. Function table
(ST6, ST7, ST9, ST10, Others)
V
CC
INT
Reset Input
SCL
(2)
SDI
SDO
CS
32KHz CLKIN
SPI Interface with
(CPOL = 0, CPHA = 0)
AI11822
Mode E SCL SDI SDO
Disable reset H Input disabled Input disabled High Z
WRITE L
AI04630
READ L
AI04631
Data bit latch High Z
X Next data bit shift
1. SDO remains at High Z until eight bits of data are ready to be shifted out during a READ.
Figure 6. Data and clock timing
CPOL
CPHA
0
0
C
SDI
SDO
MSB
MSB
LSB
LSB
(1)
Note: Supports SPI mode 0 (CPOL = 0, CPHA = 0) only.
10/51 Doc ID 12615 Rev 6
AI04632
M41T93 Description
1.1 SPI signal description
1.1.1 Serial data output (SDO)
The output pin is used to transfer data serially out of the memory. Data is shifted out on the
falling edge of the serial clock.
1.1.2 Serial data input (SDI)
The input pin is used to transfer data serially into the device. Instructions, addresses, and
the data to be written, are each received this way. Input is latched on the rising edge of the
serial clock.
1.1.3 Serial clock (SCL)
The serial clock provides the timing for the serial interface (as shown in Figure 20 on
page 42 and Figure 21 on page 42). The W/R bit, addresses, or data are latched, from the
input pin, on the rising edge of the clock input. The output data on the SDO pin changes
state after the falling edge of the clock input.
The M41T93 can be driven by a microcontroller with its SPI peripheral running in only mode
0: (CPOL, CPHA) = (0,0).
For this mode, input data (SDI) is latched in by the low-to-high transition of clock SCL, and
output data (SDO) is shifted out on the high-to-low transition of SCL (see Tab l e 2 o n
page 10 and Figure 6 on page 10).
1.1.4 Chip enable (E)
When E is high, the memory device is deselected, and the SDO output pin is held in its high
impedance state.
After power-on, a high-to-low transition on E
is required prior to the start of any operation.
Doc ID 12615 Rev 6 11/51
Operation M41T93
2 Operation
The M41T93 clock operates as a slave device on the SPI serial bus. Each memory device is
accessed by a simple serial interface that is SPI bus-compatible. The bus signals are SCL,
SDI, and SDO (see Table 1 on page 7 and Figure 5 on page 10). The device is selected
when the chip enable input (E
serially in and out of the chip. The most significant bit is presented first, with the data input
(SDI) sampled on the first rising edge of the clock (SCL) after the chip enable (E
The 32 bytes contained in the device can then be accessed sequentially in the following
order:
1
Tenths/hundredths of a second register
2
Seconds register
3
Minutes register
4
Century/hours register
5
Day register
6
Date register
) is held low. All instructions, addresses and data are shifted
) goes low.
7
Month register
8
Year register
9
Digital calibration register
10
Watchdog register
11-15
21-25
26-32
Alarm1 registers
16
Flags register
17
Timer value register
18
Timer control register
19
Analog calibration register
20
Square wave register
Alarm2 registers
User RAM
The M41T93 clock continually monitors VCC for an out-of tolerance condition. Should VCC
fall below V
, the device terminates an access in progress and resets the device address
RST
counter. Inputs to the device will not be recognized at this time to prevent erroneous data
from being written to the device from a an out-of-tolerance system.
The power input will also be switched from the V
below the battery back-up switchover voltage (V
will be maintained by the battery supply. As system power returns and V
the battery is disconnected, and the power supply is switched to external V
Write protection continues until V
reaches V
CC
pin to the external battery when VCC falls
CC
= V
SO
(min) plus t
PFD
). At this time the clock registers
RST
(min). For more
REC
rises above VSO,
CC
.
CC
information on battery storage life refer to application note AN1012.
12/51 Doc ID 12615 Rev 6
M41T93 Operation
2.1 SPI bus characteristics
The serial peripheral interface (SPI) bus is intended for synchronous communication
between different ICs. It consists of four signal lines: serial data input (SDI), serial data
output (SDO), serial clock (SCL) and a chip enable (E
By definition a device that gives out a message is called “transmitter,” the receiving device
that gets the message is called “receiver.” The device that controls the message is called
“master.” The devices that are controlled by the master are called “slaves.”
The E
input is used to initiate and terminate a data transfer. The SCL input is used to
synchronize data transfer between the master (micro) and the slave (M41T93) device.
The SCL input, which is generated by the microcontroller, is active only during address and
data transfer to any device on the SPI bus (see Figure 5 on page 10).
The M41T93 can be driven by a microcontroller with its SPI peripheral running in only mode
0: (CPOL, CPHA) = (0,0).
For this mode, input data (SDI) is latched in by the low-to-high transition of clock SCL, and
output data (SDO) is shifted out on the high-to-low transition of SCL (see Ta bl e 2 and
Figure 6 on page 10).
There is one clock for each bit transferred. Address and data bits are transferred in groups
of eight bits. Due to memory size the second most significant address bit is a “don’t care”
(address bit 6).
).
2.2 READ and WRITE cycles
Address and data are shifted MSB first into the serial data input (SDI) and out of the serial
data output (SDO). Any data transfer considers the first bit to define whether a READ or
WRITE will occur. This is followed by seven bits defining the address to be read or written.
Data is transferred out of the SDO for a READ operation and into the SDI for a WRITE
operation. The address is always the second through the eighth bit written after the enable
(E
) pin goes low. If the first bit is a '1,' one or more WRITE cycles will occur. If the first bit is a
'0,' one or more READ cycles will occur (see Figure 7 and Figure 8 on page 14).
Data transfers can occur one byte at a time or in multiple byte burst mode, during which the
address pointer will be automatically incremented. For a single byte transfer, one byte is
read or written and then E
that E
continue to remain low. Under this condition, the address pointer will continue to
increment as stated previously. Incrementing will continue until the device is deselected by
taking E
The system-to-user transfer of clock data will be halted whenever the address being read is
a clock address (00h to 07h). Although the clock continues to maintain the correct time, this
will prevent updates of time and date during either a READ or WRITE of these address
locations by the user. The update will resume either due to a deselect condition or when the
pointer increments to an non-clock or RAM address (08h to 1Fh).
Note: This is true both in READ and WRITE mode.
high. The address will wrap to 00h after incrementing to 3Fh.
is driven high. For a multiple byte transfer all that is required is
Doc ID 12615 Rev 6 13/51
Operation M41T93
Figure 7. READ mode sequence
E
7
SCL
1
6
5
3
4
2
0
9
8
12 13
14
15 16
17 22
7 BIT ADDRESS
3
4
6
5
HIGH IMPEDANCE
201
SDI
SDO
W/R BIT
7
MSB
Figure 8. WRITE mode sequence
E
SCL
SDI
W/R BIT
7
MSB
0
1
665
2
7 BIT ADDR
443321
5
DATA OUT
(BYTE 1)
3
201
5
6
9
10
DATA BYTE
4
4321
7
MSB
7
8
0
7
65
MSB
7
MSB
15
0
7
6
DATA OUT
(BYTE 2)
4
5
3
201
AI04635
SDO
HIGH IMPEDANCE
14/51 Doc ID 12615 Rev 6
AI04636
M41T93 Operation
2.3 Data retention and battery switchover (VSO = V
Once VCC falls below the switchover voltage (VSO = V
switches over to the battery and powers down into an ultra low current mode of operation to
preserve battery life. If V
from V
CC
to V
when VCC drops below V
BAT
clock registers and user RAM will be maintained by the attached battery supply.
When it is powered back up, the device switches back from battery to V
hysteresis. When V
rises above V
CC
on battery storage life refer to application note AN1012.
2.4 Power-on reset (t
The M41T93 continuously monitors VCC. When VCC falls to the power fail detect trip point,
the RST
typical) after V
Note: The t
below V
RST
The RST
chosen to control the rise time.
output pulls low (open drain) and remains low after power-up for t
rises above V
CC
period does not affect the RTC operation. Write protect only occurs when VCC is
rec
. When VCC rises above V
RST
output is affected by the t
pin is an open drain output and an appropriate pull-up resistor to VCC should be
is less than, or greater than V
BAT
rec
)
RST
rec
RST
(max).
RST
period.
(see Figure 19 on page 41). At this time the
RST
, it will recognize the inputs. For more information
, the RTC will be selectable immediately. Only the
), the device automatically
RST
, the device power is switched
RST
RST
at VSO +
CC
rec
)
(210ms
Doc ID 12615 Rev 6 15/51
Clock operation M41T93
3 Clock operation
The M41T93 is driven by a quartz-controlled oscillator with a nominal frequency of
32.768 kHz. The accuracy of the real-time clock depends on the frequency of the quartz
crystal that is used as the time-base for the RTC.
The 8-byte clock register (see Table 3 on page 20) is used to both set the clock and to read
the date and time from the clock, in binary coded decimal format. Tenths/hundredths of
seconds, seconds, minutes, and hours are contained within the first four registers.
Bit D7 of register 01h contains the STOP bit (ST). Setting this bit to a '1' will cause the
oscillator to stop. When reset to a '0' the oscillator restarts within one second (typical).
Note: Upon initial power-up, the user should set the ST bit to a '1,' then immediately reset the ST
bit to '0.' This provides an additional “kick-start” to the oscillator circuit.
Bits D6 and D7 of clock register 03h (century/ hours register) contain the CENTURY bit 0
(CB0) and CENTURY bit 1 (CB1). Bits D0 through D2 of register 04h contain the day (day of
week). Registers 05h, 06h, and 07h contain the date (day of month), month, and years. The
ninth clock register is the digital calibration register, while the analog calibration register is
found at address 12h (these are both described in the clock calibration section). Bit D7 of
register 09h (watchdog register) contains the oscillator fail interrupt enable bit (OFIE). When
the user sets this bit to '1,' any condition which sets the oscillator fail bit (OF) (see Oscillator
fail detection on page 35) will also generate an interrupt output.
Note: A WRITE to ANY location within the first eight bytes of the clock register (00h-07h),
including the ST bit and CB0-CB1 bits will result in an update of the system clock and a
reset of the divider chain. This could result in an inadvertent change of the current time.
These non-clock related bits should be written prior to setting the clock, and remain
unchanged until such time as a new clock time is also written.
The eight clock registers may be read one byte at a time, or in a sequential block. Provision
has been made to assure that a clock update does not occur while any of the eight clock
addresses are being read. If a clock address is being read, an update of the clock registers
will be halted. This will prevent a transition of data during the READ.
16/51 Doc ID 12615 Rev 6
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