Serial SPI bus real-time clock with battery switchover
Features
■ Ultra-low battery supply current of 365 nA
■ Factory calibrated accuracy ±5 ppm
guaranteed after 2 reflows (SOX18)
– Much better accuracies achievable using
built-in programmable analog and digital
calibration circuits
■ 2.0 V to 5.5 V clock operating voltage
■ Counters for tenths/hundredths of seconds,
seconds, minutes, hours, day, date, month,
year, and century
■ Automatic switchover and reset output circuitry
(fixed reference)
–M41T93S: V
(2.85 V ≤ V
–M41T93R: V
(2.55 V ≤ V
–M41T93Z: V
(2.25 V ≤ V
■ Compatible with SPI bus serial interface
(supports SPI mode 0 [CPOL = 0, CPHA = 0])
■ Programmable alarm with interrupt function
(valid even during battery backup mode)
■ Optional 2
■ Square wave output (defaults to 32 KHz on
nd
power-up)
■ RESET (RST) output
■ Watchdog timer
■ Programmable 8-bit counter/timer
■ 7 bytes of battery-backed user SRAM
■ Battery low flag
■ Low operating current of 80 µA
■ Oscillator stop detection
■ Battery or SuperCap™ backup
■ Operating temperature of –40 °C to +85 °C
= 3.0 V to 5.5 V
CC
≤ 3.00 V)
RST
= 2.7 V to 5.5 V
CC
≤ 2.70 V)
RST
= 2.38 V to 5.50 V
CC
≤ 2.38 V)
RST
programmable alarm available
M41T93
QFN16, 4 mm x 4 mm
18
1
SOX18 (18-pin, 300 mil SOIC
with embedded crystal)
■ Package options include:
– a 16-lead QFN or an 18-lead embedded
crystal SOIC
■ RoHS compliance: lead-free components are
compliant with the RoHS directive
October 2011 Doc ID 12615 Rev 6 1/51
www.st.com
1
Contents M41T93
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 SPI signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1.1 Serial data output (SDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1.2 Serial data input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1.3 Serial clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1.4 Chip enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 SPI bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2 READ and WRITE cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3 Data retention and battery switchover (V
2.4 Power-on reset (t
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
rec
SO
= V
) . . . . . . . . . . . . . . . . 15
RST
3 Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 Clock data coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1.1 Example of incoherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1.2 Accessing the device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2 Halt bit (HT) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.1 Power-down time stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3 Real-time clock accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4 Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4.1 Digital calibration (periodic counter correction) . . . . . . . . . . . . . . . . . . . 22
3.4.2 Analog calibration (programmable load capacitance) . . . . . . . . . . . . . . 24
3.5 Setting the alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.6 Optional second programmable alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.7 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.8 8-bit (countdown) timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.8.1 TI/TP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.8.2 TF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.8.3 TIE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.8.4 TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.8.5 TD1/0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.9 Square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2/51 Doc ID 12615 Rev 6
M41T93 Contents
3.10 Battery low warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.11 Century bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.12 Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.13 Oscillator fail detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.14 Oscillator fail interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.15 Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.16 OTP bit operation (SOX18 package only) . . . . . . . . . . . . . . . . . . . . . . . . 36
4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Doc ID 12615 Rev 6 3/51
List of tables M41T93
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Function table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Clock/control register map (32 bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 4. Digital calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 5. Analog calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 6. Alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 7. Timer control register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 8. Interrupt operation (bit TI
Table 9. Timer source clock frequency selection (244.1 µs to 4.25 hrs). . . . . . . . . . . . . . . . . . . . . . 32
Table 10. Timer countdown value register bits (addr 11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 11. Square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 12. Century bits examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 13. Initial power-on default values (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 14. Initial power-up default values (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 15. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 16. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 17. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 18. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 19. Crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 20. Oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 21. Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 22. AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 23. QFN16 – 16-lead, quad, flat package, no lead, 4 x 4 mm body, mech. data . . . . . . . . . . . 45
Table 24. SOX18 – 18-lead plastic SO, 300 mils, embedded crystal, pkg. mech. data . . . . . . . . . . . 47
Table 25. Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 26. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
/TP = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4/51 Doc ID 12615 Rev 6
M41T93 List of figures
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. QFN16 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. SOX18 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. Data and clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. WRITE mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. Clock data coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 10. Internal load capacitance adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 11. Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 12. Clock accuracy vs. on-chip load capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 13. Clock divider chain and calibration circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 14. Crystal isolation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 15. Alarm interrupt reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 16. Backup mode alarm waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 17. Measurement AC I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 18. I
Figure 19. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 20. Input timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 21. Output timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 22. QFN16 – 16-lead, quad, flat package, no lead, 4 x 4 mm body size, outline . . . . . . . . . . . 45
Figure 23. QFN16 – 16-lead, quad, flat, no lead, 4 x 4 mm, recommended footprint . . . . . . . . . . . . . 46
Figure 24. 32 KHz crystal + QFN16 vs. VSOJ20 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 25. SOX18 – 18-lead plastic small outline, 300 mils, embedded crystal . . . . . . . . . . . . . . . . . 47
vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
CC2
Doc ID 12615 Rev 6 5/51
Description M41T93
1 Description
The M41T93 is a low-power serial SPI bus real-time clock with a built-in 32.768 kHz
oscillator (external crystal-controlled for the QFN16 package, and embedded crystal for the
SOX18 package). Eight bytes of the register map are used for the clock/calendar function
and are configured in binary coded decimal (BCD) format. An additional 17 bytes of the
register map provide status/control of the two alarms, watchdog, 8-bit counter, and square
wave functions. An additional seven bytes are made available as user SRAM.
Addresses and data are transferred serially via a serial SPI bus-compatible interface. The
built-in address register is incremented automatically after each WRITE or READ data byte.
The M41T93 has a built-in power sense circuit which detects power failures and
automatically switches to the battery supply when a power failure occurs. The energy
needed to sustain the clock operations can be supplied by a small lithium button battery
when a power failure occurs.
Functions available to the user include a non-volatile, time-of-day clock/calendar, alarm
interrupt, watchdog timer, programmable 8-bit counter, and square wave outputs. The eight
clock address locations contain the century, year, month, date, day, hour, minute, second,
and tenths/hundredths of a second in 24-hour BCD format. Corrections for 28, 29 (leap
year), 30, and 31 day months are made automatically. The M41T93 is supplied in either a
QFN16 or an SOX18, 300 mil SOIC which includes an embedded 32 KHz crystal. The
SOX18 package requires only a user-supplied battery to provide non-volatile operation.
6/51 Doc ID 12615 Rev 6
M41T93 Description
Figure 1. Logic diagram
V
V
BAT
CC
(1)
1. For QFN16 package only
2. Defaults to 32 KHz on power-up
3. Open drain
Table 1. Signal names
Symbol Description
(1)
XI
(1)
XO
/FT/OUT Interrupt /frequency test/output driver (open drain)
IRQ
(2)
SQW
RST
E
32 KHz oscillator input
32 KHz oscillator output
32 KHz programmable square wave output
Power-on reset output (open drain)
Chip enable
XO
SCL
XI
SDI
(1)
E
V
SS
(2)
SQW
IRQ/OUT/FT
(3)
RST
SDO
(3)
AI11818
SDI Serial data address input
SDO Serial data address output
SCL Serial clock input
V
BAT
(3)
DU
V
CC
V
SS
1. For QFN16 package only
2. Defaults to 32 KHz on power-up
3. Do not use (must be tied to VCC)
Battery supply voltage (Tie V
Do not use
Supply voltage
Ground
to VSS if no battery is connected.)
BAT
Doc ID 12615 Rev 6 7/51
Description M41T93
Figure 2. QFN16 connections
CC
15
V
XI
14
13
E
12
11
SDO
IRQ/FT/OUT
(1)
RST
NC
(1)
XO
16
1
2
M41T93
SQW
NC
(2)
3
4
6
5
BAT
V
7
SS
NC
V
SCL
10
9
SDI
8
NC
AI11819
1. Open drain output
2. Defaults to 32 KHz on power-up
Figure 3. SOX18 connections
NF
NF
RST
DU
SQW
V
V
NC
NC
BAT
SS
1
(1)
2
(1)
3
4
(2)
5
6
7
M41T93
(3)
(4)
8
9
18
17
16
15
14
13
12
11
10
NC
(1)
NF
(1)
NF
V
CC
E
SDO
IRQ/FT/OUT
SCL
SDI
(2)
1. NF pins must be tied to VSS. Pins 2 and 3, and 16 and 17 are internally shorted together.
2. Open drain output
3. Do not use (must be tied to V
CC
)
4. Defaults to 32 KHz on power-up
AI11820
8/51 Doc ID 12615 Rev 6
M41T93 Description
Figure 4. Block diagram
REAL TIME CLOCK
CALENDAR
CRYSTAL
SDI
SCL
SDO
V
CC
V
E
BAT
V
RST/VSO
XI
OSCILLATOR
XO
INTERFACE
COMPARE
(2)
32KHz
SPI
WRITE
PROTECT
VCC < V
RST
OSCILLATOR FAIL
CIRCUIT
ALARM1
ALARM2
WATCHDOG
FREQUENCY TEST
OUTPUT DRIVER
8-BIT COUNTER
SQUARE WAVE
8 BITS OF OTP
USER SRAM (7 Bytes)
OFIE
A1IE
FT
OUT
TIE
SQWE
INTERNAL
POWER
t
rec
TIMER
IRQ/FT/OUT
SQW
(1)
RST
(1)
AI11821
1. Open drain output
2. V
= VSO = 2.93 V (S), 2.63 V (R), and 2.32 V (Z)
RST
Doc ID 12615 Rev 6 9/51
Description M41T93
Figure 5. Hardware hookup
V
CC
MCU
M41T93
V
CC
XI
XO
V
V
BAT
SS
IRQ/FT/OUT
RST
SQW
(1)
(1)
SCL
SDO
SDI
E
1. Open drain output
2. CPOL (clock polarity) and CPHA (clock phase) are bits that may be set in the SPI control register of the MCU.
Table 2. Function table
(ST6, ST7, ST9, ST10, Others)
V
CC
INT
Reset Input
SCL
(2)
SDI
SDO
CS
32KHz CLKIN
SPI Interface with
(CPOL = 0, CPHA = 0)
AI11822
Mode E SCL SDI SDO
Disable reset H Input disabled Input disabled High Z
WRITE L
AI04630
READ L
AI04631
Data bit latch High Z
X Next data bit shift
1. SDO remains at High Z until eight bits of data are ready to be shifted out during a READ.
Figure 6. Data and clock timing
CPOL
CPHA
0
0
C
SDI
SDO
MSB
MSB
LSB
LSB
(1)
Note: Supports SPI mode 0 (CPOL = 0, CPHA = 0) only.
10/51 Doc ID 12615 Rev 6
AI04632
M41T93 Description
1.1 SPI signal description
1.1.1 Serial data output (SDO)
The output pin is used to transfer data serially out of the memory. Data is shifted out on the
falling edge of the serial clock.
1.1.2 Serial data input (SDI)
The input pin is used to transfer data serially into the device. Instructions, addresses, and
the data to be written, are each received this way. Input is latched on the rising edge of the
serial clock.
1.1.3 Serial clock (SCL)
The serial clock provides the timing for the serial interface (as shown in Figure 20 on
page 42 and Figure 21 on page 42). The W/R bit, addresses, or data are latched, from the
input pin, on the rising edge of the clock input. The output data on the SDO pin changes
state after the falling edge of the clock input.
The M41T93 can be driven by a microcontroller with its SPI peripheral running in only mode
0: (CPOL, CPHA) = (0,0).
For this mode, input data (SDI) is latched in by the low-to-high transition of clock SCL, and
output data (SDO) is shifted out on the high-to-low transition of SCL (see Tab l e 2 o n
page 10 and Figure 6 on page 10).
1.1.4 Chip enable (E)
When E is high, the memory device is deselected, and the SDO output pin is held in its high
impedance state.
After power-on, a high-to-low transition on E
is required prior to the start of any operation.
Doc ID 12615 Rev 6 11/51
Operation M41T93
2 Operation
The M41T93 clock operates as a slave device on the SPI serial bus. Each memory device is
accessed by a simple serial interface that is SPI bus-compatible. The bus signals are SCL,
SDI, and SDO (see Table 1 on page 7 and Figure 5 on page 10). The device is selected
when the chip enable input (E
serially in and out of the chip. The most significant bit is presented first, with the data input
(SDI) sampled on the first rising edge of the clock (SCL) after the chip enable (E
The 32 bytes contained in the device can then be accessed sequentially in the following
order:
1
Tenths/hundredths of a second register
2
Seconds register
3
Minutes register
4
Century/hours register
5
Day register
6
Date register
) is held low. All instructions, addresses and data are shifted
) goes low.
7
Month register
8
Year register
9
Digital calibration register
10
Watchdog register
11-15
21-25
26-32
Alarm1 registers
16
Flags register
17
Timer value register
18
Timer control register
19
Analog calibration register
20
Square wave register
Alarm2 registers
User RAM
The M41T93 clock continually monitors VCC for an out-of tolerance condition. Should VCC
fall below V
, the device terminates an access in progress and resets the device address
RST
counter. Inputs to the device will not be recognized at this time to prevent erroneous data
from being written to the device from a an out-of-tolerance system.
The power input will also be switched from the V
below the battery back-up switchover voltage (V
will be maintained by the battery supply. As system power returns and V
the battery is disconnected, and the power supply is switched to external V
Write protection continues until V
reaches V
CC
pin to the external battery when VCC falls
CC
= V
SO
(min) plus t
PFD
). At this time the clock registers
RST
(min). For more
REC
rises above VSO,
CC
.
CC
information on battery storage life refer to application note AN1012.
12/51 Doc ID 12615 Rev 6
M41T93 Operation
2.1 SPI bus characteristics
The serial peripheral interface (SPI) bus is intended for synchronous communication
between different ICs. It consists of four signal lines: serial data input (SDI), serial data
output (SDO), serial clock (SCL) and a chip enable (E
By definition a device that gives out a message is called “transmitter,” the receiving device
that gets the message is called “receiver.” The device that controls the message is called
“master.” The devices that are controlled by the master are called “slaves.”
The E
input is used to initiate and terminate a data transfer. The SCL input is used to
synchronize data transfer between the master (micro) and the slave (M41T93) device.
The SCL input, which is generated by the microcontroller, is active only during address and
data transfer to any device on the SPI bus (see Figure 5 on page 10).
The M41T93 can be driven by a microcontroller with its SPI peripheral running in only mode
0: (CPOL, CPHA) = (0,0).
For this mode, input data (SDI) is latched in by the low-to-high transition of clock SCL, and
output data (SDO) is shifted out on the high-to-low transition of SCL (see Ta bl e 2 and
Figure 6 on page 10).
There is one clock for each bit transferred. Address and data bits are transferred in groups
of eight bits. Due to memory size the second most significant address bit is a “don’t care”
(address bit 6).
).
2.2 READ and WRITE cycles
Address and data are shifted MSB first into the serial data input (SDI) and out of the serial
data output (SDO). Any data transfer considers the first bit to define whether a READ or
WRITE will occur. This is followed by seven bits defining the address to be read or written.
Data is transferred out of the SDO for a READ operation and into the SDI for a WRITE
operation. The address is always the second through the eighth bit written after the enable
(E
) pin goes low. If the first bit is a '1,' one or more WRITE cycles will occur. If the first bit is a
'0,' one or more READ cycles will occur (see Figure 7 and Figure 8 on page 14).
Data transfers can occur one byte at a time or in multiple byte burst mode, during which the
address pointer will be automatically incremented. For a single byte transfer, one byte is
read or written and then E
that E
continue to remain low. Under this condition, the address pointer will continue to
increment as stated previously. Incrementing will continue until the device is deselected by
taking E
The system-to-user transfer of clock data will be halted whenever the address being read is
a clock address (00h to 07h). Although the clock continues to maintain the correct time, this
will prevent updates of time and date during either a READ or WRITE of these address
locations by the user. The update will resume either due to a deselect condition or when the
pointer increments to an non-clock or RAM address (08h to 1Fh).
Note: This is true both in READ and WRITE mode.
high. The address will wrap to 00h after incrementing to 3Fh.
is driven high. For a multiple byte transfer all that is required is
Doc ID 12615 Rev 6 13/51
Operation M41T93
Figure 7. READ mode sequence
E
7
SCL
1
6
5
3
4
2
0
9
8
12 13
14
15 16
17 22
7 BIT ADDRESS
3
4
6
5
HIGH IMPEDANCE
201
SDI
SDO
W/R BIT
7
MSB
Figure 8. WRITE mode sequence
E
SCL
SDI
W/R BIT
7
MSB
0
1
665
2
7 BIT ADDR
443321
5
DATA OUT
(BYTE 1)
3
201
5
6
9
10
DATA BYTE
4
4321
7
MSB
7
8
0
7
65
MSB
7
MSB
15
0
7
6
DATA OUT
(BYTE 2)
4
5
3
201
AI04635
SDO
HIGH IMPEDANCE
14/51 Doc ID 12615 Rev 6
AI04636
M41T93 Operation
2.3 Data retention and battery switchover (VSO = V
Once VCC falls below the switchover voltage (VSO = V
switches over to the battery and powers down into an ultra low current mode of operation to
preserve battery life. If V
from V
CC
to V
when VCC drops below V
BAT
clock registers and user RAM will be maintained by the attached battery supply.
When it is powered back up, the device switches back from battery to V
hysteresis. When V
rises above V
CC
on battery storage life refer to application note AN1012.
2.4 Power-on reset (t
The M41T93 continuously monitors VCC. When VCC falls to the power fail detect trip point,
the RST
typical) after V
Note: The t
below V
RST
The RST
chosen to control the rise time.
output pulls low (open drain) and remains low after power-up for t
rises above V
CC
period does not affect the RTC operation. Write protect only occurs when VCC is
rec
. When VCC rises above V
RST
output is affected by the t
pin is an open drain output and an appropriate pull-up resistor to VCC should be
is less than, or greater than V
BAT
rec
)
RST
rec
RST
(max).
RST
period.
(see Figure 19 on page 41). At this time the
RST
, it will recognize the inputs. For more information
, the RTC will be selectable immediately. Only the
), the device automatically
RST
, the device power is switched
RST
RST
at VSO +
CC
rec
)
(210ms
Doc ID 12615 Rev 6 15/51
Clock operation M41T93
3 Clock operation
The M41T93 is driven by a quartz-controlled oscillator with a nominal frequency of
32.768 kHz. The accuracy of the real-time clock depends on the frequency of the quartz
crystal that is used as the time-base for the RTC.
The 8-byte clock register (see Table 3 on page 20) is used to both set the clock and to read
the date and time from the clock, in binary coded decimal format. Tenths/hundredths of
seconds, seconds, minutes, and hours are contained within the first four registers.
Bit D7 of register 01h contains the STOP bit (ST). Setting this bit to a '1' will cause the
oscillator to stop. When reset to a '0' the oscillator restarts within one second (typical).
Note: Upon initial power-up, the user should set the ST bit to a '1,' then immediately reset the ST
bit to '0.' This provides an additional “kick-start” to the oscillator circuit.
Bits D6 and D7 of clock register 03h (century/ hours register) contain the CENTURY bit 0
(CB0) and CENTURY bit 1 (CB1). Bits D0 through D2 of register 04h contain the day (day of
week). Registers 05h, 06h, and 07h contain the date (day of month), month, and years. The
ninth clock register is the digital calibration register, while the analog calibration register is
found at address 12h (these are both described in the clock calibration section). Bit D7 of
register 09h (watchdog register) contains the oscillator fail interrupt enable bit (OFIE). When
the user sets this bit to '1,' any condition which sets the oscillator fail bit (OF) (see Oscillator
fail detection on page 35) will also generate an interrupt output.
Note: A WRITE to ANY location within the first eight bytes of the clock register (00h-07h),
including the ST bit and CB0-CB1 bits will result in an update of the system clock and a
reset of the divider chain. This could result in an inadvertent change of the current time.
These non-clock related bits should be written prior to setting the clock, and remain
unchanged until such time as a new clock time is also written.
The eight clock registers may be read one byte at a time, or in a sequential block. Provision
has been made to assure that a clock update does not occur while any of the eight clock
addresses are being read. If a clock address is being read, an update of the clock registers
will be halted. This will prevent a transition of data during the READ.
16/51 Doc ID 12615 Rev 6
M41T93 Clock operation
3.1 Clock data coherency
In order to synchronize the data during reads and writes of the real-time clock device, a set
of buffer transfer registers resides between the SPI serial interface on the user side, and the
clock/calendar counters in the part. While the read/write data is transferred in and out of the
device one bit at a time to the user, the transfers between the buffer registers and counters
occur such that all the bits are copied simultaneously. This keeps the data coherent and
ensures that none of the counters are incremented while the data is being transferred.
Figure 9. Clock data coherency
E
SDI
SCL
SDO
AT START OF READ OR WRITE,
DATA IN COUNTERS IS COPIED TO
BUFFER/TRANSFER REGISTERS.
READ / WRITE
BUFFER-TRANSFER
REGISTERS
SPI
INTERFACE
SECONDS
MINUTES
HOURS
DAY-OF-WEEK
DATE
MONTHS
YEARS
CENTURIES
NON-CLOCK
REGISTERS
SQUAREWAVE
CALIBRATION
ALARM / HALT
WATCHDOG
32KHz
OSC
DIVIDE BY 32768
1 Hz
COUNTER
COUNTER
COUNTER
COUNTER
COUNTER
COUNTER
COUNTER
AFTER A WRITE, DATA IS TRANSFERRED
FROM BUFFERS TO COUNTERS
HALT BIT SET AT POWER-DOWN
COUNTER
RTC
COUNTERS
3.1.1 Example of incoherency
Without having the intervening buffer/transfer registers, if the user began directly reading the
counters at 23:59:59, a read of the seconds register would return 59 seconds. After the
address pointer incremented, the next read would return 59 minutes. Then the next read
should return 23 hours, but if the clock happened to increment between the reads, the user
would see 00 hours. When the time was re-assembled, it would appear as 00:59:59, and
thus be incorrect by one hour.
By using the buffer/transfer registers to hold a copy of the time, the user is able to read the
entire set of registers without any values changing during the read.
Similarly, when the application needs to change the time in the counters, it is necessary that
all the counters be loaded simultaneously. Thus, the user writes sequentially to the various
buffer/transfer registers, then they are copied to the counters in a single transfer thereby
coherently loading the counters.
Doc ID 12615 Rev 6 17/51
Clock operation M41T93
3.1.2 Accessing the device
The M41T93 is comprised of 32 addresses which provide access to registers for time and
date, digital and analog calibration, two alarms, watchdog, flags, timer, squarewave and
NVRAM. The clock and alarm parameters are in binary coded decimal (BCD) format. The
calibration, timer, watchdog, and squarewave parameters are in a binary format.
In the case of the M41T93, at the start of each read or write serial transfer, the counters are
automatically copied to the buffer registers. In the event of a write to any register in the
range 0-7, at the end of the serial transfer, the buffer registers are copied back into the
counters thus revising the date/time. Any of the eight clock registers (addresses 0-7) not
updated during the transfer will have its old value written back into the counters. For
example, if only the seconds value is revised, the other seven counters will end up with the
same values they had at the start of the serial transfer.
However, writes which do not affect the clock registers - that is, a write only to the non-clock
registers (addresses 0x08 to 0x1F) - will not cause the buffer registers to be copied back to
the counters. The counters are only updated if a register in the range 0-7 was written.
Whenever the RTC registers (addresses 0-7) are written, the divider chain from the
oscillator is reset.
3.2 Halt bit (HT) operation
When the part is powered down into battery backup mode, a control bit, called the Halt or
HT bit, is set automatically. This inhibits any subsequent transfers from the counters to the
buffer registers thereby freezing in the buffer registers the time/date of the last access of the
part.
Repeated reads of the clock registers will return the same value. After the HT bit is cleared,
by writing bit 6 of address 0x0C to 0, the next read of the RTC will return the present time.
Note: Writes to the RTC registers (addresses 0-7) with the HT bit set can cause time corruption.
Since the buffer registers contain the time of the last access prior to the HT bit being set, any
write in the address range 0-7 will result in the time of the last access being copied back into
the counters.
Example: The last access was November 17, 2009, at 16:15:07.77. The system later
powered down thus setting the HT bit and freezing that value in the buffers. Later, on
December 18, 2009, at 03:22:43.35, the system is powered up and the user writes the
seconds to 46 without first clearing the HT bit. At the end of the serial transfer, the old
time/date, with the seconds modified to 46, will be written back into the clock registers
thereby corrupting them. The new, wrong time will be November 17, 2009, at 16:15:46.77.
This makes it appear the RTC lost time during the power outage.
Thus, at power-up, the user should always clear the HT bit (write bit 6 to 0 at address 0x0C)
before writing to any address in the range 0-7.
A typical power-up flow is to read the time of last access, then clear the HT bit, then read the
current time.
18/51 Doc ID 12615 Rev 6
M41T93 Clock operation
3.2.1 Power-down time stamp
Some applications may need to determine the amount of time spent in backup mode. That
can be calculated if the time of power-down and the time of power-up are known. The latter
is straightforward to obtain. But the time of power-down is only available if an access
occurred just prior to power-down. That is, if there was an access of the device just prior to
power-down, the time of the access would have been frozen in the buffer transfer registers
and thus the approximate time of power-down could be obtained.
If an application requires the time of power-down, the best way to implement it is to set up
the software to do frequent reads of the clock, such as once every 1 or 5 seconds. That
way, at power-up, the buffer-transfer registers will contain a time value within 1 (or 5)
seconds of the actual time of power-down.
Doc ID 12615 Rev 6 19/51
Clock operation M41T93
Table 3. Clock/control register map (32 bytes)
Addr
D7 D6 D5 D4 D3 D2 D1 D0
00h 0.1 seconds 0.01 seconds Seconds 00-99
01h ST 10 seconds Seconds Seconds 00-59
02h 0 10 minutes Minutes Minutes 00-59
03h CB1 CB0 10 hours Hours (24-hour format) Century/hours 0-3/00-23
04h 0 0 0 0 0 Day of week Day 01-7
05h 0 0 10 date Date: day of month Date 01-31
06h 0 0 0 10M Month Month 01-12
07h 10 Years Year Year 00-99
08h OUT FT DCS DC4 DC3 DC2 DC1 DC0 Digital calibration
09h OFIE BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog
0Ah A1IE SQWE ABE Al1 10M Alarm1month Al1 month 01-12
0Bh RPT14 RPT15 AI1 10 date Alarm1 date Al1 date 01-31
0Ch RPT13 HT AI1 10 hour Alarm1 hour Al1 hour 00-23
0Dh RPT12 Alarm1 10 minutes Alarm1 minutes Al1 min 00-59
0Eh RPT11 Alarm1 10 seconds Alarm1 seconds Al1 sec 00-59
(1)
0Fh WDF AF1 AF2
BL TF OF 0 0 Flags
10h Timer countdown value Timer value
11h TE TI
/TP TIE 0 0 0 TD1 TD0 Timer control
12h ACS AC6 AC5 AC4 AC3 AC2 AC1 AC0
13h RS3 RS2 RS1 RS0 0 0 AL2E OTP SQW
14h 0 0 0 Al2 10M Alarm2 month SRAM/Al2 month 01-12
15h RPT24 RPT25 AI2 10 date Alarm2 month SRAM/Al2 date 01-31
16h RPT23 0 AI2 10 hour Alarm2 date SRAM/Al2 hour 00-23
17h RPT22 Alarm2 10 minutes Alarm2 minutes SRAM/Al2 min 00-59
18h RPT21 Alarm2 10 seconds Alarm2 seconds SRAM/Al2 sec 00-59
19h-
1Fh
1. AF2 will always read ‘0’ if the AL2E bit is set to ‘0’.
User SRAM (7 bytes) SRAM
Function/range BCD format
Analog
calibration
0 = Must be set to zero OFIE = Oscillator fail interrupt enable
ABE = Alarm in battery backup enable bit OTP = OTP control bit
A1IE = Alarm1 interrupt enable bit RB0-RB2 = Watchdog resolution bits
AC0-AC6 = analog calibration bits RPT11-RPT15 = Alarm 1 repeat mode bits
ACS = analog calibration sign bit RPT21-RPT25 = Alarm 2 repeat mode bits
AF1, AF2 = Alarm flag RS0-RS3 = SQW frequency
AL2E = Alarm 2 enable bit SQWE = Square wave enable
BL = Battery low bit SRAM/ALM2
= SRAM/Alarm 2 bit
BMB0-BMB4 = Watchdog multiplier bits ST = Stop bit
CB0, CB1 = Century bits TD0, TD1 = Timer frequency bits
DC0-DC4 = Digital calibration bits TE = Timer enable bit
DCS = Digital calibration sign bit TF = Timer flag
FT = Frequency test bit TI
/TP = Timer interrupt or pulse
HT = Halt update bit TIE = Timer interrupt enable
OF = Oscillator fail bit WDF = Watchdog flag
OUT= Output level
20/51 Doc ID 12615 Rev 6
M41T93 Clock operation
3.3 Real-time clock accuracy
The M41T93 is driven by a quartz controlled oscillator with a nominal frequency of
32,768 Hz. The accuracy of the real-time clock is dependent upon the accuracy of the
crystal, and the match between the capacitive load of the oscillator circuit and the capacitive
load for which the crystal was trimmed. Temperature also affects the crystal frequency,
causing additional error (see Figure 11 on page 25).
The M41T93 provides the option of clock correction through either manufacturing calibration
or in-application calibration. The total possible compensation is typically –93 ppm to +156
ppm. The two compensation circuits that are available are:
1. An analog calibration register (12h) can be used to adjust internal (on-chip) load
capacitors for oscillator capacitance trimming. The individual load capacitors C
C
(see Figure 10), are selectable from a range of –18 pF to +9.75 pF in steps of
XO
0.25pF. This translates to a calculated compensation of approximately ±30 ppm (see
Analog calibration (programmable load capacitance) on page 24).
2. A digital calibration register (08h) can also be used to adjust the clock counter by
adding or subtracting a pulse at the 512 Hz divider stage. This approach provides
periodic compensation of approximately –63 ppm to +126 ppm (see Digital calibration
(periodic counter correction) on page 22).
Figure 10. Internal load capacitance adjustment
and
XI
XI
XO
C
XI
Crystal Oscillator
C
XO
AI11804
Doc ID 12615 Rev 6 21/51
Clock operation M41T93
3.4 Clock calibration
The M41T93 oscillator is designed for use with a 12.5 pF crystal load capacitance. When
the calibration circuit is properly employed, accuracy improves to better than ±1 ppm at
25 °C.
The M41T93 design provides the following two methods for clock error correction.
3.4.1 Digital calibration (periodic counter correction)
This method employs the use of periodic counter correction by adjusting the ratio of the
100 Hz divider stage to the 512 Hz divider stage. Under normal operation, the 100Hz divider
stage outputs precisely 100 pulses for every 512 pulses of the 512 Hz input stage to provide
the input frequency to the fraction of seconds clock register. By adjusting the number of
512 Hz input pulses used to generate 100 output pulses, the clock can be sped up or slowed
down, as shown in Figure 13 on page 27.
When a non-zero value is loaded into the five calibration bits (DC4 – DC0) found in the
digital calibration register (08h) and the sign bit is ‘1,’ (indicating positive calibration), the
100 Hz stage outputs 100 pulses for every 511 input pulses instead of the normal 512.
Since the 100 pulses are now being output in a shorter window, this has the effect of
speeding up the clock by 1/512 seconds for each second the circuit is active. Similarly, when
the sign bit is ‘0,’ indicating negative calibration, the block outputs 100 pulses for every 513
input pulses. Since the 100 pulses are then being output in a longer window, this has the
effect of slowing down the clock by 1/512 seconds for each second the circuit is active.
The amount of calibration is controlled by using the value in the calibration register (N) to
generate the adjustment in one second increments. This is done for the first N seconds once
every eight minutes for positive calibration, and for N seconds once every sixteen minutes
for negative calibration (see Table 4 on page 23).
For example, if the calibration register is set to '100010,' then the adjustment will occur for
two seconds in every minute. Similarly, if the calibration register is set to '000011,' then the
adjustment will occur for 3 seconds in every alternating minute.
The digital calibration bits (DC4 – DC0) occupy the five lower order bits in the digital
calibration register (08h). These bits can be set to represent any value between 0 and 31 in
binary form. The sixth bit (DCS) is a sign bit; '1' indicates positive calibration, '0' indicates
negative calibration. Calibration occurs within an 8-minute (positive) or 16-minute (negative)
cycle. Therefore, each calibration step has an effect on clock accuracy of +4.068 or –2.034
ppm. Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31 increments
in the calibration byte would represent +10.7 or –5.35 seconds per month, which
corresponds to a total range of +5.5 or –2.75 minutes per month.
Note: 1 The modified pulses are not observable on the frequency test (FT) output, nor will the effect
of the calibration be measurable real-time, due to the periodic nature of the error
compensation.
2 Positive digital calibration is performed on an eight minute cycle, therefore the value in the
calibration register should not be modified more frequently than once every eight minutes for
positive values of calibration. Negative digital calibration is performed on a sixteen minute
cycle, therefore negative values in the calibration register should not be modified more
frequently than once every sixteen minutes.
22/51 Doc ID 12615 Rev 6
M41T93 Clock operation
Table 4. Digital calibration values
Calibration value (binary) Calibration value rounded to the nearest ppm
DC4 – DC0 Negative calibration (DCS = 0) Positive calibration (DCS = 1)
0 (00000) 0 0
1 (00001) –2 4
2 (00010) –4 8
3 (00011) –6 12
4 (00100) –8 16
5 (00101) –10 20
6 (00110) –12 24
7 (00111) –14 28
8 (01000) –16 33
9 (01001) –18 37
10 (01010) –20 41
11 (01011) –22 45
12 (01100) –24 49
13 (01101) –26 53
14 (01110) –28 57
15 (01111) –31 61
16 (10000) –33 65
17 (10001) –35 69
18 (10010) –37 73
19 (10011) –39 77
20 (10100) –41 81
21 (10101) –43 85
22 (10110) –45 90
23 (10111) –47 94
24 (11000) –49 98
25 (11001) –51 102
26 (11010) –53 106
27 (11011) –55 110
28 (11100) –57 114
29 (11101) –59 118
30 (11110) –61 122
31 (11111) –63 126
N N/491520 (per minute) N/245760 (per minute)
Doc ID 12615 Rev 6 23/51
Clock operation M41T93
3.4.2 Analog calibration (programmable load capacitance)
A second method of calibration employs the use of programmable internal load capacitors to
adjust (or trim) the oscillator frequency.
By design, the oscillator is intended to be 0 ppm ± crystal accuracy at room temperature
(25 °C, see Figure 11 on page 25). For a 12.5 pF crystal, the default loading on each side of
the crystal will be 25 pF. For incrementing or decrementing the calibration value,
capacitance will be added or removed in increments of 0.25 pF to each side of the crystal.
Internally, C
C
, connected from the XI and XO pins to ground (see Figure 10 on page 21). The
XO
effective on-chip series load capacitance, C
of the oscillator is changed via two digitally controlled capacitors, CXI and
LOAD
, ranges from 3.5 pF to 17.4 pF, with a
LOAD
nominal value of 12.5 pF (AC0-AC6 = ‘0’).
The effective series load capacitance (C
C
LOAD
) is the combination of CXI and CXO:
LOAD
11C
⁄ 1CXO⁄+()⁄=
XI
Seven analog calibration bits, AC0 to AC6, are provided in order to adjust the on-chip load
capacitance value for frequency compensation of the RTC. Each bit has a different weight
for capacitance adjustment. An analog calibration sign (ACS) bit determines if capacitance
is added (ACS bit = ‘0,’ negative calibration) or removed (ACS bit = ‘1,’ positive calibration).
The majority of the calibration adjustment is positive (i.e. to increase the oscillator frequency
by removing capacitance) due to the typical characteristic of quartz crystals to slow down
due to changes in temperature, but negative calibration is also available.
Since the analog calibration register adjustment is essentially “pulling” the frequency of the
oscillator, the resulting frequency changes will not be linear with incremental capacitance
changes. The equations which govern this mechanism indicate that smaller capacitor values
of analog calibration adjustment will provide larger increments. Thus, the larger values of
analog calibration adjustment will produce smaller incremental frequency changes. These
values typically vary from 6-10 ppm/bit at the low end to <1 ppm/bit at the highest
capacitance settings. The range provided by the analog calibration register adjustment with
a typical surface mount crystal is approximately ±30 ppm around the AC6-AC0 = 0 default
setting because of this property (see Table 5 on page 25).
24/51 Doc ID 12615 Rev 6
M41T93 Clock operation
Figure 11. Crystal accuracy across temperature
Frequency (ppm)
20
0
–20
–40
–60
2
)
O
= 25°C ± 5°C
T
O
2
80–10–20–30–40
AI07888
–80
–100
–120
–140
–160
ΔF
= K x (T – T
F
= –0.036 ppm/°C2 ± 0.006 ppm/°C
K
0 10203040506070
Temperature °C
Table 5. Analog calibration values
Analog
Addr
calibration
value
0 pFx00000 0 025 pF12.5 pF
3 pF000011 0 028 pF14 pF
12h
5 pF000101 0 030 pF15 pF
–7 pF100111 0 018 pF9 pF
9.75 pF
–18 pF
1. C
2. Maximum negative calibration value
3. Maximum positive calibration value
= 1/(1/CXI + 1/CXO)
LOAD
D7 D6 D5 D4 D3 D2 D1 D0
ACS
(2)
(3)
AC6
(16 pF)
(±)
001001 1 134.75 pF17.4 pF
110010 0 0 7 pF3.5 pF
AC5
(8 pF)
AC4
(4 pF)
AC3
(2 pF)
AC2
( 1pF)
AC1
(0.5 pF)
AC0
(0.25 pF)
CXI, CXOC
LOAD
(1)
Doc ID 12615 Rev 6 25/51
Clock operation M41T93
The on-chip capacitance can be calculated as follows:
C
LOAD
AC6 AC0 value– decimal,()0.25pF×[]7pF+=
For example:
C
(12h = x0000000) = 12.5 pF
LOAD
C
(12h =11001000) = 3.5 pF and
LOAD
C
(12h = 00100111) = 17.4 pF
LOAD
The oscillator sees a minimum of 3.5 pF with no programmable load capacitance selected.
Note: These are typical values, and the total load capacitance seen by the crystal will include
approximately 1-2 pF of package and board capacitance in addition to the analog calibration
register value.
Any invalid value of analog calibration will result in the default capacitance of 25 pF.
The combination of analog and digital trimming can give up to –93 to +156 ppm of the total
adjustment.
Figure 12 represents a typical curve of clock ppm adjustment versus the Analog Calibration
value. This curve may vary with different crystals, so it is good practice to evaluate the
crystal to be used with an M41T93 device before establishing the adjustment values for the
application in question.
Figure 12. Clock accuracy vs. on-chip load capacitors
100.0
80.0
60.0
40.0
20.0
PPM ADJUSTMENT
FASTER
DECREASING LOAD CAP.
0.0
SLOWER
-20.0
OFFSET TO
, CXO (pF)
C
XI
NET EQUIV. LOAD
CAP., C
Analog Calibration
LOAD
, (pF)
0xC8 0xBC 0xA8 0x94 0x00 0x14 0x27
Value, AC,
register 0x12
XOXI
Crystal
Oscillator
C
LOAD
C
XO
C
C
XI
XO
*
=
+ C
C
XI
XO
C
XI
On-Chip
INCREASING LOAD CAP.
-5.0-18.0 -15.0 -10.0 0.0 5.0 9.75
103.5 5.0 7.5 12.5 15 17.4
ai13906
26/51 Doc ID 12615 Rev 6
M41T93 Clock operation
Two methods are available for ascertaining how much calibration a given M41T93 may
require:
● The first involves setting the clock, letting it run for a month and comparing it to a known
accurate reference and recording deviation over a fixed period of time. This allows the
designer to give the end user the ability to calibrate the clock as the environment
requires, even if the final product is packaged in a non-user serviceable enclosure. The
designer could provide a simple utility that accesses either or both of the calibration
bytes.
● The second approach is better suited to a manufacturing environment, and involves the
use of the IRQ
/FT/OUT pin. The IRQ/FT/ OUT pin will toggle at 512 Hz when FT and
OUT bits = '1' and ST = '0.' Any deviation from 512 Hz indicates the degree and
direction of oscillator frequency shift at the test temperature. For example, a reading of
512.010124 Hz would indicate a +20 ppm oscillator frequency error, requiring either a
–10 (xx001010) to be loaded into the digital calibration byte, or +6 pF (00011000) into
the analog calibration byte for correction.
Note: Setting or changing the digital calibration byte does not affect the frequency test, square
wave, or watchdog timer frequency, but changing the analog calibration byte DOES affect all
functions derived from the low current oscillator (see Figure 13).
Figure 13. Clock divider chain and calibration circuits
32KHz
512Hz Output
Frequency Test
÷2
C
XI
C
XO
Low Current
Oscillator
÷8
Analog Calibration
Circuitry
÷2
÷2
Digital Calibration Circuitry
÷2
÷2
(divide by 511/512/513)
1Hz Signal
Remainder of
Divider Circuit
Square Wave
Watchdog Timer
8-Bit Timer
Clock
Registers
AI11806a
Doc ID 12615 Rev 6 27/51
Clock operation M41T93
Figure 14. Crystal isolation example
Crystal
Local Grounding
Plane (Layer 2)
XO
XI
V
SS
AI11814
Note: The substrate pad should be tied to V
SS
.
3.5 Setting the alarm clock registers
Address locations 0Ah-0Eh (alarm 1) and 14h-18h (alarm 2) contain the alarm settings.
Either alarm can be configured independently to go off at a prescribed time on a specific
month, date, hour, minute, or second, or repeat every year, month, day, hour, minute, or
second. Bits RPT15–RPT11 and RPT25-RPT21 put the alarms in the repeat mode of
operation. Table6 on page29 shows the possible bit configurations.
Codes not listed in the table default to the once-per-second mode to quickly alert the user of
an incorrect alarm setting. When the clock information matches the alarm clock settings
based on the match criteria defined by RPT15–RPT11 and/or RPT25-RPT21, AF1 (alarm 1
flag) or AF2 (alarm 2 flag) is set. If A1IE (alarm 1 interrupt enable) is set, the alarm condition
activates the IRQ
date registers and to the RPTx5–RPTx1 bits.
Note: If the address pointer is allowed to increment to the flag register address, or the last address
written is “Alarm Seconds,” the address pointer will increment to the flag address, and an
alarm condition will not cause the interrupt/flag to occur until the address pointer is moved to
a different address.
The IRQ
output is cleared by a READ to the flags register (0Fh) as shown in Figure 15. A
subsequent READ of the flags register is necessary to see that the value of the alarm flag
has been reset to '0.'.
/FT/OUT output pin. To disable either of the alarms, write a '0' to the alarm
The IRQ
/FT/OUT pin can also be activated in the battery backup mode (see Figure 16 on
page 29).
28/51 Doc ID 12615 Rev 6
M41T93 Clock operation
3.6 Optional second programmable alarm
When the alarm 2 enable (AL2E) bit (D1 of address 13h) is set to a logic ‘1,’ registers 14h
through 18h provide control for a second programmable alarm which operates in the same
manner as the alarm function described above.
The AL2E bit defaults on initial power-up to a logic ‘0’ (alarm 2 disabled). In this mode, the
five address bytes (14h-18h) function as additional user SRAM, for a total of 12 bytes of
user SRAM.
Figure 15. Alarm interrupt reset waveform
0Fh0Eh 00h
ALARM FLAG BITS (AFx)
IRQ/FT/OUT
Figure 16. Backup mode alarm waveform
V
CC
V
PFD
V
SO
AFx Bits in Flags
Register
IRQ/FT/OUT
Note: ABE and A1IE bits = 1.
Table 6. Alarm repeat modes
RPT5 RPT4 RPT3 RPT2 RPT1 Alarm setting
HIGH-Z
AI11823
trec
HIGH-Z
AI11824
11111 Once per second
11110 Once per minute
11100 Once per hour
11000 Once per day
10000 Once per month
00000 Once per year
Doc ID 12615 Rev 6 29/51
Clock operation M41T93
3.7 Watchdog timer
The watchdog timer can be used to detect an out-of-control microprocessor. The user
programs the watchdog timer by setting the desired amount of time-out into the watchdog
register, address 09h. Bits BMB4-BMB0 store a binary multiplier and the two lower order bits
RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second,
and 11 = 4 seconds. The amount of time-out is then determined to be the multiplication of
the five-bit multiplier value with the resolution. (For example: writing 00001110 in the
watchdog register = 3*1, or 3 seconds). If the processor does not reset the timer within the
specified period, the M41T93 sets the WDF (watchdog flag) and generates a watchdog
interrupt.
The watchdog timer can be reset by having the microprocessor perform a WRITE of the
watchdog register. The time-out period then starts over.
Should the watchdog timer time-out, a value of 00h needs to be written to the watchdog
register in order to clear the IRQ
until it is again programmed correctly. A READ of the flags register will reset the watchdog
flag (bit D7; register 0Fh).
The watchdog function is automatically disabled upon power-up and the watchdog register
is cleared. If the watchdog function is set, the frequency test function is activated, and the
SQWE bit is '0,' the watchdog function prevails and the frequency test function is denied.
/FT/OUT pin. This will also disable the watchdog function
3.8 8-bit (countdown) timer
The timer value register is an 8-bit binary countdown timer. It is enabled and disabled via the
timer control register (11h) TE bit. Other timer properties such as the source clock, or
interrupt generation are also selected in the timer control register (see Tab l e 7 ). For
accurate read back of the countdown value, the serial clock (SCL) must be operating at a
frequency of at least twice the selected timer clock.
The timer control register selects one of four source clock frequencies for the timer (4096,
64, 1, or 1/60 Hz), and enables/disables the timer. The timer counts down from a softwareloaded 8-bit binary value. At the end of every countdown, the timer sets the timer flag (TF)
bit. The TF bit can only be cleared by software. When asserted, the timer flag (TF) can also
be used to generate an interrupt (IRQ
generated as a pulsed signal every countdown period or as a permanently active signal
which follows the condition of TF. The timer interrupt/timer pulse (TI
this mode selection. When reading the timer, the current countdown value is returned.
Table 7. Timer control register map
Addr D7 D6 D5 D4 D3 D2 D1 D0 Function
0Fh WDF AF1 AF2 BL TF OF 0 0 Flags
10h Timer countdown value Timer value
11h TE TI
/TP TIE 0 0 0 TD1 TD0 Timer control
/FT/OUT) on the M41T93. The interrupt may be
/TP) bit is used to control
Note: Bit positions labeled with ‘0’ should always be written with logic '0.'
30/51 Doc ID 12615 Rev 6
M41T93 Clock operation
3.8.1 TI/TP
● TI/TP = 0
IRQ
/FT/OUT is active when TF is logic '1' (subject to the status of the timer interrupt
enable bit (TIE).
● TI/TP = 1
IRQ
/FT/OUT pulses active according to Tab l e 8 (subject to the status of the TIE bit).
Note: If an alarm condition, watchdog time-out, oscillator failure, or OUT = 0 cause IRQ
be asserted low, then IRQ
pulse mode (TI
/TP = 1), clearing the TF bit will not stop the pulses on IRQ/FT/OUT. The
output pulses will only stop if TE, TIE, or TI
Table 8. Interrupt operation (bit TI
Source clock (Hz)
4096 1/8192 1/4096
64 1/128 1/64
1 1/64 1/64
1/60 1/64 1/64
1. TF and IRQ/FT/OUT become active simultaneously.
2. n = loaded countdown timer value. The timer is stopped when n = 0.
/FT/OUT will remain asserted even if TI/TP is set to '1.' When in
/TP are reset to '0.'
/TP = 1)
(1)
IRQ
period(s)
(2)
n
= 1
n > 1
3.8.2 TF
At the end of a timer countdown, TF is set to logic '1.' If both timer and alarm interrupts are
required in the application, the source of the interrupt can be determined by reading the flag
bits. The timer will auto-reload and continue to count down regardless of the state of TF bit
(or TI
/TP bit). The TF bit is cleared by reading the flags register.
/FT/OUT to
3.8.3 TIE
In level mode (TI/TP = 0), when TF is asserted, the interrupt is asserted (if TIE = 1). To clear
the interrupt, the TF bit or the TIE bit must be reset.
3.8.4 TE
● TE = 0
● TE = 1
When the timer register (10h) is set to ‘0,’ the timer is disabled.
The timer is enabled. TE is reset (disabled) on power-down. When re-enabled, the
counter will begin from the same value as when it was disabled.
Doc ID 12615 Rev 6 31/51
Clock operation M41T93
3.8.5 TD1/0
These are the timer source clock frequency selection bits (see Ta bl e 9). These bits
determine the source clock for the countdown timer (see Tab l e 1 0). When not in use, the
TD1 and TD0 bits should be set to ‘11’ (1/60 Hz) for power saving.
Table 9. Timer source clock frequency selection (244.1 µs to 4.25 hrs)
TD1 TD0 Timer source clock frequency (Hz)
0 0 4096 (244.1 µs)
0 1 64 (15.6 ms)
10 1 (1 s)
1 1 1/60 (60 s)
Table 10. Timer countdown value register bits (addr 11h)
Bit Symbol Description
7 - 0 <timer countdown value>
This register holds the loaded countdown value ‘n.’
Countdown period = n / source clock frequency
Note: Writing to the timer register will not reset the TF bit or clear the interrupt.
32/51 Doc ID 12615 Rev 6
M41T93 Clock operation
3.9 Square wave output
The M41T93 offers the user a programmable square wave function which is output on the
SQW pin. RS3-RS0 bits located in 13h establish the square wave output frequency. These
frequencies are listed in Ta bl e 1 1 . Once the selection of the SQW frequency has been
completed, the SQW pin can be turned on and off under software control with the square
wave enable bit (SQWE) located in register 0Ah.
Note: If the SQWE bit is set to '1', and V
squarewave output will be disabled.
Table 11. Square wave output frequency
Square wave bits Square wave
RS3 RS2 RS1 RS0 Frequency Units
0000None–
000132.768kHz
00108.192kHz
00114.096kHz
01002.048kHz
01011.024kHz
0110512Hz
0111256Hz
1000128Hz
100164Hz
101032Hz
101116Hz
11008Hz
11014Hz
falls below the switchover (VSO) voltage, the
CC
11102Hz
11111Hz
Doc ID 12615 Rev 6 33/51
Clock operation M41T93
3.10 Battery low warning
The M41T93 automatically performs battery voltage monitoring upon power-up and at
factory-programmed time intervals of approximately 24 hours. The battery low (BL) bit, bit
D4 of flags register 0Fh, will be asserted if the battery voltage is found to be less than
approximately 2.5 V. The BL bit will remain asserted until completion of battery replacement
and subsequent battery low monitoring tests, either during the next power-up sequence or
the next scheduled 24-hour interval.
If a battery low is generated during a power-up sequence, this indicates that the battery is
below approximately 2.5 volts and may not be able to maintain data integrity. Clock data
should be considered suspect and verified as correct. A fresh battery should be installed.
If a battery low indication is generated during the 24-hour interval check, this indicates that
the battery is near end of life. However, data is not compromised due to the fact that a
nominal V
battery backup mode, the battery should be replaced.
is supplied. In order to insure data integrity during subsequent periods of
CC
The M41T93 only monitors the battery when a nominal V
applications which require extensive durations in the battery backup mode should be
powered-up periodically (at least once every few months) in order for this technique to be
beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon
power-up via a checksum or other technique.
3.11 Century bits
These two bits will increment in a binary fashion at the turn of the century, and handle all
leap years correctly. See Ta bl e 1 2 for additional explanation.
Table 12. Century bits examples
CB0 CB1 Leap Year? Example
00Yes2000
0 1 No 2100
1 0 No 2200
1 1 No 2300
1. Leap year occurs every four years (for years evenly divisible by four), except for years evenly divisible by
100. The only exceptions are those years evenly divisible by 400 (the year 2000 was a leap year, year
2100 is not).
is applied to the device. Thus
CC
(1)
3.12 Output driver pin
When the OFIE bit, A1IE bit, and watchdog register are not set to generate an interrupt, the
IRQ
/FT/OUT pin becomes an output driver that reflects the contents of D7 of register 08h. In
other words, when D7 (OUT bit) is a '0,' then the IRQ
Note: The IRQ
34/51 Doc ID 12615 Rev 6
/FT/OUT pin is an open drain which requires an external pull-up resistor.
/FT/OUT pin will be driven low.
M41T93 Clock operation
3.13 Oscillator fail detection
If the oscillator fail (OF) bit is internally set to a '1,' this indicates that the oscillator has either
stopped, or was stopped for some period of time and can be used to judge the validity of the
clock and date data. This bit will be set to '1' any time the oscillator stops.
In the event the OF bit is found to be set to '1' at any time other than the initial power-up, the
STOP bit (ST) should be written to a '1,' then immediately reset to '0.' This will restart the
oscillator. The following conditions can cause the OF bit to be set:
● The first time power is applied (defaults to a '1' on power-up).
Note: If the OF bit cannot be written to '0' four seconds after the initial power-up, the STOP bit (ST)
should be written to a '1,' then immediately reset to '0.'
● The voltage present on VCC or battery is insufficient to support oscillation
● The ST bit is set to '1.'
● External interference of the crystal
For the M41T93, if the oscillator fail interrupt enable bit (OFIE) is set to a '1,' the
IRQ
/FT/OUT pin will also be activated. The IRQ/FT/OUT output is cleared by resetting the
OFIE or OF bit to '0' (NOT by reading the flag register).
The OF bit will remain set to '1' until written to logic '0.' The oscillator must start and have
run for at least 4 seconds before attempting to reset the OF bit to '0.' If the trigger event
occurs during a power down condition, this bit will be set correctly.
3.14 Oscillator fail interrupt enable
If the oscillator fail interrupt bit (OFIE) is set to a '1,' the IRQ/FT/OUT pin will also be
activated. The IRQ
reading the flags register).
/FT/OUT output is cleared by resetting the OFIE or OF bit to '0' (not be
Doc ID 12615 Rev 6 35/51
Clock operation M41T93
3.15 Initial power-on defaults
Upon initial application of power to the device, the register bits will initially power-on in the
state indicated in Ta bl e 1 3 and Tab le 1 4.
Table 13. Initial power-on default values (part 1)
DCS
Condition
(1)
ST CB1 CB0 OUT FT
ACS
Digital
calib.
Analog
calib.
OFIE Watchdog
(2)
A1IE SQWE ABE
Initial
power-up
Subsequent
power-up
1. All other control bits power-up in an undetermined state
2. BMB0-BMB4, RB0, RB1
3. With battery backup
4. UC = Unchanged
(3)(4)
000 100 0 0 0 0 0 1 0
UC UC UC UC 0 UC UC UC UC 0 UC UC UC
Table 14. Initial power-up default values (part 2)
Condition
Initial
power-up
Subsequent
power-up
1. All other control bits power-up in an undetermined state
2. With battery backup
3. UC = Unchanged
(1)
RPT11-15 HT OF TE TI/TP TIE TD1 TD0 RS0 RS1-3 OTP RPT21-25 AL2E
011000111000 0
(2)(3)
UC 1 UC 0 UC UC UC UC UC UC UC UC UC
3.16 OTP bit operation (SOX18 package only)
When the OTP (one time programmable) bit is set to a '1,' the value in the internal OTP
registers will be transferred to the analog calibration register (12h) and are “read only.” The
OTP value is programmed by the manufacturer, and will contain the calibration value
necessary to achieve ±5 ppm at room temperature after two SMT reflows. This clock
accuracy can be guaranteed to drift no more than ±3 ppm the first year, and ±1 ppm for
each following year due to crystal aging.
If the OTP bit is set to '0,' the analog calibration register will become a WRITE/READ
register and function like standard SRAM memory cells, allowing the user to implement any
desired value of analog calibration.
When the user sets the OTP bit, they need to wait for approximately 8 ms before the analog
registers transfer the value from the OTP to the analog registers due to the OTP read
operation.
36/51 Doc ID 12615 Rev 6
M41T93 Maximum ratings
4 Maximum ratings
Stressing the device above the rating listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 15. Absolute maximum ratings
Symbol Parameter Value
(1)
Unit
T
STG
V
CC
T
SLD
V
I
P
1. Data based on characterization results, not tested in production.
2. Reflow at peak temperature of 260 °C (total thermal budget not to exceed 245 °C for greater than 30
seconds).
Storage temperature (VCC off, oscillator off) –55 to 125 °C
Supply voltage –0.3 to 7.0 V
(2)
Lead solder temperature for 10 seconds
QFN16 260 °C
SOX18 245 °C
Input or output voltages –0.2 to Vcc+0.3 V
IO
Output current 20 mA
O
Power dissipation 1 W
D
Doc ID 12615 Rev 6 37/51
DC and AC parameters M41T93
5 DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC characteristic
tables are derived from tests performed under the measurement conditions listed in the
relevant tables. Designers should check that the operating conditions in their projects match
the measurement conditions when using the quoted parameters.
Table 16. Operating and AC measurement conditions
Parameter M41T93
Supply voltage (V
Ambient operating temperature (T
Load capacitance (C
) 2.38 V to 5.5 V
CC
) –40 to +85 °C
A
, typical) 30 pF
L
Input rise and fall times ≤ 50 ns
Input pulse voltages 0.2VCC to 0.8V
Input and output timing ref. voltages 0.3VCC to 0.7V
Note: Output Hi-Z is defined as the point where data is no longer driven.
Figure 17. Measurement AC I/O waveform
0.8V
CC
0.2V
CC
Table 17. Capacitance
Symbol Parameter
C
IN
(3)
C
OUT
1. Effective capacitance measured with power supply at 3.6 V; sampled only, not 100% tested
2. At 25 °C, f = 1 MHz
3. Outputs deselected
Input capacitance - 7 pF
Output capacitance - 10 pF
(1)(2)
Min Max Unit
0.7V
0.3V
CC
CC
CC
CC
AI02568
38/51 Doc ID 12615 Rev 6
M41T93 DC and AC parameters
Table 18. DC characteristics
IN
≤ V
≤ V
(1)
CC
CC
Min Typ Max Unit
5.5 V 8 10 µA
3.0 V 6.5 µA
CC
VCC/V
BAT
= 3.0 V,
IOL = 1.0 mA
V
= 3.0 V,
CC
= 1.0 mA
I
OL
= 3.0 V,
V
CC
= 3.0 mA
I
OL
= 3 V;
BAT
365 450 nA
±1 µA
±1 µA
CC
VCC+0.3 V
0.4 V
0.4 V
0.4 V
V
Sym Parameter Test condition
Operating voltage (S) –40 to 85 °C 3.00 5.50 V
V
Operating voltage (R) –40 to 85 °C 2.70 5.50 V
CC
Operating voltage (Z) –40 to 85 °C 2.38 5.50 V
Input leakage current 0 V ≤ V
I
LI
Output leakage current 0 V ≤ V
I
LO
Supply current
I
SCL = 0.1V
CC1
SDO = open
I
Supply current (standby)
CC2
CC
/0.9V
CC
E
= VCC;
All inputs ≥ V
OUT
= 2 MHz 0.5 mA
f
SCL
= 5 MHz 1.0 mA
f
SCL
= 10 MHz 2.0 mA
f
SCL
– 0.2 V;
CC
≤ VSS + 0.2 V
V
Input low voltage –0.3 0.3V
IL
Input high voltage 0.7V
V
IH
, FT/RST
RST
Output low voltage
V
OL
SQW, IRQ
/FT/OUT
SDO
V
Output high voltage VCC = 3.0 V, IOH = –1.0 mA (push-pull) 2.4 V
OH
Pull-up supply voltage
(open drain)
V
Backup supply voltage 1.8 5.5 V
BAT
I
Battery supply current
BAT
25 °C; V
CC
/FT/OUT 5.5 V
IRQ
= 0 V; OSC on; V
32 KHz off
1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 2.38 V to 5.5 V (except where noted)
Doc ID 12615 Rev 6 39/51
DC and AC parameters M41T93
Figure 18. I
10.000
9.000
8.000
7.000
6.000
Icc2 (µA)
5.000
4.000
3.000
2.000
Table 19. Crystal electrical characteristics
Symbol Parameter
vs. temperature
CC2
-40 -20 0 20 40 60 80
Temperature (°C)
(1)(2)
(3.0V)
(5.0V)
ai 13909
Min Typ Max Units
f
Resonant frequency - 32.768 kHz
O
R
C
1. Externally supplied if using the QFN16 package. STMicroelectronics recommends the Citizen CFS-145
(1.5 x 5 mm) and the KDS DT-38 (3 x 8 mm) for thru-hole, or the KDS DMX-26S (3.2 x 8 mm) or Micro
Crystal MS3V-T1R (1.5 x 5 mm) for surface-mount, tuning fork-type quartz crystals. For contact
Series resistance - 65
S
Load capacitance - 12.5 pF
L
(3)
kΩ
information, see Section 8: References on page 49.
2. Load capacitors are integrated within the M41T93. Circuit board layout considerations for the 32.768 kHz
crystal of minimum trace lengths and isolation from RF generating signals should be taken into account.
3. Guaranteed by design.
Table 20. Oscillator characteristics
Symbol Parameter
C
XI, CXO
V
t
STA
STA
Oscillator start voltage ≤4 s 2.0 V
Oscillator start time VCC = V
(1)
Capacitor input, capacitor output 25 pF
IC-to-IC frequency variation
(1)(2)
(2)(3)
Conditions Min Typ Max Units
SO
1s
–10 +10 ppm
1. With default analog calibration value ( = 0)
2. Reference value
3. TA = 25 °C, VCC = 5.0 V
40/51 Doc ID 12615 Rev 6
M41T93 DC and AC parameters
Figure 19. Power down/up mode AC waveforms
V
CC
VSO
SCL
SDI
Table 21. Power down/up trip points DC characteristics
Sym Parameter
tPD
(1)(2)
DON'T CARE
Min Typ Max Unit
S 2.85 2.93 3.0 V
V
Reset threshold voltage
RST
R 2.55 2.63 2.7 V
Z 2.25 2.32 2.38 V
V
Battery backup switchover V
SO
Hysteresis 25 mV
RST
Reset pulse width (VCC rising) 140 280 ms
t
rec
1. All voltages referenced to V
2. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 2.38 to 5.5 V (except where noted)
to reset delay, VCC = (V
V
CC
(V
– 100 mV; for VCC slew rate of 10 mV/µs
RST
SS
+ 100 mV), falling to
RST
trec
AI11839
V
2.5 µs
Doc ID 12615 Rev 6 41/51
DC and AC parameters M41T93
Figure 20. Input timing requirements
tEHEL
E
SCL
tDVCH
tELCHtCHEL
tCHDX
tCHEH
tCLCH
tEHCH
tCHCL
SDI
SDO
MSB IN
HIGH IMPEDANCE
Figure 21. Output timing requirements
E
SCL
tCLQV
tCLQX
SDO
ADDR. LSB IN
SDI
MSB OUT
tDLDH
tDHDL
tCH
LSB IN
tQLQH
tQHQL
tCL
AI12295
tEHQZ
LSB OUT
AI04634
42/51 Doc ID 12615 Rev 6
M41T93 DC and AC parameters
Table 22. AC characteristics
VCC < 2.7 V VCC ≥ 2.7 V
Sym Parameter
(1)
Min Max Min Max
f
SCL
t
ELCH
t
EHCH
t
EHEL
t
CHEH
t
CHEL
t
CH
t
CL
t
CLCH
t
CHCL
t
DVC H
t
CHDX
t
EHQZ
t
CLQV
t
CLQX
t
QLQH
t
QHQL
1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 2.38 to 5.5 V (except where noted)
2. tCH and tCL must never be lower than the shortest possible clock period, 1/f
3. Value guaranteed by characterization, not 100% tested in production
SCL clock frequency D.C. 5 D.C. 10 MHz
E active setup time 90 30 ns
E not active setup time 90 30 ns
E deselect time 100 40 ns
E active hold time 90 30 ns
E not active hold time 90 30 ns
(2)
Clock high time 90 40 ns
(2)
Clock low time 90 40 ns
(3)
Clock rise time 1 2 µs
(3)
Clock fall time 1 2 µs
Data in setup time 20 10 ns
Data in hold time 30 10 ns
(3)
Output disable time 100 40 ns
Clock low to output valid 60 40 ns
Output hold time 0 0 ns
(3)
Output rise time 50 40 ns
(3)
Output fall time 50 40 ns
C(max)
Units
Doc ID 12615 Rev 6 43/51
Package mechanical data M41T93
6 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
44/51 Doc ID 12615 Rev 6
M41T93 Package mechanical data
Figure 22. QFN16 – 16-lead, quad, flat package, no lead, 4 x 4 mm body size, outline
D
E
ddd
A3
C
b
L
E2
K
e
(2)
D2
A
A1
K
1
2
3
Ch
QFN16-A2
1. Drawing is not to scale
2. Substrate pad should be tied to V
Table 23. QFN16 – 16-lead, quad, flat package, no lead, 4 x 4 mm body, mech. data
SS
mm inches
Sym
Typ Min Max Typ Min Max
A 0.90 0.80 1.00 0.035 0.032 0.039
A1 0.02 0.00 0.05 0.001 0.000 0.002
A3 0.20 – – 0.008 – –
b 0.30 0.25 0.35 0.010 0.007 0.012
D 4.00 3.90 4.10 0.118 0.114 0.122
D2 – 2.50 2.80 0.067 0.061 0.071
E 4.00 3.90 4.10 0.118 0.114 0.122
E2 – 2.50 2.80 0.067 0.061 0.071
e0.65– –0.020– –
K0.20– –0.008– –
L 0.40 0.30 0.50 0.016 0.012 0.020
ddd – 0.08 – – 0.003 –
Ch – 0.33 – – 0.013 –
N16 16
Doc ID 12615 Rev 6 45/51
Package mechanical data M41T93
Figure 23. QFN16 – 16-lead, quad, flat, no lead, 4 x 4 mm, recommended footprint
2.70
0.70
0.20
(2)
4.50
2.70
0.35
0.325
0.65
AI11815
1. Dimensions shown are in millimeters (mm)
2. Substrate pad should be tied to V
SS
Figure 24. 32 KHz crystal + QFN16 vs. VSOJ20 mechanical data
6.0 ± 0.2
3.2
VS OJ 20
SMT
1
2
3
4
161514
XO
CRYSTAL
XI
ST QFN16
3.9
1.5
3.9
Note: Dimensions shown are in millimeters (mm).
13
7.0 ± 0.3
AI11816
46/51 Doc ID 12615 Rev 6
M41T93 Package mechanical data
Figure 25. SOX18 – 18-lead plastic small outline, 300 mils, embedded crystal
D
9
10 18
B
1
E
H
AA2
e
A1
ddd
h x 45°
C
LA1 α
SO-J
Note: Drawing is not to scale.
Table 24. SOX18 – 18-lead plastic SO, 300 mils, embedded crystal, pkg. mech. data
mm inches
Sym
Typ Min Max Typ Min Max
A – 2.44 2.69 – 0.096 0.106
A1 – 0.15 0.31 – 0.006 0.012
A2 – 2.29 2.39 – 0.090 0.094
B – 0.41 0.51 – 0.016 0.020
C – 0.20 0.31 – 0.008 0.012
D 11.61 11.56 11.66 0.457 0.455 0.459
ddd – – 0.10 – – 0.004
E – 7.57 7.67 – 0.298 0.302
e1.27– –0.050– –
H – 10.16 10.52 – 0.400 0.414
L – 0.51 0.81 – 0.020 0.032
α – 0° 8° – 0° 8°
N18 18
Doc ID 12615 Rev 6 47/51
Part numbering M41T93
7 Part numbering
Table 25. Ordering information
Example: M41T 93 S QA 6 E
Device family
M41T
Device type
93
Operating voltage
S = V
R = V
Z = V
= 3.00 to 5.5 V
CC
= 2.70 to 5.5 V
CC
= 2.38 to 5.5 V
CC
Package
QA = QFN16 (4 mm x 4 mm)
(1)
MY
= SOX18
Temperature range
6 = –40 °C to +85 °C
Shipping method
E = ECOPACK
®
package, tubes
(2)
F = ECOPACK® package, tape & reel
1. The SOX18 package includes an embedded 32,768 Hz crystal. Contact local ST sales office for
availability.
2. Not recommended for new design. Contact local ST sales office for availability.
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
48/51 Doc ID 12615 Rev 6
M41T93 References
8 References
Below is a listing of the crystal component suppliers mentioned in this document.
● KDS can be contacted at kouhou@kdsj.co.jp or http://www.kdsj.co.jp.
● Citizen can be contacted at csd@citizen-america.com or
http://www.citizencrystal.com.
● Micro Crystal can be contacted at sales@microcrystal.ch or
http://www.microcrystal.com.
Doc ID 12615 Rev 6 49/51
Revision history M41T93
9 Revision history
Table 26. Document revision history
Date Revision Changes
07-Aug-2006 1 Initial release.
Document status upgraded to full datasheet; updated Figure 12: Clock
08-May-2007 2
22-Oct-2007 3
accuracy vs. on-chip load capacitors; Section 3.16; Section 3.4.1;
Ta bl e 1 , 15, and 18, Figure 3 and 24; added Figure 18: I
temperature. Micro Crystal information added (Ta bl e 1 9 ).
Updated Features on cover page; minor formatting changes; modified
footnote 1 in Ta bl e 1 9 ; added Section 8: References.
CC2
vs.
15-Aug-2008 4
19-Oct-2010 5
12-Oct-2011 6
Removed references to SPI bus mode 3 operation (updated cover page,
Figure 5, 6, Section 1.1.3, Section 2.1); minor formatting changes.
Updated Note in Section 3.13: Oscillator fail detection; updated
ECOPACK® text in Section 6: Package mechanical data; reformatted
document.
Updated Features, title, Section 3.1: Clock data coherency, Section 3.2:
Halt bit (HT) operation; added Figure 9, added footnote 2 to Ta b le 2 5 :
Ordering information.
50/51 Doc ID 12615 Rev 6
M41T93
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2011 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
Doc ID 12615 Rev 6 51/51
Loading...