ST M41T56 User Manual

M41T56

Serial real-time clock (RTC) with 56 bytes NVRAM

Features

■ Counters for seconds, minutes, hours, day,

date, month, years, and century

■ 32 KHz crystal oscillator integrating load

capacitance (12.5 pF) providing exceptional
oscillator stability and high crystal series
resistance operation

■ Serial interface supports I

protocol)

■ Ultra-low battery supply current of 450 nA

(typ at 3 V)

■ 5 V ±10% supply voltage

■ Timekeeping down to 2.5 V

■ Automatic power-fail detect and switch circuitry

■ 56 bytes of general purpose RAM

■ Software clock calibration to compensate

crystal deviation due to temperature

■ Automatic leap year compensation

■ Operating temperature of –40 °C to 85 °C

■ Available in an 8-lead, 150-mil, plastic SOIC

(SO8)

■ RoHS compliant

– Lead-free second level interconnect

2

C bus (100 kHz

8

1

SO8

150-mil width

December 2011 Doc ID 6104 Rev 9 1/27

www.st.com

1

Contents M41T56

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1.1 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1.2 Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1.3 Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1.4 Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1.5 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3 Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.4 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3 Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.1 Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2 Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.3 Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2/27 Doc ID 6104 Rev 9

M41T56 List of tables

List of tables

Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 3. Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 5. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 6. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 7. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 8. Crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 9. Power down/up mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 10. Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 11. SO8 – 8-pin plastic small outline, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . 21

Table 12. Carrier tape dimensions for SO8 package (150-mil body width) . . . . . . . . . . . . . . . . . . . . 22

Table 13. Reel dimensions for 12 mm carrier tape - SO8 package (150-mil body width). . . . . . . . . . 23

Table 14. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 15. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Doc ID 6104 Rev 9 3/27

List of figures M41T56

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. 8-pin SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. M41T56 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 5. Acknowledge sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 6. Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 7. Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 8. Read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 9. Alternative read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 10. Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 11. Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 12. Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 13. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 14. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 15. SO8 – 8-pin plastic small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 16. Carrier tape for SO8 package (150-mil body width) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 17. Reel schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4/27 Doc ID 6104 Rev 9

M41T56 Description

1 Description

The M41T56 is a low-power, serial real-time clock (RTC) with 56 bytes of NVRAM. A built-in
32,768 Hz oscillator (external crystal controlled) and the first 8 bytes of the RAM are used
for the clock/calendar function and are configured in binary coded decimal (BCD) format.
Addresses and data are transferred serially via a two-line, bidirectional bus. The built-in
address register is incremented automatically after each WRITE or READ data byte.

The M41T56 clock has a built-in power sense circuit which detects power failures and
automatically switches to the battery supply during power failures. The energy needed to
sustain the RAM and clock operations can be supplied from a small lithium coin cell.

Typical data retention time is in excess of 10 years with a 50 mAh, 3 V lithium cell. The
M41T56 is supplied in an 8-lead plastic SOIC package.

Figure 1. Logic diagram

OSCI

SCL

V

CC

M41T56

V

SS

V

BAT

OSCO

SDA

FT/OUT

AI02304B

Doc ID 6104 Rev 9 5/27

Description M41T56

Table 1. Signal names

OSCI Oscillator input

OCSO Oscillator output

FT/OUT Frequency test / output driver (open drain)

SDA Serial data address input / output

SCL Serial clock

V

BAT

V

CC

V

SS

Battery supply voltage

Supply voltage

Ground

Figure 2. 8-pin SOIC connections

M41T56

OSCI V

V

BAT

SS

Figure 3. M41T56 block diagram

OSCI

OSCO

FT/OUT

V

CC

V

SS

V

BAT

SCL

SDA

OSCILLATOR

32.768 kHz

VOLTAGE

SENSE

and

SWITCH

CIRCUITRY

SERIAL

BUS

INTERFACE

1
2

3

4

8

7
6
5

DIVIDER

CONTROL

LOGIC

ADDRESS

REGISTER

CC

FT/OUTOSCO

SCL
SDAV

1 Hz

AI02306B

SECONDS

MINUTES

CENTURY/HOURS

DAY

DATE

MONTH

YEAR

CONTROL

RAM

(56 x 8)

6/27 Doc ID 6104 Rev 9

AI02566

M41T56 Operation

2 Operation

The M41T56 clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 64 bytes
contained in the device can then be accessed sequentially in the following order:

1. Seconds register

2. Minutes register

3. Century/hours register

4. Day register

5. Date register

6. Month register

7. Years register

8. Control register

9. RAM

The clock continually monitors V
V

, the device terminates an access in progress and resets the device address counter.

PFD

for an out of tolerance condition. Should VCC fall below

CC

Inputs to the device will not be recognized at this time to prevent erroneous data from being
written to the device from an out of tolerance system. When V
automatically switches over to the battery and powers down into an ultra low current mode
of operation to conserve battery life. Upon power-up, the device switches from battery to
V

CC

at V

and recognizes inputs when VCC goes above V

BAT

2.1 2-wire bus characteristics

This bus is intended for communication between different ICs. It consists of two lines: one
bidirectional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the
SCL lines must be connected to a positive supply voltage via a pull-up resistor.

The following protocol has been defined:

● Data transfer may be initiated only when the bus is not busy.

● During data transfer, the data line must remain stable whenever the clock line is high.

● Changes in the data line while the clock line is high will be interpreted as control

signals.

Accordingly, the following bus conditions have been defined:

2.1.1 Bus not busy

falls below V

CC

volts.

PFD

, the device

BAT

Both data and clock lines remain high.

2.1.2 Start data transfer

A change in the state of the data line, from high to low, while the clock is high, defines the
START condition.

Doc ID 6104 Rev 9 7/27

Operation M41T56

2.1.3 Stop data transfer

A change in the state of the data line, from low to high, while the clock is high, defines the
STOP condition.

2.1.4 Data valid

The state of the data line represents valid data when after a start condition, the data line is
stable for the duration of the high period of the clock signal. The data on the line may be
changed during the low period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and stop conditions is not limited.
The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.

By definition, a device that gives out a message is called “transmitter,” the receiving device
that gets the message is called “receiver.” The device that controls the message is called
“master.” The devices that are controlled by the master are called “slaves.”

2.1.5 Acknowledge

Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low
level put on the bus by the receiver, whereas the master generates an extra acknowledge
related clock pulse.

A slave receiver which is addressed is obliged to generate an acknowledge after the
reception of each byte. Also, a master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the slave transmitter.

The device that acknowledges has to pull down the SDA line during the acknowledge clock
pulse in such a way that the SDA line is a stable low during the high period of the
acknowledge related clock pulse. Of course, setup and hold times must be taken into
account. A master receiver must signal an end-of-data to the slave transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave. In this
case, the transmitter must leave the data line high to enable the master to generate the
STOP condition.

Figure 4. Serial bus data transfer sequence

DATA LINE

STABLE

DATA VALID

CLOCK

DATA

START

CONDITION

CHANGE OF

DATA ALLOWED

STOP

CONDITION

8/27 Doc ID 6104 Rev 9

AI00587

M41T56 Operation

Figure 5. Acknowledge sequence

CLOCK PULSE FOR

ACKNOWLEDGEMENT

SCLK FROM
MASTER

START

12 89

DATA OUTPUT
BY TRANSMITTER

DATA OUTPUT
BY RECEIVER

MSB LSB

Figure 6. Bus timing requirements sequence

SDA

tHD:STAtBUF

tR

SCL

SP

tHIGH

tLOW

tF

tHD:DAT

tSU:DAT

SR

AI00601

tHD:STA

tSU:STOtSU:STA

P

AI00589

Doc ID 6104 Rev 9 9/27