ST M36W108AT, M36W108AB User Manual

M36W108AB100ZM1T

M36W108AT

M36W108AB

8 Mbit (1Mb x8, Boot Block) Flash Memory and 1 Mbit (128Kb x8) SRAM Low Voltage Multi-Memory Product

■SUPPLY VOLTAGE

–VCCF = VCCS = 2.7V to 3.6V: for Program, Erase and Read

■ACCESS TIME: 100ns

■LOW POWER CONSUMPTION

–Read: 40mA max. (SRAM chip)

–Stand-by: 30µA max. (SRAM chip)

–Read: 10mA max. (Flash chip)

–Stand-by: 100µA max. (Flash chip)

FLASH MEMORY

■8 Mbit (1Mb x 8) BOOT BLOCK ERASE

■PROGRAMMING TIME: 10µs typical

■PROGRAM/ERASE CONTROLLER (P/E.C.)

–Program Byte-by-Byte

–Status Register bits and Ready/Busy Output

■SECURITY PROTECTION MEMORY AREA

■INSTRUCTION ADDRESS CODING: 3 digits

■MEMORY BLOCKS

–Boot Block (Top or Bottom location)

–Parameter and Main Blocks

■BLOCK, MULTI-BLOCK and CHIP ERASE

■ERASE SUSPEND and RESUME MODES

–Read and Program another Block during Erase Suspend

■100,000 PROGRAM/ERASE CYCLES per BLOCK

■ELECTRONIC SIGNATURE

–Manufacturer Code: 20h

–Device Code, M36W108AT: D2h

–Device Code, M36W108AB: DCh

SRAM

■1 Mbit (128Kb x 8)

■POWER DOWN FEATURES USING TWO CHIP ENABLE INPUTS

■LOW VCC DATA RETENTION: 2V

PRELIMINARY DATA

BGA		LGA

LBGA48 (ZM)	LGA48 (ZN)
6 x 8 solder balls	6 x 8 solder lands

Figure 1. Logic Diagram

	VCCF	VCCS
20		8
A0-A19		DQ0-DQ7
W
EF		RB
	M36W108AT
G	M36W108AB
RP
E1S
E2S
	VSS	AI02620

March 1999

1/36

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M36W108AT, M36W108AB

Figure 2. LBGA and LGA Connections (Top View)

	1	2	3	4	5	6
A	W	A14	A11	G	A10	E1S
B	VCCS	A18	A8	DQ7	DQ5	VSS
C	A17	NC	A5	DQ4	DQ2	DQ1
D	VSS	EF	NC	DQ0	A0	A1
E	NC	NC	DQ3	A6	A3	A2
F	NC	VCCF	NC	A19	A7	A4
G	NC	DQ6	A13	RP	RB	E2S
H	NC	A12	NC	A16	A15	A9

AI02508

Table 1. Signal Names

	A0-A16							Address Inputs
	A17-A19							Address Inputs for Flash Chip
	DQ0-DQ7							Data Input/Outputs, Command Inputs
								for Flash Chip
								Chip Enable for Flash Chip
	EF
							E2S	Chip Enable for SRAM Chip
	E1S,
								Output Enable
	G
								Write Enable
	W
								Reset for Flash Chip
	RP
								Ready/Busy Output for Flash Chip
	RB
	VCCF							Supply Voltage for Flash Chip
	VCCS							Supply Voltage for SRAM Chip
	VSS							Ground
	NC							Not Connected Internally

DESCRIPTION

The M36W108A is multi-chip device containing an 8 Mbit boot block Flash memory and a 1 Mbit of SRAM. The device is offered in the new Chip Scale Package solutions: LBGA48 1.0mm ball pitch and LGA48 1.0mm land pitch.

The two components, of the package’s overall 9 Mbit of memory, are distinguishable by use of the three chip enable lines: EF for the Flash memory, E1S and E2S for the SRAM.

The Flash memory component is identical with the M29W008A device. It is a non-volatile memory that may be erased electrically at the block or chip level and programmed in-system on a Byte-by- Byte basis using only a single 2.7V to 3.6V VCCF supply. For Program and Erase operations the necessary high voltages are generated internally. The device can also be programmed in standard programmers. The array matrix organization allows each block to be erased and reprogrammed without affecting other blocks.

Instructions for Read/Reset, Auto Select for reading the Electronic Signature, Programming, Block

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M36W108AT, M36W108AB

Table 2. Absolute Maximum Ratings (1)

Symbol									Parameter	Value	Unit
	TA					Ambient Operating Temperature (3)				–40 to 85	°C
TBIAS						Temperature Under Bias				–50 to 125	°C
TSTG						Storage Temperature				–65 to 150	°C
VIO (2)						Input or Output Voltage				–0.5 to VCC +0.5	V
VCCF						Flash Chip Supply Voltage				–0.6 to 5	V
VCCS						SRAM Chip Supply Voltage				–0.3 to 4.6	V
V									Voltage	0.6 to 13.5	V
						EF,		RP
	(EF,		RP)
	PD					Power Dissipation				0.7	W

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.

2.Minimum Voltage may undershoot to –2V during transition and for less than 20ns.

3.Depends on range.

and Chip Erase, Erase Suspend and Resume are written to the device in cycles of commands to a Command Interface using standard microprocessor write timings.

The SRAM component is a low power SRAM that features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 2.7V to 3.6V VCCS supply, and all inputs and outputs are TTL compatible.

SIGNAL DESCRIPTIONS

See Figure 1 and Table 1.

Address Inputs (A0-A16). Addresses A0 to A16 are common inputs for the Flash chip and the SRAM chip. The address inputs for the Flash memory or the SRAM array are latched during a write operation on the falling edge of Flash Chip Enable (EF), SRAM Chip Enable (E1S or E2S) or Write Enable (W).

Address Inputs (A17-A19). Address A17 to A19 are address inputs for the Flash chip. They are latched during a write operation on the falling edge of Flash Chip Enable (EF) or Write Enable (W).

Data Input/Outputs (DQ0-DQ7). The input is data to be programmed in the Flash or SRAM memory array or a command to be written to the C.I. of the Flash chip. Both are latched on the rising edge of Flash Chip Enable (EF), SRAM Chip Enable (E1S or E2S) or Write Enable (W). The output is data from the Flash memory or SRAM array, the Electronic Signature Manufacturer or Device codes or the Status register Data Polling bit

DQ7, the Toggle Bits DQ6 and DQ2, the Error bit DQ5 or the Erase Timer bit DQ3. Outputs are valid when Flash Chip Enable (EF) or SRAM Chip Enable (E1S or E2S) and Output Enable (G) are active. The output is high impedance when the both the Flash chip and the SRAM chip are deselected or the outputs are disabled and when Reset (RP) is at a VIL.

Flash Chip Enable (EF). The Chip Enable input for Flash activates the memory control logic, input buffers, decoders and sense amplifiers. EF at VIH deselects the memory and reduces the power consumption to the standby level. EF can also be used to control writing to the command register and to the Flash memory array, while W remains

at VIL. It is not allowed to set EF at VIL, E1S at VIL and E2S at VIH at the same time.

SRAM Chip Enable (E1S, E2S). The Chip Enable inputs for SRAM activate the memory control logic, input buffers, decoders and sense amplifiers. E1S at VIH or E2S at VIL deselects the memory and reduces the power consumption to the standby level. E1S and E2S can also be used to control writing to the SRAM memory array, while

W remains at VIL. It is not allowed to set EF at VIL, E1S at VIL and E2S at VIH at the same time.

Output Enable (G). The Output Enable gates the outputs through the data buffers during a read operation. When G is High the outputs are High impedance.

Write Enable (W). The Write Enable input controls writing to the Command Register of the Flash chip and Address/Data latches.

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M36W108AT, M36W108AB

Table 3. Main Operation Modes (1)

Operation Mode

EF

E1S

E2S

G

W

RP

DQ7-DQ0

Flash Chip Read

VIL

VIH

X

VIL

VIH

VIH

Data Output

VIL

X

VIL

VIL

VIH

VIH

Data Output

SRAM Chip Read

VIH

VIL

VIH

VIL

VIH

X

Data Output

Flash Chip Write

VIL

VIH

X

VIH

VIL

VIH

Data Input

VIL

X

VIL

VIH

VIL

VIH

Data Input

SRAM Chip Write

VIH

VIL

VIH

X

VIL

X

Data Input

Flash Chip Output Disable

X

VIH

X

VIH

VIH

X

Hi-Z

X

X

VIL

VIH

VIH

X

Hi-Z

SRAM Chip Output Disable

VIH

VIL

VIH

VIH

VIH

X

Hi-Z

Flash Chip Stand-by

VIH

X

X

X

X

VIH

Hi-Z

Flash Chip Reset

X

VIH

X

X

X

VIL

Hi-Z

X

X

VIL

X

X

VIL

Hi-Z

SRAM Chip Stand-by

X

VIH

X

X

X

VIL

Hi-Z

X

X

VIL

X

X

VIL

Hi-Z

Note: 1. X = VIL or VIH.

Reset Input (RP). The Reset input provides hardware reset of the Flash chip. Reset of the Flash memory is achieved by pulling RP to VIL for

at least tPLPX. When the reset pulse is given, if the Flash memory is in Read or Standby modes, it will

be available for new operations in tPHEL after the rising edge of RP.

If the Flash memory is in Erase or Program mode

the reset will take tPLYH during which the Ready/ Busy (RB) signal will be held at VIL. The end of the

Flash memory reset will be indicated by the rising edge of RB. A hardware reset during an Erase or Program operation will corrupt the data being programmed or the block(s) being erased. See Table 18 and Figure 10.

Ready/Busy Output (RB). Ready/Busy is an open-drain output of the Flash chip. It gives the internal state of the Program/Erase Controller (P/ E.C.) of the Flash device. When RB is Low, the Flash device is busy with a Program or Erase operation and it will not accept any additional program or erase instructions except the Erase Suspend instruction. When RB is High, the Flash device is ready for any Read, Program or Erase operation. The RB will also be High when the Flash memory is put in Erase Suspend or Standby modes.

VCCF Supply Voltage. Flash memory power supply for all operations (Read, Program and Erase).

VCCS Supply Voltage. SRAM power supply for all operations (Read, Program).

VSS Ground. VSS is the reference for all voltage measurements.

POWER SUPPLY

Power Up. The Flash memory Command Interface is reset on power up to Read Array. Either Flash Chip Enable (EF) or Write Enable (W) inputs must be tied to VIH during Power Up to allow maximum security and the possibility to write a command on the first rising edge of EF and W. Any write cycle initiation is blocked when VCCF is below VLKO.

Supply Rails. Normal precautions must be taken for supply voltage decoupling; each device in a system should have the VCCF, VCCS rails decoupled with a 0.1µF capacitor close to the VCCF,

VCCS and VSS pins. The PCB trace widths should be sufficient to carry the VCCF and VCCS program

currents and the VCCF erase current required.

4/36

M36W108AT, M36W108AB

Figure 3. Internal Functional Arrangement

VCCF VSS

RP

EF

8 Mbit

A0-A19 Flash Memory

(1Mb x 8)

W

G

VCCS VSS

A0-A16

1 Mbit SRAM

(128 Kb x 8)

E1S

E2S

RB

DQ0-DQ7

AI02444

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M36W108AT, M36W108AB

FLASH MEMORY COMPONENT

Organization and Architecture

Organization. The Flash chip is organized as 1Mbit x 8. The memory uses the address inputs A0-A19 and the Data Input/Outputs DQ0-DQ7. Memory control is provided by Chip Enable (EF), Output Enable (G) and Write Enable (W) inputs.

Erase and Program operations are controlled by an internal Program/Erase Controller (P/E.C.). Status Register data output on DQ7 provides a Data Polling signal, while Status Register data outputs on DQ6 and DQ2 provide Toggle signals to indicate the state of the P/E.C. operations. A Ready/Busy (RB) output indicates the completion of the internal algorithms.

Memory Blocks. The device features asymmetrically blocked architecture providing system memory integration. Both Top and Bottom Boot Block devices have an array of 19 blocks, one Boot Block of 16K Bytes, two Parameter Blocks of 8K Bytes, one Main Block of 32K Bytes and fifteen Main Blocks of 64K Bytes. The Top Boot Block

Table 4. Top Boot Block, Flash Block Address

Size (KWord)	Address Range
16	FC000h-FFFFFh
8	FA000h-FBFFFh
8	F8000h-F9FFFh
32	F0000h-F7FFFh
64	E0000h-EFFFFh
64	D0000h-DFFFFh
64	C0000h-CFFFFh
64	B0000h-BFFFFh
64	A0000h-AFFFFh
64	90000h-9FFFFh
64	80000h-8FFFFh
64	70000h-7FFFFh
64	60000h-6FFFFh
64	50000h-5FFFFh
64	40000h-4FFFFh
64	30000h-3FFFFh
64	20000h-2FFFFh
64	10000h-1FFFFh
64	00000h-0FFFFh

6/36

version has the Boot Block at the top of the memory address space and the Bottom Boot Block version locates the Boot Block starting at the bottom. The memory maps and block address tables are showed in Figures 4, 5 and Tables 4, 5. Each block can be erased separately, any combination of blocks can be specified for multi-block erase or the entire chip may be erased. The Erase operations are managed automatically by the P/E.C. The block erase operation can be suspended in order to read from or program to any block not being erased, and then resumed.

Device Operations

The following operations can be performed using the appropriate bus cycles: Read Array, Write command, Output Disable, Standby and Reset (see Table 6).

Read. Read operations are used to output the contents of the Memory Array, the Electronic Sig- nature or the Status Register. Both Chip Enable (EF) and Output Enable (G) must be low, with Write Enable (W) high, in order to read the output of the memory.

Table 5. Bottom Boot Block, Flash Block

Address

Size (KWord)	Address Range
64	F0000h-FFFFFh
64	E0000h-EFFFFh
64	D0000h-DFFFFh
64	C0000h-CFFFFh
64	B0000h-BFFFFh
64	A0000h-AFFFFh
64	90000h-9FFFFh
64	80000h-8FFFFh
64	70000h-7FFFFh
64	60000h-6FFFFh
64	50000h-5FFFFh
64	40000h-4FFFFh
64	30000h-3FFFFh
64	20000h-2FFFFh
64	10000h-1FFFFh
32	08000h-0FFFFh
8	06000h-07FFFh
8	04000h-05FFFh
16	00000h-03FFFh

M36W108AT, M36W108AB

Write. Write operations are used to give Instruction Commands to the memory or to latch input data to be programmed. A write operation is initiated when Chip Enable (EF) is Low and Write Enable (W) is at VIL with Output Enable (G) at VIH.

Addresses are latched on the falling edge of W or EF whichever occurs last. Commands and Input Data are latched on the rising edge of W or EF whichever occurs first.

Output Disable. The data outputs are high impedance when the Output Enable (G) is at VIH with

Write Enable (W) at VIH.

Standby. The memory is in standby when Chip Enable (EF) is at VIH and the P/E.C. is idle. The power consumption is reduced to the standby level and the outputs are high impedance, independent of the Output Enable (G) or Write Enable (W) inputs.

Automatic Standby. After 150ns of bus inactivity and when CMOS levels are driving the addresses, the chip automatically enters a pseudo-standby mode where consumption is reduced to the CMOS standby value, while outputs still drive the bus.

Table 6. Flash User Bus Operations (1)

Instructions and Commands

Seven instructions are defined (see Table 7) to perform Read Array, Auto Select (to read the Electronic Signature), Program, Block Erase, Chip Erase, Erase Suspend and Erase Resume. The internal P/E.C. automatically handles all timing and verification of the Program and Erase operations. The Status Register Data Polling, Toggle, Error bits and the RB output may be read at any time, during programming or erase, to monitor the progress of the operation.

Instructions, made up of commands written in cycles, can be given to the Program/Erase Controller through a Command Interface (C.I.).

The C.I. latches commands written to the memory. Commands are made of address and data sequences. Two coded cycles unlock the Command Interface. They are followed by an input command or a confirmation command. The coded sequence consists of writing the data AAh at the address 5555h during the first cycle and the data 55h at the address 2AAAh during the second cycle.

Operation

EF

G

W

RP

A15

A12

A9

A6

A1

A0

DQ7-DQ0

Read Byte

VIL

VIL

VIH

VIH

A15

A12

A9

A6

A1

A0

Data Output

Write Byte

VIL

VIH

VIL

VIH

A15

A12

A9

A6

A1

A0

Data Input

Output Disable

VIL

VIH

VIH

VIH

X

X

X

X

X

X

Hi-Z

Stand-by

VIH

X

X

VIH

X

X

X

X

X

X

Hi-Z

Reset

X

X

X

VIL

X

X

X

X

X

X

Hi-Z

Note: 1. X = VIL or VIH.

Table 7. Read Flash Electronic Signature

Other

Code

Device

EF

G

W

A1

A0

DQ7-DQ0

Addresses

Manufact. Code

VIL

VIL

VIH

VIL

VIL

Don’t care

20h

Device Code

M36W108AT

VIL

VIL

VIH

VIL

VIH

Don’t care

D2h

M36W108AB

VIL

VIL

VIH

VIL

VIH

Don’t care

DCh

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M36W108AT, M36W108AB

Table 8. Flash Commands

	Hex Code	Command
	00h	Invalid/Reserved
	10h	Chip Erase Confirm
	20h	Reserved
	30h	Block Erase Resume/Confirm
	80h	Set-up Erase
	90h	Read Electronic Signature/
		Block Protection Status
	A0h	Program
	B0h	Erase Suspend
	F0h	Read Array/Reset

Instructions are composed of up to six cycles. The first two cycles input a Coded Sequence to the Command Interface which is common to all instructions (see Table 9). The third cycle inputs the instruction set-up command. Subsequent cycles output the addressed data or Electronic Signature for Read operations. In order to give additional data protection, the instructions for Program and Block or Chip Erase require further command inputs. For a Program instruction, the fourth command cycle inputs the address and data to be programmed. For an Erase instruction (block or chip), the fourth and fifth cycles input a further Coded Sequence before the Erase confirm command on the sixth cycle. Erasure of a memory block may be suspended, in order to read data from another block or to program data in another block, and then resumed.

When power is first applied or if VCCF falls below VLKO, the command interface is reset to Read Array.

Command sequencing must be followed exactly. Any invalid combination of commands will reset the device to Read Array. The increased number of cycles has been chosen to assure maximum data security.

Read/Reset (RD) Instruction. The Read/Reset instruction consists of one write cycle giving the command F0h. It can be optionally preceded by the two Coded cycles. Subsequent read operations will read the memory array addressed and

output the data read. A wait state of tPLYH is necessary after Read/Reset prior to any valid read if

the memory was in an Erase or Program mode when the RD instruction is given (see Table 18 and Figure 10).

Auto Select (AS) Instruction. This instruction uses the two Coded cycles followed by one write cycle giving the command 90h to address 5555h for command set-up. A subsequent read will output the Manufacturer Code or the Device Code (Electronic Signature) depending on the levels of A0 and A1 (see Table 7). The Electronic Signature can be read from the memory allowing programming equipment or applications to automatically match their interface to the characteristics of the Flash memory. The Manufacturer Code, 20h, is output when the addresses lines A0 and A1 are at VIL, the Device Code is output when A0 is at VIH with A1 at VIL. Other address inputs are ignored.

Program (PG) Instruction. This instruction uses four write cycles. The Program command A0h is written to address 5555h on the third cycle after two Coded Cycles. A fourth write operation latches the Address and the Data to be written and starts the P/E.C. Read operations output the Status Register bits after the programming has started. Memory programming is made only by writing ’0’ in place of ’1’. Status bits DQ6 and DQ7 determine if programming is on-going and DQ5 allows verification of any possible error. Programming at an address not in blocks being erased is also possible during erase suspend. In this case, DQ2 will toggle at the address being programmed.

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M36W108AT, M36W108AB

Block Erase (BE) Instruction. This instruction uses a minimum of six write cycles. The Erase Set-up command 80h is written to address 5555h on third cycle after the two Coded cycles. The Block Erase Confirm command 30h is similarly written on the sixth cycle after another two Coded Cycles. During the input of the second command an address within the block to be erased is given and latched into the memory.

Additional block Erase Confirm commands and block addresses can be written subsequently to erase other blocks in parallel, without further Coded cycles. The erase will start after the erase timeout period (see Erase Timer Bit DQ3 description). Thus, additional Erase Confirm commands for other blocks must be given within this delay. The input of a new Erase Confirm command will restart the timeout period. The status of the internal timer can be monitored through the level of DQ3, if DQ3 is ’0’ the Block Erase Command has been given and the timeout is running, if DQ3 is ’1’, the timeout has expired and the P/E.C. is erasing the block(s). If the second command given is not an erase confirm or if the Coded cycles are wrong, the instruction aborts, and the device is reset to Read Array. It is not necessary to program the block with 00h as the P/E.C. will do this automatically before to erasing to FFh. Read operations after the sixth rising edge of W or EF output the Status Register bits.

During the execution of the erase by the P/E.C., the memory only accepts the Erase Suspend (ES) and Read/Reset (RD) instructions. A Read/Reset command will definitively abort erasure and result in invalid data in blocks being erased. A complete state of the block erase operation is given by the Status Register bits (see DQ2, DQ3, DQ5, DQ6 and DQ7 description).

Chip Erase (CE) Instruction. This instruction uses six write cycles. The Erase Set-up command 80h is written to address 5555h on the third cycle after the two Coded Cycles. The Chip Erase Confirm command 10h is similarly written on the sixth cycle after another two Coded Cycles. If the sec-

ond command given is not an erase confirm or if the Coded Sequence is wrong, the instruction aborts and the device is reset to Read Array. It is not necessary to program the array with 00h first as the P/E.C. will automatically do this before erasing it to FFh. Read operations after the sixth rising edge of W or EF output the Status Register bits. A complete state of the chip erase operation is given by the Status Register bits (see DQ2, DQ3, DQ5, DQ6 and DQ7 description).

Erase Suspend (ES) Instruction. The Block Erase operation may be suspended by this instruction which consists of writing the command B0h without any specific address. No Coded Cycles are required. It permits reading of data from another block and programming in another block while an erase operation is in progress. Erase suspend is accepted only during the Block Erase instruction execution. Writing this command during the erase timeout period will, in addition to suspending the erase, terminate the timeout. The Toggle bit DQ6 stops toggling when the P/E.C. is suspended. The Toggle bits will stop toggling between 0.1µs and 15µs after the Erase Suspend (ES) command has been written. The device will then automatically be set to Read Memory Array mode. When erase is suspended, a Read from blocks being erased will output DQ2 toggling and DQ6 at '1'. A Read from a block not being erased returns valid data. During suspension the memory will respond only to the Erase Resume (ER) and the Program (PG) instructions. A Program operation can be initiated during Erase Suspend in one of the blocks not being erased. It will result in both DQ2 and DQ6 toggling when the data is being programmed. A Read/Reset command will definitively abort erasure and result in invalid data in the blocks being erased.

Erase Resume (ER) Instruction. If an Erase Suspend instruction was previously executed, the erase operation may be resumed by giving the command 30h, at any address, and without any Coded cycles.

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M36W108AT, M36W108AB

Table 9. Flash Instructions (1)

Mne.

Instr.

Cyc.

1st Cyc.

2nd Cyc.

3rd Cyc.

4th Cyc.

5th Cyc.

6th Cyc.

7th Cyc.

1+

Addr. (3,6)

X

Read Memory Array until a new write cycle is initiated.

RD (2,4)

Read/Reset

Data

F0h

Memory

Addr. (3,6)

555h

2AAh

555h

Array

3+

Read Memory Array until a new write cycle

is initiated.

Data

AAh

55h

F0h

AS (4)

Auto Select

3+

Addr. (3,6)

555h

2AAh

555h

Read Electronic Signature until a new write

cycle is initiated. See Note 5.

Data

AAh

55h

90h

Addr. (3,6)

555h

2AAh

555h

Program

Address

Read Data Polling or Toggle Bit

PG

Program

4

Data

AAh

55h

A0h

Program

until Program completes.

Data

Addr. (3,6)

555h

2AAh

555h

555h

2AAh

Block

Additional

BE

Block Erase

6

Address

Block (7)

Data

AAh

55h

80h

AAh

55h

30h

30h

CE

Chip Erase

6

Addr. (3,6)

555h

2AAh

555h

555h

2AAh

555h

Note 8

Data

AAh

55h

80h

AAh

55h

10h

ES (9)

Erase

1

Addr. (3,6)

X

Read until Toggle stops, then read all the data needed from any

Suspend

Block(s) not being erased then Resume Erase.

Data

B0h

ER

Erase

1

Addr. (3,6)

X

Read Data Polling or Toggle Bits until Erase completes or Erase

Resume

is suspended another time.

Data

30h

Note: 1. Commands not interpreted in this table will default to read array mode.

2.A wait of tPLYH is necessary after a Read/Reset command if the memory was in an Erase, Erase Suspend or Program mode before starting any new operation (see Table 15 and Figure 8).

3.X = Don’t care.

4.The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the command cycles.

5.Signature Address bits A0, A1, at VIL will output Manufacturer code (20h). Address bits A0 at VIH and A1, at VIL will output Device code.

6.For Coded cycles address inputs A11-A19 are don’t care.

7.Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry, timeout status can be verified through DQ3 value (see Erase Timer Bit DQ3 description). When full command is entered, real Data Polling or Toggle bit until Erase is completed or suspended.

8.Read Data Polling, Toggle bits or RB until Erase completes.

9.During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.

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							M36W108AT, M36W108AB
Table 10. Flash Status Register Bits (1)
DQ	Name		Logic Level			Definition	Note
				‘1’		Erase Complete or erase block
						in Erase Suspend
							Indicates the P/E.C. status, check during
	Data			‘0’		Erase On-going
7							Program or Erase, and on completion before
						Program Complete or data of
	Polling						checking bits DQ5 for Program or Erase
				DQ		non erase block during Erase	Success.
						Suspend
						Program On-going
				DQ
			‘-1-0-1-0-1-0-1-’			Erase or Program On-going	Successive reads output complementary
							data on DQ6 while Programming or Erase
			DQ			Program Complete
							operations are on-going. DQ6 remains at
6	Toggle Bit
						Erase Complete or Erase	constant level when P/E.C. operations are
			‘-1-1-1-1-1-1-1-’			Suspend on currently	completed or Erase Suspend is
						addressed block	acknowledged.
5	Error Bit			‘1’		Program or Erase Error	This bit is set to ‘1’ in the case of
				‘0’		Program or Erase On-going	Programming or Erase failure.
4	Reserved
							P/E.C. Erase operation has started. Only
	Erase			‘1’		Erase Timeout Period Expired	possible command entry is Erase Suspend
3							(ES).
	Time Bit
				‘0’		Erase Timeout Period	An additional block to be erased in parallel
						On-going	can be entered to the P/E.C.
						Chip Erase, Erase or Erase
						Suspend on the currently
			‘-1-0-1-0-1-0-1-’			addressed block.
						Erase Error due to the
						currently addressed block
2	Toggle Bit					(when DQ5 = ‘1’)	Indicates the erase status and allows to
							identify the erased block.
						Program on-going, Erase
				‘1’		on-going on another block or
						Erase Complete
			DQ			Erase Suspend read on non
						Erase Suspend block
1	Reserved
0	Reserved

Note: 1. Logic level ‘1’ is High, ‘0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.

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