ST M36L0R7050T0, M36L0R7050B0 User Manual

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128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory

32 Mbit (2M x16) PSRAM, 1.8V Supply Multi-Chip Package

FEATURES SUMMARY

■ MULTI-CHIP PACKAGE

– 1 die of 128 Mbit (8Mb x16, Multiple Bank,

Multi-level, Burst) Flash Memory

– 1 die of 32 Mbit (2Mb x16) Asynchronous

Pseudo SRAM

■ SUPPLY VOLTAGE

–V
–V

■ ELECTRONIC SIGNATURE

= V

DDF

= 9V for fast program (12V tolerant)

PPF

– Manufacturer Code: 20h
– Device Code (Top Flash Configuration)

M36L0R7050T0: 88C4h

– Device Code (Bottom Flas h

Configuration) M36L0R7050B0: 88C5h

■ PACKAGE

– Compliant with Lead-Free Soldering

Processes

– Lead-Free Versions

FLASH MEMORY

■ SYNCHRONOUS / ASYNCHRONOUS READ

– Synchronous Burst Read mode: 54MHz
– Asynchronous Page Read mode
– Random Access: 85ns

■ SYNCHRONOUS BURST READ SUSPEND

■ PROGRAMMING TIME

– 10µs typical Word program time using

Buffer Program

■ MEMORY ORGANIZATION

– Multiple Bank Memory Array: 8 Mbit

Banks

– Parameter Blocks (Top or Bottom

location)

■ DUAL OPERATIONS

– program/erase in one Ban k whi le read in

others

– No delay between read and write

operations

■ SECURITY

– 64 bit unique device number
– 2112 bit user programmable OTP Cells

DDP

= V

= 1.7 to 1.95V

DDQ

M36L0R7050T0

M36L0R7050B0

Figure 1. Package

FBGA

TFBGA88 (ZAQ)

8 x 10mm

■ BLOCK LOCKING

– All blocks lock ed at power -up
– Any combination of blocks can be locked

with zero latency
–WP
– Absolute Write Protection with V

■ COMMON FLASH INTERFACE (CFI)

■ 100,000 PROGRAM/ERASE CYCLES per

BLOCK

PSRAM

■ ACCESS TIME: 85ns

■ LOW STANDBY CURRENT: 100µA

■ DEEP POWER-DOWN CURRENT: 10µA

■ BYTE CONTROL: UB

■ PROGRAMMABLE PARTIAL ARRAY

■ 8 WORD PAGE ACCESS CAPABILITY: 25ns

■ PARTIAL POWER-DOWN MODES

– Deep Power-Down
– 4 Mbit Partial Power-Down
– 8 Mbit Partial Power-Down
– 16 Mbit Partial Power-Down

for Block Lock-Down

F

/LB

P

= V

PPF

P

SS

1/18December 2004

M36L0R7050T0, M36L0R7050B0

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Address Inputs (A0-A22). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Flash Chip Enable (E
Flash Output Enable (G
Flash Write Enable (W
Flash Write Protect (WP
Flash Reset (RP
Flash Latch Enable (L
Flash Clock (K

F

Flash Wait (WAIT
PSRAM Chip Enable (E1
PSRAM Chip Enable (E2
PSRAM Output Enable (G
PSRAM Write Enable (W
PSRAM Upper Byte Enable (UB
PSRAM Lower Byte Enable (LB
V

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

DDF

V

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

DDP

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

V

DDQ

V

Program Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

PPF

Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

V

SS

).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

F

).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

F

).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

F

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

F

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

F

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

F

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

F

).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

P

).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

P

).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

P

).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

P

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

P

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

P

FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 2. Main Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

FLASH MEMORY DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

PSRAM DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 3. Power-Down Configuration Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2/18

M36L0R7050T0, M36L0R7050B0

Table 4. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 5. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 6. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 6. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 7. Flash Memory DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 8. Flash Memory DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 9. PSRAM DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 7. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Bottom View Outline15

Table 10. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Data. . . . . 15

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 11. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3/18

M36L0R7050T0, M36L0R7050B0

SUMMARY DESCRIPTION

The M36L0R7050T0 and M36L0R7050B0 com­bine two memory devices in a Multi-Chip Package:
a 128-Mbit, Multiple Bank Flash memory, the
M30L0R7000T0 or M30L0R7000B0, and a 32­Mbit PseudoSRAM, the M69AR048B. Recom­mended operating conditions do not allow more
than one memory to be active at the same time.

The memory is offered in a Stacked TFBGA88
(8x10mm, 8x10 ball array, 0.8mm pitch) package.

In addition to the stan dard version, the pac kages
are also available in Lead- free version , in comp li­ance with JEDEC Std J-STD-020 B, the ST ECO­PACK 7191395 Specification, and the RoHS
(Restriction of Hazardous Substances) directive.

All packages are c omp lia nt with Le ad- fr ee so ld er ­ing processes.

The memory is supplied with all the bits erased
(set to ‘1’).

Table 1. Signal Names

A0-A22

(1)

DQ0-DQ15 Common Data Input/Output
V

DDF

V

DDQ

V

PPF

V

SS

V

DDP

NC Not Connected Internally
DU Do Not Use as Internally Connected

Address Inputs

Power Supply for Flash Memory
Flash Memory Power Supply for I/O

Buffers
Flash Optional Supply Voltage for Fast

Program and Erase
Ground
PSRAM Power Supply

Figure 2. Logic Diagram

V

DDQ

V

DDF

23

A0-A22

E

F

G

F

W

F

RP

F

WP

E1

E2

UB

LB

G
W

F

L

F

K

F

P

P

P

P

P

P

M36L0R7050T0

M36L0R7050B0

Flash Memory

L

V

PPF

V

DDP

16

DQ0-DQ15

WAIT

F

F

E

F

G

F

W

F

RP

F

WP
K

F

WAIT

F

F

Latch Enable Input
Chip Enable Input
Output Enable Input
Write Enable Input
Reset Input
Write Protect Input
Burst Clock
Wait Data in Burst Mode

PSRAM

E1

P

G

P

W

P

E2

P

UB

P

LB

P

Note: 1. A22-A21 are not connected to the PSRAM component.

Chip Enable Input
Output Enable Input
Write Enable Input
Power-down Input
Upper Byte Enable Inp ut
Lower Byte Enable Inp ut

4/18

V

SS

AI08731

Figure 3. TFBGA Connections (Top view through package)

M36L0R7050T0, M36L0R7050B0

87654321

A

B A21

C

D

E

F

G

H

DU

A4

A5

A3

A2

A1

A0

G

DU

A19A18

LB

P

A6

P

NC

NCA17

NCA7

UB

DQ2DQ8

DQ1DQ0

V

SS

V

SS

V

PPF

WP

RP

P

DQ10

DQ3

V

DDF

NC

W

P

L

F

F

F

W

F

DQ5

DQ12

NC

K

F

E

P

DQ13

DU

A22

A9

A10A20

A14A8

WAIT

DQ7DQ14

DU

A11

A12

A13

A15

A16

NC

F

NC

J

K

L

M

V

NC

E

DU

SS

DQ9G

F

F

DU DU NC

V

SS

DU

V

DDQ

DQ11

V

DDF

V

V

DDP

SS

NC

V

SS

DQ15DQ6DQ4

V

V

DDQ

SS

DU

V

E2

V

DDQ

P

SS

DU

AI08732

5/18

M36L0R7050T0, M36L0R7050B0

SIGNAL DESCRIPTIONS

See Figure 2., Logic Diagram and Table 1., Signal

Names, for a brief overview of the signals connect-

ed to this device.
Address Inputs (A0-A22). Addresses A0-A20

are common inputs fo r th e Fl as h Mem ory an d the
PSRAM components. The other lines (A21-A22)
are inputs for the Flash Memory components only.

The Address Inputs select the cells in the memory
array to access during Bus Read operations. Dur­ing Bus Write operations they control the com­mands sent to the Command Interface of the Flash
memory Program/Eras e Controller or they select
the cells to access in the PSRAM.

The Flash memory component is accessed
through the Chip Enable s ignal (E
the Write Enable (W

) signal, while the PSRAM is

F

accessed through two Chip E nable signals (E1
and E2P) and the Write Enable signal (WP).

Data Input/Output (DQ0-DQ15). In the Flash
memory the Data I/O outputs the data stored at the
selected address du ring a Bus Read operati on or
inputs a command or the data to be pro grammed
during a Write Bus operation.

In the PSRAM the Lower Byte Data Inputs/Out­puts, DQ0-DQ7, carry the data to or from the lower
part of the selected address during a Write or
Read operation, when Lower Byte Enable (LB
driven Low.
The Upper Byte Data Inputs/Outputs, DQ8-DQ15,
carry the data to or from the upper part of the se­lected address dur ing a Write or Rea d operation,
when Upper Byte Enable (UB

Flash Chip Enable (E

). The Chip Enable input

F

activates the memory cont rol logic, input buffers,
decoders and sense amplifiers. When Chip En­able is Low, V

, and Reset is High, VIH, the device

IL

is in active mode. W hen Chi p E nab le i s at V
Flash memory is deselect ed, the out puts ar e high
impedance and the power consumption is reduced
to the standby level.

Flash Output Enable (G

). The Output Enable

F

input controls data output during Flash memory
Bus Read operations.

Flash Write Enable (

W

). The Write Enable

F

controls the Bus Write operation of the Flash
memories’ Command Int erface. The data an d ad­dress inputs are latched on the rising edge of Chip
Enable or Write Enable whichever occurs first.

Flash Write Protect (WP

). Write Protect is an

F

input that gives an additio nal hardware protection
for each block. When Write Protect is Low, V
Lock-Down is enabled and the protection status of
the Locked-Down blocks cannot be changed.
When Write Protect is a t High, V
disabled and the Locked-Down blocks can be

) and through

F

) is driven Low.

P

, Lock-Down is

IH

IH

) is

P

the

IL

locked or unlocked. (See the Lock Status Table in
the M30L0R7000T0 datasheet).

Flash Reset (RP

). The Reset input prov ides a

F

hardware reset of the m emory. When Reset is at

, the memory is in Reset mode: the outputs are

V

IL

high impedance and the current consumption is
reduced to the Reset Supply Current I

Table 7.,Flash Memory DC Characteristics - Cur­rents, for th e value o f I

. After Reset all b locks

DD2

are in the Locked state and the Configuration Reg­ister is reset. When Reset is at V

, the device is in

IH

normal operation. Exiti ng Reset mode the devic e
enters Asynchronous Read mode, but a nega tive
transition of Chip Enable or Latch Enable is re­quired to ensure valid data outputs.

The Reset pin can be interfaced with 3V logic with­out any additional circui try. It can be tied to V

P

(refer to Table 8., Flash Memory DC Characteris-

tics - Voltages).

Flash Latch Enable (L

). Latch Enable latches

F

the address bits on its rising edge. The address
latch is transparent when Latch Enable is Low, V
and it is inhibited when Latch Enable i s H igh , V
Latch Enable can be kept Low (also at board level)
when the Latch Enable func tion is not requ ired or
supported.

Flash Clock (K

). The Clock input sy nchronizes

F

the Flash memory to the microcontroller during
synchronous read operations; the address is
latched on a Clock edge (r ising o r falling, accord­ing to the configurat ion settings) when Latch En ­able is at V

. Clock is don't care during

IL

Asynchronous Read and in write operations.

Flash Wait (WAIT

). WAIT is a Flash output sig-

F

nal used during Synchronous Read to indicate
whether the data on the output bus are valid. This
output is high impedance when Flash Chip Enable
is at V

or Flash Reset is at VIL. It can be config-

IH

ured to be active during the wait cycle or one clock
cycle in advance. The WA IT

signal is not gated

F

by Output Enable.

PSRAM Chip Enable (E1

(Low), the Chip Enable, E1

). When asserted

P

, activates the memo-

P

ry state machine, address buffers and decod ers,
allowing Read and Write operations to be per­formed. When de-asserted (High), all other pins
are ignored, and the device is put, automatically, in
low-power Standby mode.

It is not allowed to set E
at V

at the same time.

IH

PSRAM Chip Enable (E2

,

, puts the device in Power-down mode (Deep

E2

P

at V

F

E1P at VIL and E2

IL,

). The Chip Enable,

P

Power-Down or a Partial Power-Down mode)
when it is drive n Low. De ep Po wer- down m ode i s
the lowest power mode.

DD2

. Refer to

RPH

IL

IH

,
.

P

6/18

M36L0R7050T0, M36L0R7050B0

It is not allowed to set EF at V
at V

at the same time.

IH

PSRAM Output Enable (G

able, G

, provides a h igh speed tri-state c ontrol,

P

E1P at VIL and E2

IL,

). The Output En-

P

allowing fast read/write cycles to be achieved with
the common I/O data bus.

PSRAM Write Enable (W

, controls the Bus Write operation of the device.

W

P

PSRAM Upper Byte Enable (UB

Byte Enable, UB

, gates the data on the Upper

P

). The Write Enable,

P

). The Upper

P

Byte Data Inputs/Outp uts (DQ8-DQ15) t o or from
the upper part of the selected address during a
Write or Read operation.

PSRAM Lower Byte Enable (LB

Byte Enable, LB

, gates the data on the Lower

P

). The Lower

P

Byte Data Inputs/Outputs (DQ0-DQ7) to or from
the lower part of the selected address during a
Write or Read operation.

V

Supply Voltage. V

DDF

provides the power

DDF

supply to the internal cores of the Flash memory
component. It is the main power supply for all
Flash operations (Read, Program and Erase).

V

Supply Voltage. The V

DDP

Supply Volt-

DDP

age supplies the power f or al l PS RAM o peration s
(Read, Write, etc.) and for driving the refresh logic,
even when the device is not being accessed.

V

Supply Voltage. V

DDQ

provides t he power

DDQ

supply for the Flash Memory I/O pins. This allows
all Outputs to be powered independently of the
Flash Memory core power supply, V

DDF

.

P

PPF

PPF

Program Supply Voltage. V

V

Flash control input and a Flas h power su pply pin.
The two functions are selected by the voltage
range applied to the pin.

If V
V
age lower than V

is kept in a low voltage range (0V to V

PPF

is seen as a control input. In this case a volt-

PPF

gives an absolute pr otec-

PPLKF

tion against Program or Erase, while V
enables these functions (see Tables 7 an d 8, DC
Characteristics for the relevant values). V
only sampled at the beginning of a Program or
Erase; a change in its value after the operation has
started does not have any effec t and Program or
Erase operations continue.

If V
supply pin. In th is condition V

is in the range of V

PPF

it acts as a power

PPHF

must be stable

PPF

until the Program/Erase algorithm is completed.

Ground. VSS is the common ground refer-

V

SS

ence for all voltage measurements in the Flash
(core and I/O Buffers) and PSRAM chips.

Note: Each Flash memory device in a system
should have their supply voltage (V
the program supply voltage V

PPF

with a 0.1µF ceramic capacitor close to the pin
(high frequency, inherently low inductance ca­pacitors should be as close as possible to the
package). See Figure 6., AC Measurement

Load Ci rcui t. The PCB track widths should be

sufficient to carry the required V
and erase currents.

is both a

DDQ

> V

PPF

DDF

PP1F

PPF

) and

decoupled

program

PPF

)

is

7/18

M36L0R7050T0, M36L0R7050B0

FUNCTIONAL DESCRIPTION

The PSRAM and Flash memory components have
separate power supplies but share the same
grounds. They are distinguished by three Chip En­able inputs: E

for the PSRAM.

E2

P

Recommended operating conditions do not allow
more than one device to be ac tive at a time. The

Figure 4. Functional Block Diagram

for the Flash memory and E1P and

F

most common example is simultaneous read oper­ations in the Flash memory and the PSRAM which
would result in a data bu s c ont enti on . T herefo re it
is recommended to put the other device in the high
impedance state when reading the selected de­vice.

A21-A22

A0-A20

W

RP

WP

E1
G
W
E2
UB
LB

128 Mbit

Flash

Memory

32 Mbit

PSRAM

V

DDQ

DQ0-DQ15

WAIT

F

V

DDFVPPF

E

F

G

F
F

F
F

L

F

K

F

V

DDP

P

P

P

P

P

P

8/18

V

SS

AI08733

M36L0R7050T0, M36L0R7050B0

Table 2. Main Operating Modes

E

Operation

Flash Read

Flash Write

Flash Address
Latch

Flash Output
Disable

Flash Standby

GFW

F

V

ILVILVIH

V

ILVIHVIL

V

X

IL

V

ILVIHVIH

V

XX X

IH

Flash Reset X X X X

F

V

IHVIL

LFRP

(2

V

IL

)

(2

V

IL

)

X

F

V

IH

V

IH

V

IH

V

IH

V

IH

V

IL

PSRAM Read

Flash Memory must be disabled

PSRAM Write

Output Disable

PSRAM
Standby

Any Flash mode is allowed

(Deselected)
PSRAM Power-

Down

Note: 1. X = Don't care.

2. L

can be tied to VIH if the valid address has been previous ly latched.

F

3. Depends on G

4. WAIT signal polarity is configured using the Set Confi guration Register command. See the M30L0R7000T0 datasheet for details.

.

F

(4)

WAIT

E1PE2PGPWPLBPUB

F

P

DQ15-DQ0

Flash Data Out

PSRAM must be disabled

Flash Data In

Flash Data Out

Hi-Z Hi-Z

Any PSRAM mode is allowed

Hi-Z Hi-Z

V

V

V

IL

IH

V

V

IL

IH

V

V

IL

IH

V

V

IL

IH

V

V

IL

IH

V

V

IL

IH

V

V

IL

IH

V

V

IL

IH

V

V

IH

IH

V

X

IL

V

IL

IHVIHVIL

V

V

IL

IHVILVIH

V

V

IL

IHVILVIL

V

VILV

IH

V

VILV

IH

V

VILV

IH

V

V

IL

V

VILV

IH

IHVIL

ILVIH

ILVIL

IHVIHVIH

IHVIH

XXXX Hi-Z

XXXX Hi-Z

Upper Byte

Lower Byte

Word Read

Upper Byte

Lower Byte

Word Write

or Hi-Z

Hi-Z

data out

data out

data in

data in

Hi-Z

(3)

9/18

M36L0R7050T0, M36L0R7050B0

FLASH MEMORY DEVICE

The M36L0R7050T0 and M36L0R7050B0 contain
a 128 Mbit Flash memory. For detailed information
on how to use the devices, see the

M30L0R7000(T/B)0 datas heet which is available
from the internet site

http://www.st.com

or from

your local STMicroelectronics distributor.

PSRAM DEVICE

The M36L0R7050T0 and M36L0R7050B0 contain
a 32 Mbit PSRAM. This device can be placed in a
number of sleep and partial sleep modes (see Ta-

ble 3.). For detailed information on how to use the

Table 3. Power-Down Configuration Data

Mode

Deep Power-Down (default)0011
4Mb Partial Power-Down0010
8Mb Partial Power-Down0001
16Mb Partial Power-Down0000

DQ15–DQ9 DQ8-DQ2 DQ1 DQ0

device, see the M69A R048B datasheet which is
available from the int ernet site

http://www.st.com

or from your local STMicroelectronics distributor.

Power-Down Configuration Data

10/18

M36L0R7050T0, M36L0R7050B0

MAXIMUM RATING

Stressing the device above the ra ting l isted in the
Absolute Maximum Ratin gs table ma y cause per ­manent damage to the device. Thes e are stress
ratings only and operation of the device at these or
any other conditions abo ve those indica ted in the
Operating sections of this specification is not im-

Table 4. Absolute Maximum Ratings

Symbol Parameter

T

A

T

BIAS

T

STG

T

LEAD

V

IO

V

, V

DDF

DDQ

V

DDP

V

PPF

I

O

t

VPPFH

Note: 1. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK® 7191395 specification,

and the European directive on Restr i ctions on Hazardous Substances (RoHS) 2002/95/EU.

Ambient Operatin g Temperature –25 85 °C
Temperature Under Bias –25 85 °C
Storage Temperature –55 125 °C
Lead Temperature during Soldering
Input or Output Voltage –0.5 3.6 V

,

Core and Input/Output Supply Voltages –0.2 2.5 V

Flash Program Voltage –0.2 14 V
Output Short Circuit Current 100 mA
Time for V

PPF

at V

PPFH

plied. Exposu re to Abso lute Max imum Rati ng con­ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and o ther relevant quality docu­ments.

Value

Min Max

(1)

100 hours

Unit

°C

11/18

M36L0R7050T0, M36L0R7050B0

DC AND AC PARAMETERS

This section summ arizes the operating measure­ment conditions, and th e DC and AC c haracteris ­tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement

Table 5. Operating and AC Measurement Conditions

Parameter

V

Supply Voltage

DDF

Supply Voltage

V

DDP

Supply Voltage

V

DDQ

V

Supply Voltage (Factory

PPF

environment)

V

Supply Voltage (Application

PPF

environment)
Ambient Operating Temperature –25 85 –30 85 °C
Load Capacitance (C
Output Circuit Resisto rs (R

)

L

, R2)

1

Input Rise and Fall Times 5 5 ns
Input Pulse Voltages
Input and Output Timing Ref. Voltages

Min Max Min Max

1.7 1.95 – – V
––1.71.95V

1.7 1.95 – – V

8.5 12.6 – – V

–0.4

Conditions summarized in Table 5., Operating and

AC Measurement Conditions. Designers should

check that the operating conditi ons in their circuit
match the operating conditions when relying on
the quoted parameters.

Flash Memory PSRAM

+0.4

V

DDQ

30 50 pF

16.7 16.7 kΩ

0 to V

DDQ

V

/2 V

DDQ

––V

0 to V

DDQ

/2

DDQ

Unit

V
V

Figure 5. AC Measurement I/O Waveform

V

DDQ

V

0V

Note: V

DDQ

= V

DDP

.

DDQ

AI06161

/2

Figure 6. AC Measurement Load Circuit

V

DDQ

V

0.1µF

DDF

0.1µF

V

DDQ

DEVICE
UNDER

TEST

includes JIG capacitance

C

L

CL

Table 6. Device Capacitance

Symbol Parame te r Test Condition Min Max Unit

V

V

OUT

IN

= 0V

= 0V

12 pF
15 pF

C

IN

C

OUT

Note: Sampled only, not 100% tested.

Input Capacitance
Output Capacitance

R

1

R

2

AI08364B

12/18

M36L0R7050T0, M36L0R7050B0

Table 7. Flash Memory DC Characteristics - Currents

Symbol Parameter Test Condition Min Typ Max Unit

I

Input Leakage Current

LI

I

Output Leakage Curr en t

LO

Supply Current
Asynchronous Read (f=6MHz)

Supply Current
Synchronous Read (f=40MHz)

I

DD1

Supply Current
Synchronous Read (f=54MHz)

I

DD2

I

DD3

I

DD4

Supply Current
(Reset)

Supply Current (Standby)
Supply Current (Automatic

Standby)

Supply Current (Prog ram )

(1)

I

DD5

Supply Current (Erase )

Supply Current

(1,2)

I

DD6

I

DD7

I

PP1

I

PP2

I

PP3

Note: 1. Sampled only, not 100% tested.

(Dual Operations)

Supply Current Progr am / Eras e

(1)

Suspended (Standby)

V

Supply Current (Progr am )

PPF

(1)

Supply Current (Erase )

V

PPF

V

Supply Current (Read ) V

PPF

(1)

V

Supply Current (Standby) V

PPF

2. V

Dual Operation current is the sum of read and program or erase currents.

DDF

0V ≤ V

0V ≤ V

E

F

≤ V

IN

DDQ

≤ V

OUT

= VIL, GF = V

DDQ

±1 µA
±1 µA

IH

10 15 mA

4 Word 7 16 mA
8 Word 10 18 mA

16 Word 13 20 mA

Continuous 18 25 mA

4 Word 16 18 mA
8 Word 18 20 mA

16 Word 21 25 mA

Continuous 22 27 mA

= VSS ± 0.2V

RP

F

E

= V

F

DDF

= VIL, GF = V

E

F

= V

V

PPF

V

= V

PPF

V

= V

PPF

V

= V

PPF

± 0.2 V

IH

PPH

DDF

PPH

DDF

25 70 µA

25 70 µA

25 70 µA

815mA

10 20 mA

815mA

10 20 mA

Program/Erase in one

Bank, Asynchronous

20 35 mA

Read in another Bank
Program/Erase in one

Bank, Synchronous

32 47 mA

Read in another Bank

= V

PPF

PPF

PPF

PPF

PPF

PPF

DDF

= V
= V
= V
= V

≤ V
≤ V

± 0.2 V

PPH

DDF

PPH

DDF

DDF

DDF

25 70 µA

25mA

0.2 5 µA
25mA

0.2 5 µA

0.2 5 µA

0.2 5 µA

E

F

V
V
V
V

13/18

M36L0R7050T0, M36L0R7050B0

Table 8. Flash Memory DC Characteristics - Voltages

Symbol Parameter Test Condition Min Typ Max Unit

V

V
V
V

V

V

V

PPLK

V
V

Table 9. PSRAM DC Characteristics

Symbol Parameter Test Condition Min Max Unit

I

I

I

I

CCPD

I

CCP4

I

CCP8

I

CCP16

V
V

V

V

Note: 1. Maximum DC voltage on input and I/O pins is V

Input Low Voltage –0.5 0.4 V

IL

V

Input High Voltage

IH

Output Low Voltage

OL

Output High Voltage

OH

V

PP1

PPH

PPF

V

PPF

Program Voltage-Logic

Program Voltage Factory

I

= 100µA

OL

I

= –100µA V

OH

Program, Erase 1.1 1.8 3.3 V
Program, Erase 8.5 9.0 12.6 V

–0.4 V

DDQ

–0.1

DDQ

Program or Erase Lockout 0.4 V
V

LKO

RPH

CC1

CC2

CC3

Lock Voltage

DDF

RPF pin Extended High Voltage

V

Active Current

DDP

V

Page Read Current

DDP

= 1.95V,

V

DDP

V

= VIH or VIL,

IN

E1P = VIL and E2P = VIH,

I

= 0mA

OUT

= 1.95V,

V

DDP

V

= VIH or VIL,

IN

E1P = VIL and E2P = VIH,

I

= 0mA, t

OUT

PRC

1V

/ tWC =

t

RC

minimum

tRC / tWC =

1 µs

= min.

Deep Power-

Down

V

= 1.95V,

V

Power-Down Current

DDP

I

Input Leakage Current

LI

I

I

IH

Output Leakage Curr en t

LO

Standby Supply Current CMOS

SB

(1)

Input High Voltage

(2)

Input Low Voltage –0.3

IL

Output High Voltage

OH

Output Low Voltage

OL

During voltage transitions, input may positive overshoot to V

2. Minimum DC voltage on input or I/O pins is –0.3V.
During voltage transitions, input may positive overshoot to V

VIN = VIH or VIL,

DDP

DDP

E2

≤ 0.2V

P

0V ≤ V

0V ≤ V

V

DDP

≤ V

IN

≤ V

OUT

= 1.95V,

VIN ≤ 0.2V or VIN ≥ V

E1

= E2P ≥ V

P

V

= 1.65V, IOH = –0.5mA

DDP

+0.2V.

DDP

SSP

DDP

I

= 1mA

OL

+ 1.0V for a period of up to 5ns.

+ 1.0V for a period of up to 5ns.

4Mb Partial
8Mb Partial

16Mb Partial

DDP

DDP

–0.2V,

DDP

–0.2V

(3)

(3)

(3)

–1 1 µA
–1 1 µA

0.8V

DDPVDDP

1.4 V

+ 0.4

DDQ

0.1 V

3.3 V

25 mA

3mA

10 mA

10 µA

40 µA
50 µA
65 µA

100 µA

+ 0.2

0.2V

DDP

0.4 V

V

V

V
V

14/18

M36L0R7050T0, M36L0R7050B0

PACKAGE MECHANICAL

Figure 7. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Bottom View Outline

D

D1

e

b

ddd

A2

A1

BGA-Z42

E

E2

Note: Drawing is not to scale.

E1

FE FE1

SE

BALL "A1"

A

FD

SD

Table 10. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Data

Symbol

Typ Min Max Typ Min Max

A 1.200 0.0472
A1 0.200 0.0079
A2 0.850 0.0335

b 0.350 0.300 0.400 0.0138 0.0118 0.0157

D 8.000 7.900 8.100 0.3150 0.3110 0.3189
D1 5.600 0.2205

ddd 0.100 0.0039

E 10.000 9.900 10.100 0.3937 0.3898 0.3976
E1 7.200 0.2835
E2 8.800 0.3465

e 0.800 – – 0.0315 – –
FD 1.200 0.0472
FE 1.400 0.0551

FE1 0.600 0.0236

SD 0.400 0.0157

SE 0.400 0.0157

millimeters inches

15/18

M36L0R7050T0, M36L0R7050B0

PART NUMBERING

Table 11. Ordering Information Scheme

Example: M36 L 0 R 7 0 5 0 T 0 ZAQ T

Device Type

M36 = Multi-Chip Package (Multiple Flash + RAM)

Flash 1 Architecture

L = Multilevel, Multiple Bank, Burst mode

Flash 2 Architecture

0 = No Die

Operating Voltage

R = V

Flash 1 Density

7 = 128 Mbit

Flash 2 Density

0 = No Die

DDF1

= V

DDP

= V

= 1.7 to 1.95V

DDQ

RAM 1 Density

5 = 32 Mbit

RAM 0 Density

0 = No Die

Parameter Blocks Location

T = Top Boot Block Flash
B = Bottom Boot Block Flash

Product Version

0 = 0.13µm Flash technology, 85ns speeds;

0.18µm RAM, 85ns speed

Package

ZAQ = Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch

Option

Blank = Standard Packing
T = Tape & Reel Packing
E= Lead-free and RoHS package, standard packing
F= Lead-free and RoHS package, tape and reel packing

Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available op­tions (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST­Microelectronics Sales Office nearest to you.

16/18

REVISION HISTORY

Table 12. Document Revision History

Date Version Revision Details

29-Jul-2003 0.1 First Issue

Package specifications updated. PSRAM component updated in accordance with

03-Jun-2004 0.2

04-Dec-2004 1.0

M69AR048B datasheet. Flash memory component updated in accordance with
M30L0R7000(T/B)0 datasheet.
Document status changed from Target Specification to Preliminary Data.

TFBGA88 package fully compliant with the ST ECOPACK specification.
Document status prom ote d from Pre lim ina ry Da ta to full Datashe et .
Flash memory and PSRAM data updated to the version 1.0 of the M30L0R7000x0
datasheet and to the version 4.0 of the M69AR048B datasheet.

M36L0R7050T0, M36L0R7050B0

17/18

M36L0R7050T0, M36L0R7050B0

Information furnished is be lieved to be a ccur ate and reli able. Howe ver, STMicroele ctronic s assu mes no r esponsib ilit y for th e consequences
of use of such information nor for any infrin gement of patent s or other rights of third parties which ma y result from it s use. No license is granted

by implication or otherwi se under any patent or patent rights of STMicroelectronics. Spec ifications mentioned in this publication are subjec t

to change without not ice. This pub licat ion su persed es and repl aces all in format ion previou sly su pplie d. STMicroele c tronic s prod ucts ar e no t

authorized for use as critical compone nts in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

ECOPACK is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners

© 2004 STMicroelectronics - All rights reserved

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18/18