ST M36L0R7050T0, M36L0R7050B0 User Manual

M36L0R7050

M36L0R7050T0

M36L0R7050B0

128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory 32 Mbit (2M x16) PSRAM, 1.8V Supply Multi-Chip Package

FEATURES SUMMARY

■ MULTI-CHIP PACKAGE Figure 1. Package

–1 die of 128 Mbit (8Mb x16, Multiple Bank, Multi-level, Burst) Flash Memory

–1 die of 32 Mbit (2Mb x16) Asynchronous Pseudo SRAM

■SUPPLY VOLTAGE

–VDDF = VDDP = VDDQ = 1.7 to 1.95V

–VPPF = 9V for fast program (12V tolerant)

■ELECTRONIC SIGNATURE

–Manufacturer Code: 20h

–Device Code (Top Flash Configuration) M36L0R7050T0: 88C4h

–Device Code (Bottom Flash Configuration) M36L0R7050B0: 88C5h

■PACKAGE

–Compliant with Lead-Free Soldering Processes

–Lead-Free Versions

FLASH MEMORY

■SYNCHRONOUS / ASYNCHRONOUS READ

–Synchronous Burst Read mode: 54MHz

–Asynchronous Page Read mode

–Random Access: 85ns

■SYNCHRONOUS BURST READ SUSPEND

■PROGRAMMING TIME

–10µs typical Word program time using Buffer Program

■MEMORY ORGANIZATION

–Multiple Bank Memory Array: 8 Mbit Banks

–Parameter Blocks (Top or Bottom location)

■DUAL OPERATIONS

–program/erase in one Bank while read in others

–No delay between read and write operations

■SECURITY

–64 bit unique device number

–2112 bit user programmable OTP Cells

FBGA

TFBGA88 (ZAQ) 8 x 10mm

■BLOCK LOCKING

–All blocks locked at power-up

–Any combination of blocks can be locked with zero latency

–WPF for Block Lock-Down

–Absolute Write Protection with VPPF = VSS

■COMMON FLASH INTERFACE (CFI)

■100,000 PROGRAM/ERASE CYCLES per BLOCK

PSRAM

■ACCESS TIME: 85ns

■LOW STANDBY CURRENT: 100µA

■DEEP POWER-DOWN CURRENT: 10µA

■BYTE CONTROL: UBP/LBP

■PROGRAMMABLE PARTIAL ARRAY

■8 WORD PAGE ACCESS CAPABILITY: 25ns

■PARTIAL POWER-DOWN MODES

–Deep Power-Down

–4 Mbit Partial Power-Down

–8 Mbit Partial Power-Down

–16 Mbit Partial Power-Down

December 2004

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M36L0R7050T0, M36L0R7050B0

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Address Inputs (A0-A22). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Flash Chip Enable (EF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Flash Output Enable (GF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Flash Write Enable (WF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Flash Write Protect (WPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Flash Reset (RPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Flash Latch Enable (LF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Flash Clock (KF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Flash Wait (WAITF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PSRAM Chip Enable (E1P).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PSRAM Chip Enable (E2P).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PSRAM Output Enable (GP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

PSRAM Write Enable (WP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

PSRAM Upper Byte Enable (UBP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

PSRAM Lower Byte Enable (LBP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

VDDF Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

VDDP Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

VDDQ Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

VPPF Program Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

VSS Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2. Main Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

FLASH MEMORY DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PSRAM DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 3. Power-Down Configuration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

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M36L0R7050T0, M36L0R7050B0

Table 4. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 5. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 6. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 7. Flash Memory DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 8. Flash Memory DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 9. PSRAM DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 7. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Bottom View Outline15 Table 10. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Data. . . . . 15

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 11. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

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M36L0R7050T0, M36L0R7050B0

SUMMARY DESCRIPTION

The M36L0R7050T0 and M36L0R7050B0 combine two memory devices in a Multi-Chip Package: a 128-Mbit, Multiple Bank Flash memory, the M30L0R7000T0 or M30L0R7000B0, and a 32Mbit PseudoSRAM, the M69AR048B. Recommended operating conditions do not allow more than one memory to be active at the same time.

The memory is offered in a Stacked TFBGA88 (8x10mm, 8x10 ball array, 0.8mm pitch) package.

In addition to the standard version, the packages are also available in Lead-free version, in compliance with JEDEC Std J-STD-020B, the ST ECOPACK 7191395 Specification, and the RoHS (Restriction of Hazardous Substances) directive.

All packages are compliant with Lead-free soldering processes.

The memory is supplied with all the bits erased (set to ‘1’).

Figure 2. Logic Diagram

VDDQ	VPPF
VDDF	VDDP
23	16

A0-A22

EF	DQ0-DQ15
GF	WAITF
WF
RPF

WPF M36L0R7050T0

M36L0R7050B0

LF

KF

E1P

GP

WP

E2P

UBP

LBP

VSS

AI08731

4/18

Table 1. Signal Names

	A0-A22 (1)									Address Inputs
	DQ0-DQ15									Common Data Input/Output
	VDDF									Power Supply for Flash Memory
	VDDQ									Flash Memory Power Supply for I/O
										Buffers
	VPPF									Flash Optional Supply Voltage for Fast
										Program and Erase
	VSS									Ground
	VDDP									PSRAM Power Supply
	NC									Not Connected Internally
	DU									Do Not Use as Internally Connected
	Flash Memory
		F
	L									Latch Enable Input
			F
	E									Chip Enable Input
					F
	G									Output Enable Input
						F
	W									Write Enable Input
								F
	RP									Reset Input
									F
	WP									Write Protect Input
	KF									Burst Clock
	WAITF									Wait Data in Burst Mode
	PSRAM
							P
	E1									Chip Enable Input
					P
	G									Output Enable Input
						P
	W									Write Enable Input
	E2P									Power-down Input
								P
	UB									Upper Byte Enable Input
							P
	LB									Lower Byte Enable Input

Note: 1. A22-A21 are not connected to the PSRAM component.

M36L0R7050T0, M36L0R7050B0

Figure 3. TFBGA Connections (Top view through package)

	1	2	3	4	5	6	7	8
A	DU	DU					DU	DU
B	A4	A18	A19	VSS	VDDF	NC	A21	A11
C	A5	LBP	NC	VSS	NC	KF	A22	A12
D	A3	A17	NC	VPPF	WP	EP	A9	A13
E	A2	A7	NC	WPF	LF	A20	A10	A15
F	A1	A6	UBP	RPF	WF	A8	A14	A16
G	A0	DQ8	DQ2	DQ10	DQ5	DQ13	WAITF	NC
H	GP	DQ0	DQ1	DQ3	DQ12	DQ14	DQ7	NC
J	NC	GF	DQ9	DQ11	DQ4	DQ6	DQ15	VDDQ
K	EF	DU	DU	NC	VDDP	NC	VDDQ	E2P
L	VSS	VSS	VDDQ	VDDF	VSS	VSS	VSS	VSS
M	DU	DU					DU	DU

AI08732

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Flash Write Enable (WF

M36L0R7050T0, M36L0R7050B0

SIGNAL DESCRIPTIONS

See Figure 2., Logic Diagram and Table 1., Signal Names, for a brief overview of the signals connected to this device.

Address Inputs (A0-A22). Addresses A0-A20 are common inputs for the Flash Memory and the PSRAM components. The other lines (A21-A22) are inputs for the Flash Memory components only.

The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Flash memory Program/Erase Controller or they select the cells to access in the PSRAM.

The Flash memory component is accessed through the Chip Enable signal (EF) and through the Write Enable (WF) signal, while the PSRAM is accessed through two Chip Enable signals (E1P and E2P) and the Write Enable signal (WP).

Data Input/Output (DQ0-DQ15). In the Flash memory the Data I/O outputs the data stored at the selected address during a Bus Read operation or inputs a command or the data to be programmed during a Write Bus operation.

In the PSRAM the Lower Byte Data Inputs/Outputs, DQ0-DQ7, carry the data to or from the lower part of the selected address during a Write or Read operation, when Lower Byte Enable (LBP) is driven Low.

The Upper Byte Data Inputs/Outputs, DQ8-DQ15, carry the data to or from the upper part of the selected address during a Write or Read operation, when Upper Byte Enable (UBP) is driven Low.

Flash Chip Enable (EF). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is Low, VIL, and Reset is High, VIH, the device is in active mode. When Chip Enable is at VIH the Flash memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level.

Flash Output Enable (GF). The Output Enable input controls data output during Flash memory Bus Read operations.

). The Write Enable controls the Bus Write operation of the Flash memories’ Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first.

Flash Write Protect (WPF). Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is Low, VIL, Lock-Down is enabled and the protection status of the Locked-Down blocks cannot be changed. When Write Protect is at High, VIH, Lock-Down is disabled and the Locked-Down blocks can be

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locked or unlocked. (See the Lock Status Table in the M30L0R7000T0 datasheet).

Flash Reset (RPF). The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in Reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current IDD2. Refer to Table 7., Flash Memory DC Characteristics - Cur-

rents, for the value of IDD2. After Reset all blocks are in the Locked state and the Configuration Reg-

ister is reset. When Reset is at VIH, the device is in normal operation. Exiting Reset mode the device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs.

The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to VRPH (refer to Table 8., Flash Memory DC Characteristics - Voltages).

Flash Latch Enable (LF). Latch Enable latches the address bits on its rising edge. The address latch is transparent when Latch Enable is Low, VIL, and it is inhibited when Latch Enable is High, VIH. Latch Enable can be kept Low (also at board level) when the Latch Enable function is not required or supported.

Flash Clock (KF). The Clock input synchronizes the Flash memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge (rising or falling, according to the configuration settings) when Latch Enable is at VIL. Clock is don't care during Asynchronous Read and in write operations.

Flash Wait (WAITF). WAIT is a Flash output signal used during Synchronous Read to indicate whether the data on the output bus are valid. This output is high impedance when Flash Chip Enable

is at VIH or Flash Reset is at VIL. It can be configured to be active during the wait cycle or one clock

cycle in advance. The WAITF signal is not gated by Output Enable.

PSRAM Chip Enable (E1P). When asserted (Low), the Chip Enable, E1P, activates the memory state machine, address buffers and decoders, allowing Read and Write operations to be performed. When de-asserted (High), all other pins are ignored, and the device is put, automatically, in low-power Standby mode.

It is not allowed to set EF at VIL, E1P at VIL and E2P at VIH at the same time.

PSRAM Chip Enable (E2P). The Chip Enable, E2P, puts the device in Power-down mode (Deep Power-Down or a Partial Power-Down mode) when it is driven Low. Deep Power-down mode is the lowest power mode.