ST M36D0R6040T0, M36D0R6040B0 User Manual
查询M36D0R6040B0ZAI供应商
64 Mbit (4Mb x16, Multiple Bank, Page) Flash Memory
and 16 Mbit (1Mb x16) PSRAM, Multi-Chip Package
FEATURES SUMMARY
■ MULTI-CHIP PACKAGE
– 1 die of 64 Mbit (4Mb x 16) Flash Memory
– 1 die of 16 Mbit (1Mb x 16) Pseudo SRAM
■ SUPPLY VOLTAGE
DDF
= V
–V
■ LOW POWER CONSUMPTION
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code (Top Flash Configuration),
M36D0R6040T0: 8810h
– Device Code (Bottom Flas h
Configuration), M36D0R6040B0: 8811h
■ PACKAGE
– Compliant with Lead-Free Soldering
Processes
– Lead-Free Versions
FLASH MEMORY
■ PROGRAMMING TIME
– 8µs by Word typical for Fast Factory
Program
– Double/Quadruple Word Program option
– Enhanced Factory Program options
■ MEMORY BLOCKS
– Multiple Bank Memory Array: 4 Mbit
Banks
– Parameter Blocks (Top location)
■ ASYNCHRONOUS READ
– Asynchronous Page Read mode
– Random Access: 70ns
■ DUAL OPERATIONS
– Program Eras e in one Bank wh ile Rea d in
others
– No delay between Read and Write
operations
■ BLOCK LOCKING
– All blocks lock ed at Powe r-up
– Any combination of blocks can be locked
–WP
for Block Lock-Down
F
= 1.7V to 1.95V
DDP
M36D0R6040T0
M36D0R6040B0
Figure 1. Package
FBGA
Stacked TFBGA67 (ZAI)
12 x 8mm
■ SECURITY
– 128-bit user programmable OTP cells
– 64-bit unique device number
■ COMMON FLASH INTERFACE (CFI)
■ 100,000 PROGRAM/ERASE CYCLES per
BLOCK
PSRAM
■ ACCESS TIME: 70ns
■ LOW STANDBY CURRENT: 110µA
■ DEEP POWER DOWN CURRENT: 10µA
1/18December 2004
M36D0R6040T0, M36D0R6040B0
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Address Inputs (A0-A19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Address Inputs (A20-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Chip Enable (E
Flash Output Enable (G
Flash Write Enable (W
Flash Write Protect (WP
Flash Reset (RP
PSRAM Chip Enable (E1
PSRAM Chip Enable (E2
PSRAM Output Enable (G
PSRAM Write Enable (W
PSRAM Upper Byte Enable (UB
PSRAM Lower Byte Enable (LB
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
V
DDF
V
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DDP
Program Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
V
PPF
V
Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SS
).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
F
).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
F
).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
F
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
F
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
F
).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
P
).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
P
).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
P
).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
P
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
P
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
P
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Main Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
FLASH MEMORY COMPONENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PSRAM COMPONENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/18
M36D0R6040T0, M36D0R6040B0
Table 5. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 6. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 7. Flash Memory DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 8. Flash Memory DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 9. PSRAM DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. Stacked TFBGA67 12x8mm - 8x8 active ball array, 0.8mm pitch, Package Outline . . . 15
Table 10. Stacked TFBGA67 12x8mm - 8x8 ball array, 0.8mm pitch, Package Mechanical Data . 15
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 11. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3/18
M36D0R6040T0, M36D0R6040B0
SUMMARY DESCRIPTION
The M36D0R6040T0 and M 36D0R6040B0 combine two memory devices in a Multi-Chip Package:
a 64-Mbit, Multiple Bank Flash memory, the
M58WR064FT/B, and a 16-Mbit Pseudo SRAM,
the M69AR024B. Recommended operating conditions do not allow more than one memory to be active at the same time.
The memory is offered in a Stacked TFBGA67
(12 x 8mm, 8x8 ball array, 0.8mm pitch) package.
In addition to the stan dard version, the pac kages
are also available in Lead- free version , in comp liance with JEDEC Std J-STD-020 B, the ST ECOPACK 7191395 Specification, and the RoHS
(Restriction of Hazardous Substances) directive.
All packages are c omp lia nt with Le ad- fr ee so ld er ing processes.
The memory is supplied with all the bits erased
(set to ‘1’).
Figure 2. Logic Diagram
V
PPF
A0-A21
E
G
W
RP
V
DDF
22
F
F
F
F
V
DDP
16
DQ0-DQ15
Table 1. Signal Names
A0-A19 Common Address Inputs
DQ0-DQ15 Common Data Input/Output
V
DDF
V
PPF
V
SS
V
DDP
NC Not Connected Internally
Flash Memory Signals
A21-A20
E
F
G
F
W
F
RP
F
WP
F
PSRAM Signals
E1
P
G
P
W
P
E2
P
UB
P
LB
P
Flash Memory Powe r Sup ply
Common Flash Optional Supply
Voltage for Fast Program & Erase
Ground
PSRAM Power Supply
Address Inputs for the Flash memory
only
Chip Enable input
Output Enable input
Write Enable input
Reset input
Write Protect input
Chip Enable input
Output Enable input
Write Enable input
Power-down input
Upper Byte Enable inp ut
Lower Byte Enable inp ut
4/18
WP
E1
E2
UB
LB
G
W
F
P
P
P
P
P
P
M36D0R6040T
M36D0R6040B
V
SS
AI09200
Figure 3. TFBGA Connections (Top view through package)
M36D0R6040T0, M36D0R6040B0
AI09201
1211
109876543
NCNC
NC
SSF
V
A12
A13A11A20NC
A15 A14
DQ7
DQ14
P
W
DQ15A9A16
A8 A10
DQ5
DQ4
DQ6DQ13NCW
A21
DDF
V
DDP
V
P
E2
DQ12V
F
RP
DQ3DQ2
DQ10
DQ11A19WP
PPF
V
DQ1DQ0
DQ8
DQ9G
P
P
UB
P
E1
A1
A2A3A6A7A18
A17
NC
NCG
NC
F
SSF
V
F
E
A0A4NCNC
A5
F
21
NC
A
B
C
SSP
D
F
E
LB
F
P
G
NC
H
5/18
M36D0R6040T0, M36D0R6040B0
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram and Table 1., Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A19). Addresses A0-A19
are common inputs for the Flash Memory and
PSRAM components. T he Address Inputs select
the cells in the memory array to access during Bus
Read operations. During Bus Write operations
they control the command s sent to the Comma nd
Interface of the Flash memory internal state machine and they select the cells to access in the
PSRAM.
The Flash memory is acce ssed through the Chip
Enable signal (E
) signal, while the PSRAM is accessed
(W
F
through two Chip Enable signals (E1
and the Write Enable signal (W
Address Inputs (A20-A21). Addresses A20-A21
are inputs for the Fl ash Memo ry compon ent only.
The Flash Memory is acce ssed through the Chip
Enable signals (
(W
) signal.
F
Data Input/Output (DQ0-DQ15). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation or inputs a command
or the data to be progra mmed d uring a Write Bus
operation.
Flash Chip Enable (E
puts activate the memory control logics, input buffers, decoders and sense amplifiers. When Chip
Enable is Low, V
vice is in active mode. When Chip Enable is at V
the Flash memory is deselec ted, the outputs are
high impedance and the power consumption is reduced to the standby level.
Flash Output Enable (G
pins control data outputs during Flash memory
Bus Read operations.
Flash Write Enable (
controls the Bus Write operation of the Flash
memories’ Command Int erface. The data an d address inputs are latched on the rising edge of Chip
Enable or Write Enable whichever occurs first.
Flash Write Protect (WP
input that gives an additio nal hardware protection
for each block. When Write Protect is Low, V
Lock-Down is enabled and the protection status of
the Locked-Down blocks cannot be changed.
When Write Protect is a t High, V
disabled and the Locked-Down blocks can be
locked or unlocked. (Refer to Lock Status Table in
M58WR064F(T/B) datasheet).
Flash Reset (RP
hardware reset of the m emory. When Reset is at
V
, the memory is in Reset mode: the outputs are
IL
) and through the Wr ite Enable
F
and E2P)
P
).
P
E
) and through the Writ e Enable
F
). The Chip Enable in-
F
, and Reset is High, VIH, the de-
IL
). The Output Enable
F
W
). The Write Enable
F
). Write Protect is an
F
, Lock-Down is
IH
). The Reset input provides a
F
IH
IL
high impedance and the current consumption is
reduced to the Reset Supply Current I
Table 7.,Flash Memory DC Characteristics - Currents, for the value of I
. After Reset all b locks
DD2
are in the Locked state and the Configuration Register is reset. When Reset is at V
, the device is in
IH
normal operation. Exiti ng Reset mode the devic e
enters Asynchronous Read mode, but a nega tive
transition of Chip Enable or Latch Enable is required to ensure valid data outputs.
The Reset pin can be interfaced with 3V logic without any additional circui try. It can be tied to V
(refer to Table 8., Flash Memory DC Characteris-
tics - Voltages).
PSRAM Chip Enable (E1
(Low), the Chip Enable, E1
). When asserted
P
, activates the memo-
P
ry state machine, address buffers and decod ers,
allowing Read and Write operations to be performed. When de-asserted (High), all other pins
are ignored, and the device is put, automatically, in
low-power Standby mode.
PSRAM Chip Enable (E2
, puts the device i n Deep Power-down mode
E2
P
). The Chip Enable,
P
when it is driven Low. This is the lowest power
mode.
PSRAM Output Enable (G
able, G
, provides a h igh speed tri-state c ontrol,
P
). The Output En-
P
allowing fast read/write cycles to be achieved with
the common I/O data bus.
PSRAM Write Enable (W
W
, controls the Bus Wri te o per ati on of the mem -
P
). The Write Enable,
P
ory’s Command Interface.
PSRAM Upper Byte Enable (UB
Byte Enable, UB
, gates the data on the Upper
P
). The Upper
P
Byte Data Inputs/Outp uts (DQ8-DQ15) t o or from
the upper part of the selected address during a
Write or Read operation.
PSRAM Lower Byte Enable (LB
Byte Enable, LB
, gates the data on the Lower
P
). The Lower
P
Byte Data Inputs/Outputs (DQ0-DQ7) to or from
the lower part of the selected address during a
Write or Read operation.
V
Supply Voltage. V
DDF
provides the power
DDF
supply to the internal core of the Flash memory
component. It is the main power supplies for all
Flash memory operations (Read, Program and
,
Erase).
V
Supply Voltage. The V
DDP
Supply Volt-
DDP
age supplies the power for all operations (Read or
Write) and for driving the refresh logic, even when
the device is not being accessed.
V
Program Supply Voltage. V
PPF
PPF
Flash Memory control input and a Flash Mem ory
power supply pin. The two functions are selected
by the voltage range applied to the pin.
. Refer to
DD2
is both a
RPH
6/18
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