ST M36D0R6040T0, M36D0R6040B0 User Manual

M36D0R6040B0ZAI

M36D0R6040T0

M36D0R6040B0

64 Mbit (4Mb x16, Multiple Bank, Page) Flash Memory and 16 Mbit (1Mb x16) PSRAM, Multi-Chip Package

FEATURES SUMMARY

■MULTI-CHIP PACKAGE

–1 die of 64 Mbit (4Mb x 16) Flash Memory

–1 die of 16 Mbit (1Mb x 16) Pseudo SRAM

■SUPPLY VOLTAGE

–VDDF = VDDP = 1.7V to 1.95V

■LOW POWER CONSUMPTION

■ELECTRONIC SIGNATURE

–Manufacturer Code: 20h

–Device Code (Top Flash Configuration), M36D0R6040T0: 8810h

–Device Code (Bottom Flash Configuration), M36D0R6040B0: 8811h

■PACKAGE

–Compliant with Lead-Free Soldering Processes

–Lead-Free Versions

FLASH MEMORY

■PROGRAMMING TIME

–8µs by Word typical for Fast Factory Program

–Double/Quadruple Word Program option

–Enhanced Factory Program options

■MEMORY BLOCKS

–Multiple Bank Memory Array: 4 Mbit Banks

–Parameter Blocks (Top location)

■ASYNCHRONOUS READ

–Asynchronous Page Read mode

–Random Access: 70ns

■DUAL OPERATIONS

–Program Erase in one Bank while Read in others

–No delay between Read and Write operations

■BLOCK LOCKING

–All blocks locked at Power-up

–Any combination of blocks can be locked

–WPF for Block Lock-Down

Figure 1. Package

FBGA

Stacked TFBGA67 (ZAI)

12 x 8mm

■SECURITY

–128-bit user programmable OTP cells

–64-bit unique device number

■COMMON FLASH INTERFACE (CFI)

■100,000 PROGRAM/ERASE CYCLES per BLOCK

PSRAM

■ACCESS TIME: 70ns

■LOW STANDBY CURRENT: 110µA

■DEEP POWER DOWN CURRENT: 10µA

December 2004

1/18

M36D0R6040T0, M36D0R6040B0

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Address Inputs (A0-A19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Address Inputs (A20-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Flash Chip Enable (EF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Flash Output Enable (GF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Flash Write Enable (WF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Flash Write Protect (WPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Flash Reset (RPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PSRAM Chip Enable (E1P).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PSRAM Chip Enable (E2P).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PSRAM Output Enable (GP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PSRAM Write Enable (WP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PSRAM Upper Byte Enable (UBP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PSRAM Lower Byte Enable (LBP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

VDDF Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

VDDP Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

VPPF Program Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

VSS Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2. Main Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

FLASH MEMORY COMPONENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PSRAM COMPONENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 4. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

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M36D0R6040T0, M36D0R6040B0

Table 5. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 6. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 7. Flash Memory DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 8. Flash Memory DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 9. PSRAM DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 6. Stacked TFBGA67 12x8mm - 8x8 active ball array, 0.8mm pitch, Package Outline . . . 15 Table 10. Stacked TFBGA67 12x8mm - 8x8 ball array, 0.8mm pitch, Package Mechanical Data . 15

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 11. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

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M36D0R6040T0, M36D0R6040B0

SUMMARY DESCRIPTION

The M36D0R6040T0 and M36D0R6040B0 combine two memory devices in a Multi-Chip Package: a 64-Mbit, Multiple Bank Flash memory, the M58WR064FT/B, and a 16-Mbit Pseudo SRAM, the M69AR024B. Recommended operating conditions do not allow more than one memory to be active at the same time.

The memory is offered in a Stacked TFBGA67 (12 x 8mm, 8x8 ball array, 0.8mm pitch) package.

In addition to the standard version, the packages are also available in Lead-free version, in compliance with JEDEC Std J-STD-020B, the ST ECOPACK 7191395 Specification, and the RoHS (Restriction of Hazardous Substances) directive.

All packages are compliant with Lead-free soldering processes.

The memory is supplied with all the bits erased (set to ‘1’).

Figure 2. Logic Diagram

VPPF

VDDF VDDP

22	16

A0-A21

DQ0-DQ15

EF

GF

WF

RPF

WPF

E1P

GP M36D0R6040T

M36D0R6040B

WP

E2P

UBP

LBP

VSS

AI09200

4/18

Table 1. Signal Names

	A0-A19								Common Address Inputs
	DQ0-DQ15								Common Data Input/Output
	VDDF								Flash Memory Power Supply
	VPPF								Common Flash Optional Supply
									Voltage for Fast Program & Erase
	VSS								Ground
	VDDP								PSRAM Power Supply
	NC								Not Connected Internally
	Flash Memory Signals
	A21-A20								Address Inputs for the Flash memory
									only
		F
	E								Chip Enable input
				F
	G								Output Enable input
					F
	W								Write Enable input
							F
	RP								Reset input
								F
	WP								Write Protect input
	PSRAM Signals
	E1					P			Chip Enable input
				P
	G								Output Enable input
					P
	W								Write Enable input
	E2P								Power-down input
							P
	UB								Upper Byte Enable input
						P
	LB								Lower Byte Enable input

	1	2	3
A	NC	NC	A20
B			A16
C			WF
D			VSSP
E			WPF
F			LBP
G			A18
H	NC	NC	NC

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4

A11

A8

NC

RPF

VPPF

UBP

A17

A5

5	6	7	8
A15	A14	A13	A12
A10	A9	DQ15	WP
A21		DQ13	DQ6
		DQ12	E2P
A19	DQ11		DQ10
GP		DQ9	DQ8
A7	A6	A3	A2
A4	A0	EF	VSSF

9

VSSF

DQ14

DQ4

VDDP

DQ2

DQ0

A1

GF

10

11

12

NC NC NC

DQ7

DQ5

VDDF

DQ3

DQ1

E1P

NC NC NC

AI09201

package) through view (Top Connections TFBGA .3 Figure

M36D0R6040B0 M36D0R6040T0,

Flash Write Enable (WF

M36D0R6040T0, M36D0R6040B0

SIGNAL DESCRIPTIONS

See Figure 2., Logic Diagram and Table 1., Signal Names, for a brief overview of the signals connected to this device.

Address Inputs (A0-A19). Addresses A0-A19 are common inputs for the Flash Memory and PSRAM components. The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Flash memory internal state machine and they select the cells to access in the PSRAM.

The Flash memory is accessed through the Chip Enable signal (EF) and through the Write Enable (WF) signal, while the PSRAM is accessed through two Chip Enable signals (E1P and E2P) and the Write Enable signal (WP).

Address Inputs (A20-A21). Addresses A20-A21 are inputs for the Flash Memory component only. The Flash Memory is accessed through the Chip Enable signals (EF) and through the Write Enable (WF) signal.

Data Input/Output (DQ0-DQ15). The Data I/O outputs the data stored at the selected address during a Bus Read operation or inputs a command or the data to be programmed during a Write Bus operation.

Flash Chip Enable (EF). The Chip Enable inputs activate the memory control logics, input buffers, decoders and sense amplifiers. When Chip Enable is Low, VIL, and Reset is High, VIH, the device is in active mode. When Chip Enable is at VIH the Flash memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level.

Flash Output Enable (GF). The Output Enable pins control data outputs during Flash memory Bus Read operations.

). The Write Enable controls the Bus Write operation of the Flash memories’ Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first.

Flash Write Protect (WPF). Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is Low, VIL, Lock-Down is enabled and the protection status of the Locked-Down blocks cannot be changed. When Write Protect is at High, VIH, Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (Refer to Lock Status Table in M58WR064F(T/B) datasheet).

Flash Reset (RPF). The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in Reset mode: the outputs are

6/18

high impedance and the current consumption is reduced to the Reset Supply Current IDD2. Refer to Table 7., Flash Memory DC Characteristics - Cur-

rents, for the value of IDD2. After Reset all blocks are in the Locked state and the Configuration Reg-

ister is reset. When Reset is at VIH, the device is in normal operation. Exiting Reset mode the device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs.

The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to VRPH (refer to Table 8., Flash Memory DC Characteristics - Voltages).

PSRAM Chip Enable (E1P). When asserted (Low), the Chip Enable, E1P, activates the memory state machine, address buffers and decoders, allowing Read and Write operations to be performed. When de-asserted (High), all other pins are ignored, and the device is put, automatically, in low-power Standby mode.

PSRAM Chip Enable (E2P). The Chip Enable, E2P, puts the device in Deep Power-down mode when it is driven Low. This is the lowest power mode.

PSRAM Output Enable (GP). The Output Enable, GP, provides a high speed tri-state control, allowing fast read/write cycles to be achieved with the common I/O data bus.

PSRAM Write Enable (WP). The Write Enable, WP, controls the Bus Write operation of the memory’s Command Interface.

PSRAM Upper Byte Enable (UBP). The Upper Byte Enable, UBP, gates the data on the Upper Byte Data Inputs/Outputs (DQ8-DQ15) to or from the upper part of the selected address during a Write or Read operation.

PSRAM Lower Byte Enable (LBP). The Lower Byte Enable, LBP, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-DQ7) to or from the lower part of the selected address during a Write or Read operation.

VDDF Supply Voltage. VDDF provides the power supply to the internal core of the Flash memory component. It is the main power supplies for all Flash memory operations (Read, Program and Erase).

VDDP Supply Voltage. The VDDP Supply Voltage supplies the power for all operations (Read or Write) and for driving the refresh logic, even when the device is not being accessed.

VPPF Program Supply Voltage. VPPF is both a Flash Memory control input and a Flash Memory power supply pin. The two functions are selected by the voltage range applied to the pin.