ST M35B32 User Manual
32 Kbit, 256-byte page, fast program EEPROM memory
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
UFDFPN8 (MC)
2 x 3 mm
Features
■ SPI bus compatible serial interface
■ 32 Kbit of EEPROM divided into two sectors:
– Data sector
– Event sector
■ Large page size: 256 bytes
■ Fast programming:
– Event sector: 256 bytes programmed in
less than 1 ms
– Data sector: 256 bytes written in less than
5ms
■ Low energy EEPROM in either Read, Write,
Program or Erase modes
■ 2.5 V to 5.5 V single supply voltage
■ Operating temperature range:
– –40°C to +85°C
– –40°C to +125°C
■ Operating frequency, f
■ Electronic signature: 20 10 0Ch
■ Data cycling:
– Data sector: more than 1 Million write
cycles
– Event sector: more than 10 000 write
cycles
■ Data retention:
– Data sector: more than 40 years’ data
retention
– Event sector: 1 year
■ Packages
–ECOPACK
® (RoHS compliant)
= 20 MHz
C
M35B32
accessed by SPI bus interface
Target specification
May 2011 Doc ID 18391 Rev 3 1/42
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
www.st.com
1
Contents M35B32
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Chip Select (S
2.5 Reset (RESET
2.6 Write Protect (W
2.7 V
2.8 V
supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CC
ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SS
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 An easy way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 A fast way to store data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 Polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . . 12
4.4 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.3 Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4.3 BPi bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.5 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.6 Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.7 Page Write (PW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2/42 Doc ID 18391 Rev 3
M35B32 Contents
6.8 Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.9 ECC (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . . . 26
6.10 Page Erase (PE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.11 Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7 Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.1 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.1.1 Operating supply voltage V
7.1.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.1.3 Internal reset during power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.1.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
11 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
12 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Doc ID 18391 Rev 3 3/42
List of tables M35B32
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 3. Read Identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 4. Value of the WEL bit after decoding a Page Write, Page Program, Page
Erase or Sector Erase instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 6. Operating conditions (range 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 7. Operating conditions (range 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 8. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 9. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 10. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 11. AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 12. SO8N – 8-lead plastic small outline, 150 mils body width, mechanical data . . . . . . . . . . . 37
Table 13. TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 38
Table 14. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 15. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 16. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4/42 Doc ID 18391 Rev 3
M35B32 List of figures
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. Bus master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Write Enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8. Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9. Read Identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 18
Figure 10. Read Status Register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . 20
Figure 11. Write Status Register (WRSR) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12. Read Data Bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 22
Figure 13. Page Write (PW) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14. Page Program (PP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 15. Page Erase (PE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 16. Sector Erase (SE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 17. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 18. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 19. Write Protect setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 20. Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 21. Reset AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 22. SO8N – 8-lead plastic small outline, 150 mils body width, package outline. . . . . . . . . . . . 37
Figure 23. TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 24. Ultra thin Fine pitch Dual Flat Package No lead (UFDFPN8), 2 × 3mm
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Doc ID 18391 Rev 3 5/42
Description M35B32
RESET
AI15472
S
V
CC
M35B32
V
SS
W
Q
C
D
1 Description
The M35B32 is a 32-Kbit electrically erasable programmable memory (EEPROM) accessed
through the SPI bus.
The M35B32 is able to save and store up to 256 bytes within a very short time with the help
of the Event sector, this feature being convenient in cases of an unexpected power loss or if
an urgent data storage is required. The fast storage is performed with a very low energy
budget as the Program time lasts less than 1 ms and as the supply voltage can be as low as
2.5 V associated with a low Programming current (the M35B32 is based on EEPROM cells,
energy-saving technology when compared to the Flash technology).
Memory organization
The M35B32 is split into two sectors:
● the Data sector: standard EEPROM which can be written
a time) with a standard write time and a standard retention time,
● the Event sector: data bytes which can be programmed
time) with a fast programming time and a limited retention time.
The time required to update data is significantly reduced by the Page size (256 bytes) as a
page is updated in a single shot.
(a)
by page (1 to 256 bytes at
(b)
by page (1 to 256 bytes at a
Both Data sector and Event sector can be erased either a page at a time (using the Page
Erase instruction) or a sector at a time (using the Sector Erase instruction).
The size of each sector is defined by the user.
Figure 1. Logic diagram
a. Write cycle = 2 cycles = Erase + Program
b. Program cycle = single cycle (a Write cycle includes two cycles: Erase cycle + Program cycle)
6/42 Doc ID 18391 Rev 3
M35B32 Description
1
AI14872
2
3
4
8
7
6
5
RESET
DV
SS
C
Q
S
V
CC
W
Figure 2. 8-pin package connections
1. See Package mechanical data section for package dimensions, and how to identify pin-1.
Table 1. Signal names
Signal name Function Direction
C Serial Clock Input
D Serial Data input Input
Q Serial Data output Output
S Chip Select Input
W
RESET
Write Protect Input
Reset Input
V
CC
V
SS
Supply voltage
Ground
Doc ID 18391 Rev 3 7/42
Signal description M35B32
2 Signal description
During all operations, VCC must be held stable and within the specified valid range:
V
(min) to VCC(max).
CC
All of the input and output signals must be held high or low (according to voltages of V
V
, VIL or VOL, as specified in Ta bl e 1 0 ). These signals are described below.
OH
2.1 Serial Data output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
2.2 Serial Data input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be programmed. Values are latched on the rising edge of Serial
Clock (C).
,
IH
2.3 Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
2.4 Chip Select (S)
When this input signal is high, the device is deselected and Serial Data Output (Q) is at high
impedance. Unless an internal Read, Program, Erase or Write cycle is in progress, the
device will be in the Standby Power mode (this is not the Deep Power-down mode). Driving
Chip Select (S
After Power-up, a falling edge on Chip Select (S
instruction.
) low selects the device, placing it in the Active Power mode.
2.5 Reset (RESET)
The Reset (RESET) input provides a hardware reset for the memory. In this mode, the
device is in Standby mode, the WEL and WIP bits are reset (to 0) and the outputs are high
impedance.
When Reset (RESET
Reset (RESET
) is driven high, the memory is in the normal operating mode. When
) is driven low, the memory will enter the Reset mode
) is required prior to the start of any
(c)
.
c. If the M35A32 is executing a Write (pr program) cycle), the RESET pin driven active (low) does not stop an on
going Program or Write cycle.
8/42 Doc ID 18391 Rev 3
M35B32 Signal description
2.6 Write Protect (W)
This input signal puts the device in the Hardware Protected mode, when Write Protect (W) is
driven low (V
write, program and erase operations). When Write Protect (W
Kbytes of EEPROM memory can be accessed in Read and Write mode.
), causing the Event sector to become read-only (by protecting them from
IL
) is driven high (VIH), the 4
2.7 VCC supply voltage
VCC is the supply voltage. (See also Section 7 for more)
2.8 VSS ground
VSS is the reference for the VCC supply voltage.
Doc ID 18391 Rev 3 9/42
SPI modes M35B32
AI01438B
C
MSB
CPHA
D
0
1
CPOL
0
1
Q
C
MSB
3 SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
● CPOL=0, CPHA=0
● CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 3, is the clock polarity when the
bus master is in Standby mode and not transferring data:
● C remains at 0 for (CPOL=0, CPHA=0)
● C remains at 1 for (CPOL=1, CPHA=1)
Figure 3. SPI modes supported
10/42 Doc ID 18391 Rev 3
M35B32 SPI modes
30)"US-ASTER
30)-EMORY
$EVICE
3$/
3$)
3#+
#1$
3
30)-EMORY
$EVICE
#1$
3
30)-EMORY
$EVICE
#1$
3
#3 #3 #3
30))NTERFACEWITH
#0/,#0(!
OR
7
2%3%4
7
2%3%4
7
2%3%4
22 2
6
##
6
##
6
##
6
##
6
33
6
33
6
33
6
33
2
2EFERTO.OTE 2EFERTO.OTE
2EFERTO.OTE
Figure 4. Bus master and memory devices on the SPI bus
Note: 1 The /W and /RESET inputs are CMOS inputs and have also to be driven high or low if/when the SPI
bus master leaves the lines in high impedance. This has to be done with the help of pull up or pull
down resistors (depending on the application requirements).
Figure 4 shows an example of three devices connected to an MCU, on an SPI bus. Only one
device is selected at a time, so only one device drives the Serial Data Output (Q) line at a
time, the other devices are high impedance.
A pull-up resistor connected on each /S input (represented in Figure 4) ensures that each
slave device on the SPI bus is not selected if the bus master leaves the /S line in the high
impedance state.
In applications where the bus master might enter a state where all inputs/outputs SPI lines
are in high impedance at the same time (for example, if the Bus Master is reset during the
transmission of an instruction), the clock line (C) must be connected to an external pulldown resistor so that, if all inputs/outputs become high impedance, the C line is pulled low
(while the S
time, and so, that the t
line is pulled high). This ensures that S and C do not become high at the same
requirement is met.
SHCH
Doc ID 18391 Rev 3 11/42
Operating features M35B32
4 Operating features
4.1 An easy way to modify data
The Page Write (PW) instruction provides a convenient way of modifying data (1 up to 256
contiguous bytes at a time), and simply requires the start address, and the new data in the
instruction sequence.
4.2 A fast way to store data
The Page Program (PP) instruction provides a fast way of modifying the data (1 up to 256
contiguous bytes at a time) in the Event sector, provided that these data bytes were erased
(by the completion of an earlier Page Erase instruction).
When addressing the Event sector (Sector 0, see Figure 5), the Page Program instruction is
executed in a very short time (t
executing a Page Program (or Page Write) instruction in the Data sector.
To be correctly used, the Event sector has to be first erased. When an event occurs, data
are programmed in the Event sector within a fast time. Later on, when the device receives
less requests from the application, the contents of the Event sector can be copied/written
into the Data sector (to benefit from the standard data retention time of 40 years), after what
the Event sector content can be erased (using only one instruction: the Sector Erase
instruction).
, see Ta bl e 1 1 ), that is about 5 times faster than when
FP
4.3 Polling during a write, program or erase cycle
A further improvement in the write, program or erase time can be achieved by not waiting for
the worst case delay (t
Status Register so that the application program can monitor its value, polling it to establish
when the previous cycle is complete.
, tPP, tPE, or tSE). The write in progress (WIP) bit is provided in the
PW
12/42 Doc ID 18391 Rev 3
M35B32 Operating features
4.4 Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M35B32 features the following data protection mechanisms:
● Power on reset can provide protection against inadvertent changes while the power
supply is outside the operating specification.
● Program, Erase and Write instructions are checked that they consist of a number of
clock pulses that is a multiple of eight, before they are accepted for execution.
● All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the WEL bit (in the status register). This bit is returned to its reset
state by the following events:
–Power-up
– Reset (RESET
– Write Disable (WRDI) instruction completion
– Page Write (PW) instruction completion
– Page Program (PP) instruction completion
– Page Erase (PE) instruction completion
– Sector Erase (SE) instruction completion
● The Hardware Protected mode is entered when Write Protect (W) is driven low, causing
the Event sector to become read-only. When Write Protect (W
Kbytes of EEPROM memory can be accessed in Read and Write mode.
● The Reset (RESET) signal can be driven low to protect the contents of the memory
during any critical time, not just during Power-up and Power-down. When driven active
(low), the RESET pin does not stop an on going Program or Write cycle.
) driven low
) is driven high, the 4
Doc ID 18391 Rev 3 13/42
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