ST M34F04 User Manual
With Hardware Write Control on Top Half of Memory
FEATURES SUMMARY
■ Two Wire I
Supports 400 kHz Protocol
■ 2.5 to 5.5V Single Supply Voltage:
■ Hardware Write Control of the top half of
memory (addresses 100h to 1FFh)
■ BYTE and PAGE WRITE (up to 16 Bytes)
■ RANDOM and SEQUENTIAL READ Modes
■ Self-Timed Programming Cycle
■ Automatic Address Incrementing
■ Enhanced ESD/Latch-Up Behavior
■ More than 1 Million Erase/Write Cycles
■ More than 40 Year Data Retention
■ SO8 Package
– ECOPACK® (RoHS compliant)
2
C Serial Interface
M34F04
4Kbit Serial I²C Bus EEPROM
Figure 1. Packages
SO8 (MN)
150 mil width
1/21January 2006
M34F04
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. SO Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Data (SDA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chip Enable (E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Write Control (WC
Supply voltage (V
Operating supply voltage V
Internal device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Power-down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus . . . . . . . . . . . . . . . 6
Figure 5. I2C Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Device Select Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
CC
CC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DEVICE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Stop Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Acknowledge Bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Data Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. Write Mode Sequences, to Addresses in the Top Half, with WC=1 (data write inhibited). 9
Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Byte Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Write Mode Sequences with WC=0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 8. Write Cycle Polling Flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Minimizing System Delays by Polling On ACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 9. Read Mode Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Random Address Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Sequential Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Acknowledge in Read Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2/21
M34F04
Table 4. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 7. Input Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 8. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 9. AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11.AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12.SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . .18
Table 10. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width,
Package Mechanical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 11. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3/21
M34F04
SUMMARY DESCRIPTION
The M34F04 is an electrically erasable programmable memory (EEPROM), organized as 512 x 8.
2
These devices are compatible with the I
C memory protocol. This is a two wire serial interface that
uses a bi-directional data bus and serial clo ck. The
devices carry a built-in 4-bit Device Type Identifier
code (1010) in accordance with the I
2
C bus defini-
tion.
2
The device behaves as a slave in the I
C protocol,
with all memory operations synchronized by the
serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a Device
Select Code and RW
bit (as described in Table 2),
terminated by an acknowledge bit.
When writing data to the memory, the device in-
serts an acknowledge bit during the 9
th
bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
In order to meet environmental requirements, ST
offers these devices in ECOPACK® packages.
ECOPACK® packages are Lead-free and RoHS
compliant.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Table 1. Signal Names
E1, E2 Chip Enable
SDA Serial Data
SCL Serial Clock
WC
V
CC
V
SS
Write Control
Supply Voltage
Ground
Figure 3. SO Connections
M34F04
NC V
1
2
E2
3
4
SS
AI09073
8
CC
WCE1
7
SCL
6
SDAV
5
Figure 2. Logic Diagram
V
CC
2
E1-E2 SDA
SCL
WC
M34F04
V
SS
Note: 1. NC = Not Connected
2. See PACKAGE MECHANICAL for package dimensions,
and how to identify pin-1.
AI09072
4/21
SIGNAL DESCRIPTION
M34F04
Serial Clock (SCL)
This input signal is used to strobe all data in and
out of the device. In applications where this signal
is used by slave devices to synchronize the bus to
a slower clock, the bus master must have an open
drain output, and a pull-up resistor can be connected from Serial Clock (SCL) to V
. (Figure 4
CC
indicates how the value of the pull-up resistor can
be calculated). In most applicat ions, though, this
method of synchronization is not employed, and
so the pull-up resistor is not necessary, provided
that the bus master has a push-pull (rather than
open drain) output.
Serial Data (SDA)
This bi-directional signal is used to transfer data in
or out of the device. It is an open drain output that
may be wire-OR’ed with other open drain or open
collector signals on the bus. A pull up resistor must
be connected from Serial Data (SDA) to V
CC
. (Figure 4 indicates how the value of the pull-up resistor
can be calculated).
Chip Enable (E1, E2)
These input signals are used t o set the va lue that
is to be looked for on the three least significant bits
(b3, b2) of the 7-bit Device Select Code. These inputs must be tied to V
or VSS, to establish the
CC
Device Select Code.
) is driven High. When unconnected, the sig-
(WC
nal is internally read as V
, and Write operations
IL
are allowed.
When attempting to write in the upper half of the
memory, while Write Control (WC) is being driven
High, Device Select and Address bytes are acknowledged, Data bytes are not acknowledged.
Supply voltage (V
Operating supply voltage V
CC
)
. Prior to select-
CC
ing the memory and issuing instructions to it, a valid and stable V
voltage must be applied: this
CC
voltage must be a DC voltage within the specified
(min), VCC(max)] range as defined in Table 5.
[V
CC
This voltage must remain stable and valid until the
end of the transmission of the instruction and, for
a Write instruction, until the completion of the internal write cycle (t
).
W
Internal device reset. In order to prevent inadvertent Write operations during Power-up, a Power On Reset (POR) circuit is included. At Power-up
(continuous rise of V
spond to any instruction until V
), the device will not re-
CC
has reached the
CC
Power On Reset threshold voltage (this threshold
is lower than the minimum V
operating voltage
CC
defined in Section 9: DC and AC parameters).
When V
has passed the POR threshold voltage,
CC
the device is reset and in the Standby Power
mode.
Write Control (WC
)
This input signal is useful for protecting half of the
memory from inadvertent write operations. Write
operations are disabled to the upper half (1FFh to
100h) of the memory array when Write Control
Power-down. At Power-down (where V
creases continuously), as soon as V
CC
de-
CC
drops from
the normal operating voltage to below the Power
On Reset threshold voltage, the device stops responding to any instruction sent to it.
5/21
M34F04
Figure 4. Maximum RL Value versus Bus Capacitance (C
20
16
12
8
Maximum RP value (kΩ)
4
0
10
Figure 5. I
2
C Bus Protocol
SCL
C
BUS
fc = 400kHz
100
(pF)
fc = 100kHz
) for an I2C Bus
BUS
V
MASTER
1000
CC
SDA
SCL
R
R
L
C
BUS
L
C
BUS
AI01665
SDA
SCL
SDA
SCL
SDA
START
Condition
START
Condition
1 23 7 89
MSB
1 23 7 89
MSB
SDA
Input
SDA
Change
STOP
Condition
ACK
ACK
STOP
Condition
AI00792B
6/21
M34F04
Table 2. Device Select Code
Device Type Identifier
(1)
Chip Enable
b7 b6 b5 b4 b3 b2 b1 b0
Device Select Code 1 0 1 0 E2 E1 A8 RW
Note: 1. The most significant bit, b7, is sent first.
2. E1 and E2 are compared against the respective external pins on the memory device.
3. A8 represents most significant bits of the address.
(2,3)
RW
7/21
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